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vc/intel/fsp/fsp2_0/graniterapids: Update to formal FSP header files

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Change-Id: I6e94f44d50f2b53855adc1bb1cd6a1a5d9929003
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This commit is contained in:
Jincheng Li 2024-09-25 14:41:56 +08:00 • committed by Lean Sheng Tan
commit 87436bc4dd
40 changed files with 4471 additions and 3267 deletions
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16
src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/CxlNodeHob.h
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@ -1,6 +1,6 @@
/** @file
Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -26,25 +26,32 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _CXL_NODE_HOB_
#define _CXL_NODE_HOB_
#define CXL_NODE_HOB_GUID { 0xdd8ae009, 0xda5a, 0x44a3, { 0xbe, 0x18, 0xda, 0x0c, 0x16, 0xc5, 0xaf, 0x5c } }
#define CXL_NODE_HOB_GUID { 0xdd8ae009, 0xda5a, 0x44a3, { 0xbe, 0x18, 0xda, 0x0c, 0x16, 0xc5, 0xaf, 0x5c } }
#ifndef MAX_IIO_STACK
#define MAX_IIO_STACK 16
#endif
#ifndef MAX_CXL_HDM_RANGES
#define MAX_CXL_HDM_RANGES 0x2 // Maximum number of CXL HDM ranges per CXL end device.
#endif
#ifndef MAX_CXL_PER_SOCKET
#define MAX_CXL_PER_SOCKET 8
#define MAX_CXL_PER_SOCKET MAX_IIO_STACK
#endif
#define CXL_NODE_ATTR_MEM BIT0
#define CXL_NODE_ATTR_PERSISTENT BIT1
#define CXL_NODE_ATTR_MEM_HW_INIT BIT2
#define CXL_NODE_ATTR_ACCELERATOR BIT3
#define CXL_NODE_ATTR_HOT_PLUGGABLE BIT4
typedef UINT32 CXL_NODE_ATTR;
@ -75,6 +82,7 @@ typedef struct {
UINT32 Size;
UINT8 Ways;
UINT8 SocketBitmap;
BOOLEAN AcpiSratSpMemFlag;
CXL_EFI_MEM_TYPE EfiMemType;
CXL_PERF_DATA InitiatorPerfData; // Performance data between device egress and initiator.
CXL_PERF_DATA TargetPerfData; // Performance data of entire target memory region.
@ -86,7 +94,7 @@ typedef struct {
//
// CXL node info for UEFI memory map and ACPI tables construction
//
CXL_NODE_INFO CxlNodeInfo[MAX_CXL_PER_SOCKET * MAX_CXL_HDM_RANGES];
CXL_NODE_INFO CxlNodeInfo[MAX_IIO_STACK * MAX_CXL_HDM_RANGES];
} CXL_NODE_SOCKET;
#pragma pack()

169
src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/EnhancedWarningLogLib.h
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@ -1,169 +0,0 @@
/** @file
Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef _ENHANCED_WARNING_LOG_LIB_
#define _ENHANCED_WARNING_LOG_LIB_
#define FSP_RESERVED_LEN 12
#pragma pack(1)
///
/// Enhanced Warning Log Header
///
typedef struct {
EFI_GUID EwlGuid; /// GUID that uniquely identifies the EWL revision
UINT32 Size; /// Total size in bytes including the header and buffer
UINT32 FreeOffset; /// Offset of the beginning of the free space from byte 0
/// of the buffer immediately following this structure
/// Can be used to determine if buffer has sufficient space for next entry
UINT32 Crc; /// 32-bit CRC generated over the whole size minus this crc field
/// Note: UEFI 32-bit CRC implementation (CalculateCrc32) (References [7])
/// Consumers can ignore CRC check if not needed.
UINT32 Reserved; /// Reserved for future use, must be initialized to 0
} EWL_HEADER;
///
/// List of all entry types supported by this revision of EWL
///
typedef enum {
EwlType0 = 0,
EwlType1 = 1,
EwlType2 = 2,
EwlType3 = 3,
EwlType4 = 4,
EwlType5 = 5,
EwlType6 = 6,
EwlType7 = 7,
EwlType8 = 8,
EwlType9 = 9,
EwlType10 = 10,
EwlType11 = 11,
EwlType12 = 12,
EwlType13 = 13,
EwlType14 = 14,
EwlType15 = 15,
EwlType16 = 16,
EwlType17 = 17,
EwlType18 = 18,
EwlType19 = 19,
EwlType20 = 20,
EwlType21 = 21,
EwlType22 = 22,
EwlType23 = 23,
EwlType24 = 24,
EwlType25 = 25,
EwlType26 = 26,
EwlType27 = 27,
EwlType28 = 28,
EwlType29 = 29,
EwlType30 = 30,
EwlType31 = 31,
EwlType32 = 32,
EwlTypeMax,
EwlTypeOem = 0x8000,
EwlTypeDelim = MAX_INT32
} EWL_TYPE;
///
/// EWL severities
///
typedef enum {
EwlSeverityInfo,
EwlSeverityWarning,
EwlSeverityFatal,
EwlSeverityMax,
EwlSeverityDelim = MAX_INT32
} EWL_SEVERITY;
///
/// Generic entry header for parsing the log
///
typedef struct {
EWL_TYPE Type;
UINT16 Size; /// Entries will be packed by byte in contiguous space
EWL_SEVERITY Severity; /// Warning, error, informational, this may be extended in the future
} EWL_ENTRY_HEADER;
///
/// Legacy content provides context of the warning
///
typedef struct {
UINT8 MajorCheckpoint; // EWL Spec - Appendix B
UINT8 MinorCheckpoint;
UINT8 MajorWarningCode; // EWL Spec - Appendix A
UINT8 MinorWarningCode;
} EWL_ENTRY_CONTEXT;
///
/// Legacy content to specify memory location
///
typedef struct {
UINT8 Socket; /// 0xFF = n/a
UINT8 Channel; /// 0xFF = n/a
UINT8 PseudoChannel; /// 0xFF = n/a
UINT8 Dimm; /// 0xFF = n/a
UINT8 Rank; /// 0xFF = n/a
} EWL_ENTRY_MEMORY_LOCATION;
///
/// Type 3 = Enhanced type for command, control IO errors
///
typedef struct {
EWL_ENTRY_HEADER Header;
EWL_ENTRY_CONTEXT Context;
EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
UINT8 reserved1[FSP_RESERVED_LEN]; // MRC_LT Level; MRC_GT Group; GSM_CSN Signal;
UINT8 EyeSize; // 0xFF = n/a
} EWL_ENTRY_TYPE3;
#pragma pack()
///
/// Enhanced Warning Log Spec defined data log structure
///
typedef struct {
EWL_HEADER Header; /// The size will vary by implementation and should not be assumed
UINT8 Buffer[4 * 1024]; /// The spec requirement is that the buffer follow the header
} EWL_PUBLIC_DATA;
///
/// EWL private data structure. This is going to be implementation dependent
/// When we separate OEM hooks via a PPI, we can remove this
///
typedef struct {
UINT32 bufSizeOverflow; // Number of bytes that could not be added to buffer
UINT32 numEntries; // Number of entries currently logged
EWL_PUBLIC_DATA status; // Spec defined EWL
} EWL_PRIVATE_DATA;
#endif // #ifndef _ENHANCED_WARNING_LOG_LIB_

59
src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FirmwareVersionInfoHob.h
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@ -1,59 +0,0 @@
/** @file
Header file for Firmware Version Information
@copyright
Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
#define _FIRMWARE_VERSION_INFO_HOB_H_
#include <Uefi/UefiMultiPhase.h>
#include <Pi/PiBootMode.h>
#include <Pi/PiHob.h>
#pragma pack(1)
///
/// Firmware Version Structure
///
typedef struct {
UINT8 MajorVersion;
UINT8 MinorVersion;
UINT8 Revision;
UINT16 BuildNumber;
} FIRMWARE_VERSION;
///
/// Firmware Version Information Structure
///
typedef struct {
UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
} FIRMWARE_VERSION_INFO;
#ifndef __SMBIOS_STANDARD_H__
///
/// The Smbios structure header.
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Handle;
} SMBIOS_STRUCTURE;
#endif
///
/// Firmware Version Information HOB Structure
///
typedef struct {
EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
UINT8 Count; ///< Offset 28 Number of FVI elements included.
///
/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
///
} FIRMWARE_VERSION_INFO_HOB;
#pragma pack()
#endif // _FIRMWARE_VERSION_INFO_HOB_H_

21
src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspAcpiHobs.h
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@ -1,6 +1,6 @@
/** @file
Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -26,15 +26,28 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _FSP_ACPI_HOBS_H_
#define _FSP_ACPI_HOBS_H_
#ifndef __FSP_ACPI_HOBS__
#define __FSP_ACPI_HOBS__
//Typecast HOB pointer to APEI table structure of ACPI version 6.2
#define FSP_RAS_ACPI_HOB_GUID { 0x826785ee, 0xa8e0, 0x4d8f, { 0x82, 0x6f, 0x54, 0x29, 0x2c, 0xe7, 0x6f, 0xe6 } }
//Typecast HOB pointer to ACPI CXL CEDT table structure
#define FSP_CXL_CEDT_ACPI_HOB_GUID { 0x5CB7A12A, 0x8B2D, 0x485A, { 0xB7, 0x04, 0xC0, 0x52, 0x49, 0x56, 0x81, 0xE7 } }
// Typecast HOB pointer to MEM_TRAINING_DATA_HOB_HEADER.
// User with NDA clearance should refer to RC code for latest structure definition.
#define FSP_MEM_TRAINING_DATA_HOB_GUID { 0x7e8b89e2, 0x8b84, 0x4cb3, { 0x86, 0x8f, 0x10, 0xb6, 0x78, 0x71, 0xa2, 0xc0 }}
// Typecast HOB pointer to EWL_PRIVATE_DATA.
// User with NDA clearance should refer to RC code for latest structure definition.
#define FSP_EWL_ID_HOB_GUID { 0xd8e05800, 0x5e, 0x4462, { 0xaa, 0x3d, 0x9c, 0x6b, 0x47, 0x4, 0x92, 0xb } };
//Typecast HOB pointer to RAS_ACPI_PARAM_HOB_DATA;
#define RAS_ACPI_PARAM_HOB_GUID {0x594dfe5c, 0x7a87, 0x49dc, { 0x8f, 0x33, 0xea, 0x83, 0x4d, 0x6f, 0x18, 0x90 } }
#endif //#ifndef _FSP_ACPI_HOBS_H_
#endif // __FSP_ACPI_HOBS__

17
src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspEas.h
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@ -1,17 +0,0 @@
/** @file
Intel FSP definition from Intel Firmware Support Package External
Architecture Specification v2.2.
@copyright
Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_EAS_H_
#define _FSP_EAS_H_
#include <Uefi.h>
#include <Guid/GuidHobFspEas.h>
#include <Guid/FspHeaderFile.h>
#include <FspEas/FspApi.h>
#endif // _FSP_EAS_H_

4
src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspEdpcParam.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -26,6 +26,8 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSP_EDPC_PARAM__

21
src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspErrorInfoHob.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -26,20 +26,23 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _FSP_ERROR_INFO_HOB_H_
#define _FSP_ERROR_INFO_HOB_H_
#include <Uefi/UefiMultiPhase.h>
#include <Pi/PiBootMode.h>
#include <Pi/PiHob.h>
#include <Pi/PiStatusCode.h>
#define FSP_ERROR_INFO_HOB_GUID { 0x611e6a88, 0xadb7, 0x4301, { 0x93, 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6 }}
///
/// GUID value indicating the FSP error information.
///
#define FSP_ERROR_INFO_HOB_GUID { 0x611e6a88, 0xadb7, 0x4301, { 0x93, 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6 } }
#define FSP_ERROR_INFO_STATUS_CODE_TYPE (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED)
///
/// FSP Error Information Block.
///
#pragma pack(1)
typedef struct {
///
/// GUID HOB header.
@ -81,4 +84,4 @@ typedef struct {
#pragma pack()
#endif //#ifndef _FSP_ERROR_INFO_HOB_H_
#endif //_FSP_ERROR_INFO_H_

70
src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspExtMemoryPprHob.h Normal file
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@ -0,0 +1,70 @@
/** @file
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _FSP_EXT_MEMORY_PPR_HOB_H_
#define _FSP_EXT_MEMORY_PPR_HOB_H_
#include "FspGlobals.h"
#define FSP_EXT_MEMORY_PPR_HOB_GUID { 0x3956C6DA, 0x35B6, 0x4036, { 0x93, 0xE4, 0xB1, 0x51, 0x38, 0x60, 0x21, 0x1E } }
#pragma pack(1)
typedef struct FspExtPprAddr {
UINT8 Status;
UINT8 ErrorType;
UINT8 Socket;
UINT8 MemoryController;
UINT8 Channel;
UINT8 Dimm;
UINT8 Bank;
UINT32 Row;
UINT8 Rank;
} FSP_EXT_PPR_ADDR;
typedef struct FspExtPprDdrInfo {
UINT8 Count;
FSP_EXT_PPR_ADDR PprAddresses[FSP_MAX_PPR_ADDR_ENTRIES_DDR];
} FSP_EXT_DDR_PPR_INFO;
typedef struct FspExtMemoryPprData {
FSP_EXT_DDR_PPR_INFO DdrPprInfo;
} FSP_EXT_MEMORY_PPR_DATA;
typedef struct FspExtMemoryPprHob {
FSP_EXT_HEADER Header;
FSP_EXT_MEMORY_PPR_DATA Data;
} FSP_EXT_MEMORY_PPR_HOB;
#pragma pack()
#endif // _FSP_EXT_MEMORY_PPR_HOB_H_

161
src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspExtSystemMemoryMapHob.h Normal file
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@ -0,0 +1,161 @@
/** @file
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _FSP_EXT_SYSTEM_MEMORY_MAP_HOB_H_
#define _FSP_EXT_SYSTEM_MEMORY_MAP_HOB_H_
#include "FspGlobals.h"
#define FSP_EXT_SYSTEM_MEMORY_MAP_HOB_GUID { 0xDF310DE8, 0x579F, 0x419C, { 0xB6, 0xAB, 0x4D, 0x4B, 0xE7, 0xCA, 0xB0, 0x83 } }
#pragma pack(1)
typedef struct FspDimmDevice {
UINT8 Present;
BOOLEAN Enabled;
UINT8 DramIoWidth; // Actual DRAM IO Width (4, 8, 16)
UINT8 NumRanks; // Number of ranks on dimm
UINT8 NumPackageRanks; // Number of Package ranks on dimm
// For DDR5 NumRanks and NumPackageRanks same
// For MCR NumRanks and NumPackageRanks may differ
UINT8 ActKeyByte2; // Actual module type reported by SPD
UINT16 DimmSize;
UINT16 VendorID;
UINT16 DeviceID;
UINT16 RevisionID;
UINT8 SerialNumber[FSP_DIMM_MAX_SERIALNUMBER_LEN]; // Serial Number
UINT8 PartNumber[FSP_DIMM_MAX_PARTNUMBER_LEN]; // Part Number
UINT16 SubsystemVendorID;
UINT16 SubsystemDeviceID;
UINT16 SubsystemRevisionID;
UINT16 FisVersion; // Firmware Interface Specification version
INT32 CommonTck;
UINT16 SpdRegVen; // Register Vendor ID in SPD
UINT8 DataWidth;
} FSP_EXT_DIMM_DEVICE;
typedef struct FspExtMemoryDimmDeviceInfo {
UINT8 Count;
FSP_EXT_DIMM_DEVICE Dimms[FSP_MAX_DIMM];
} FSP_EXT_DIMM_DEVICE_INFO;
typedef struct FspMemoryChannelDevice {
UINT8 Enabled; // 0 = channel disabled, 1 = channel enabled
UINT8 Features; // Bit mask of features to enable or disable
UINT8 MaxDimm; // Number of DIMM
UINT8 ChFailed;
UINT8 NgnChFailed;
UINT8 Is4BitEccDimmPresent; // 4-bit Ecc dimm present indicator
UINT8 DdrPopulationMap; // Bitmap to indicate location of DDR DIMMs within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
UINT8 PmemPopulationMap; // Bitmap to indicate location of PMem modules within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
FSP_EXT_DIMM_DEVICE_INFO DimmInfo;
} FSP_EXT_MEMORY_CHANNEL_DEVICE;
typedef struct FspMemoryController {
UINT8 ImcEnabled;
UINT32 MemSize;
} FSP_EXT_MEMORY_CONTROLLER;
typedef struct FspExtMemoryChannelDeviceInfo {
UINT8 Count;
FSP_EXT_MEMORY_CHANNEL_DEVICE Devices[FSP_MAX_CH];
} FSP_EXT_MEMORY_CHANNEL_DEVICE_INFO;
typedef struct FspExtMemoryControllerInfo {
UINT8 Count;
UINT8 NumChPerMC;
FSP_EXT_MEMORY_CONTROLLER MemControllers[FSP_MAX_IMC];
} FSP_EXT_MEMORY_CONTROLLER_INFO;
typedef struct FspMemoryMapSocket {
UINT8 SocketEnabled;
UINT32 IioStackBitmap;
UINT32 SktTotMemMapSPA; // Total memory mapped to SPA
FSP_EXT_MEMORY_CONTROLLER_INFO MemoryControllerInfo;
FSP_EXT_MEMORY_CHANNEL_DEVICE_INFO MemoryChannelDeviceInfo;
} FSP_EXT_MEMORY_MAP_SOCKET;
typedef struct FspExtMemMapSocketInfo {
UINT8 Count;
FSP_EXT_MEMORY_MAP_SOCKET Sockets[FSP_MAX_SOCKET];
} FSP_EXT_MEMORY_MAP_SOCKET_INFO;
typedef struct FspMemoryMapElement {
UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
UINT8 NodeId; // Node ID of the HA Owning the memory
UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA
UINT8 ClusterId; // Logical cluster Id of SNC cluster - only 0 in UMA clustering and all2all
UINT32 BaseAddress; // Base Address of the element in 64MB chunks
UINT32 ElementSize; // Size of this memory element in 64MB chunks
} FSP_EXT_MEMORY_MAP_ELEMENT;
typedef struct FspExtMemMapElementInfo {
UINT8 Count;
FSP_EXT_MEMORY_MAP_ELEMENT Elements[FSP_MAX_MEMORY_MAP_ELEMENTS];
} FSP_EXT_MEMORY_MAP_ELEMENT_INFO;
typedef struct FspExtRasInfo {
UINT8 SystemRasType;
UINT8 RasModesEnabled; // RAS modes that are enabled
UINT16 ExRasModesEnabled; // Extended RAS modes that are enabled
} FSP_EXT_RAS_INFO;
typedef struct FspExtMemoryConfigurationInfo {
UINT32 LowMemBase; // Mem base in 64MB units for below 4GB mem.
UINT32 LowMemSize; // Mem size in 64MB units for below 4GB mem.
UINT32 HighMemBase; // Mem base in 64MB units for above 4GB mem.
UINT32 HighMemSize; // Mem size in 64MB units for above 4GB mem.
UINT32 MmiohBase; // MMIOH base in 64MB granularity
UINT32 MemSize; // Total physical memory size
UINT16 MemFreq;
UINT8 MemMode; // 0 - Independent, 1 - Lockstep
UINT8 VolMemMode; // 0 - 1LM, 1 - 2LM
UINT16 DramType;
UINT8 DdrVoltage; // Mem Frequency
UINT8 ErrorCorrectionType;
} FSP_EXT_MEMORY_CONFIGURATION_INFO;
typedef struct FspExtSystemMemoryMapData {
FSP_EXT_MEMORY_CONFIGURATION_INFO MemoryConfigurationInfo;
FSP_EXT_RAS_INFO RasInfo;
FSP_EXT_MEMORY_MAP_ELEMENT_INFO MemoryMapElementInfo;
FSP_EXT_MEMORY_MAP_SOCKET_INFO MemoryMapSocketInfo;
} FSP_EXT_SYSTEM_MEMORY_MAP_DATA;
typedef struct FspExtSystemMemoryMapDataHob{
FSP_EXT_HEADER Header;
FSP_EXT_SYSTEM_MEMORY_MAP_DATA Data;
} FSP_EXT_SYSTEM_MEMORY_MAP_HOB;
#pragma pack()
#endif // _FSP_EXT_SYSTEM_MEMORY_MAP_HOB_H_

61
src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspGlobals.h Normal file
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@ -0,0 +1,61 @@
/** @file
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _FSP_EXT_GLOBALS_
#define _FSP_EXT_GLOBALS_
#define FSP_MAX_SOCKET MAX_SOCKET
#define FSP_MAX_IMC MAX_IMC
#define FSP_MAX_MC_CH MAX_MC_CH
#define FSP_MAX_DIMM MAX_DIMM
#define FSP_DIMM_MAX_SERIALNUMBER_LEN NGN_MAX_SERIALNUMBER_STRLEN
#define FSP_DIMM_MAX_PARTNUMBER_LEN NGN_MAX_PARTNUMBER_STRLEN
#define FSP_MAX_CH ((FSP_MAX_IMC)*(FSP_MAX_MC_CH))
#define FSP_MAX_MEMORY_MAP_ELEMENTS 150
#define MEM_64MB_TO_BYTES(Size64M) ((UINT64)(Size64M) << 26)
#define MEM_64MB_TO_KBYTES(Size64M) ((UINT64)(Size64M) << 16)
#define MEM_64MB_TO_MBYTES(Size64M) ((UINT64)(Size64M) << 6)
#define MEM_64MB_TO_GBYTES(Size64M) ((Size64M) >> 4)
#define MEM_BYTES_TO_64MB(SizeB) ((SizeB) >> 26)
#define MEM_KBYTES_TO_64MB(SizeKB) ((SizeKB) >> 16)
#define MEM_MBYTES_TO_64MB(SizeMB) ((SizeMB) >> 6)
#define FSP_MAX_PPR_ADDR_ENTRIES_DDR MAX_PPR_ADDR_ENTRIES_DDR
typedef struct FspExtHeader {
UINT64 Magic;
UINT32 DataLength;
UINT32 CheckSum;
} FSP_EXT_HEADER;
#endif // _FSP_EXT_GLOBALS_

8
src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspUpd.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -37,11 +37,11 @@ are permitted provided that the following conditions are met:
#pragma pack(1)
#define FSPT_UPD_SIGNATURE 0x545F445055525053 /* 'SPRUPD_T' */
#define FSPT_UPD_SIGNATURE 0x545F445055524E47 /* 'GNRUPD_T' */
#define FSPM_UPD_SIGNATURE 0x4D5F445055525053 /* 'SPRUPD_M' */
#define FSPM_UPD_SIGNATURE 0x4D5F445055524E47 /* 'GNRUPD_M' */
#define FSPS_UPD_SIGNATURE 0x535F445055525053 /* 'SPRUPD_S' */
#define FSPS_UPD_SIGNATURE 0x535F445055524E47 /* 'GNRUPD_S' */
#define FSPI_UPD_SIGNATURE 0x495F445055524E47 /* 'GNRUPD_I' */

233
src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspiUpd.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -35,13 +35,27 @@ are permitted provided that the following conditions are met:
#include <FspUpd.h>
#define FSP_RAS_ACPI_HOB_GUID { 0x826785ee, 0xa8e0, 0x4d8f, { 0x82, 0x6f, 0x54, 0x29, 0x2c, 0xe7, 0x6f, 0xe6 } };
#pragma pack(1)
typedef struct {
/** WHEA Support
/** RAS Log Level.
RAS Log setup options.
0:None, 1:MIN (BASIC_FLOW), 2:MID (BASIC_FLOW, FUNC_FLOW), 3:MAX (BASIC_FLOW, FUNC_FLOW, REG)
**/
UINT8 RasLogLevel;
/** WHEA FV Base Address
The physical memory-mapped base address of the WHEA (FV).
**/
UINT64 WheaFvBase;
/** WHEA FV Base Size
The size of the WHEA FV region in bytes
**/
UINT64 WheaFvBaseSize;
/** WHEA Support
Enable/Disable WHEA support.
0:Disable, 1:Enable
**/
@ -69,15 +83,216 @@ typedef struct {
**/
UINT8 PcieErrInjActionTable;
/** SGX Memory Error Injection Support
Enable/Disable Error Injection Support in SGX Memory.
0:6dB, 1:3.5dB
**/
UINT8 SgxErrorInjEn;
/** Os Native AER Support
Select FFM or OS native for AER error handling. If select OS native, BIOS also initialize
FFM first until handshake, which depends on OS capability in FSP.
0:Disable, 1:Enable
**/
UINT8 OsNativeAerSupport;
/** IIO MCA Support.
Enable/Disable IIO MCA Support.
0:Disable, 1:Enable
**/
UINT8 IoMcaEn;
/** System Errors
System Error Enable/Disable setup options.
0:Disabled, 1:Enabled
**/
UINT8 SystemErrorEn;
/** CPU CrashLog Feature
The feature helps collecting crash data from OOBMSM SSRAM
0:Disabled, 1:Enabled,2:Auto
**/
UINT8 CpuCrashLogFeature;
/** MCERR Trigger CrashLog Disable
The feature helps to disable MCERR to trigger crash log
0:No, 1:Yes
**/
UINT8 McerrTriggerDisable;
/** Smbus Error Recovery
Enable or Disable(Default) Smbus Error Recovery
0:Disabled, 1:SMI, 2:Error Pin
**/
UINT8 SmbusErrorRecovery;
/** EMCA Error Support
Enable/Disable EMCA Error support
0:Disable, 1:Enable
**/
UINT8 EmcaEn;
/** EMCA Logging Support
Enable/Disable EMCA Logging
0:Disable, 1:Enable
**/
UINT8 ElogEn;
/** LMCE Support
Enable/Disable Local MCE firmware support
0:Disable, 1:Enable
**/
UINT8 LmceEn;
/** EMCA MCE-SMI Enable
Enable/Disable EMCA Uncorrected SMI for gen2
0:Disable, 2:EMCA gen2 MSMI
**/
UINT8 EmcaMsmiEn;
/** EMCA CMCI-SMI Morphing
Enable/Disable EMCA CSMI
0:Disable, 2:EMCA gen2 CSMI
**/
UINT8 EmcaCsmiEn;
/** EMCA CMCI-SMI Threshold
Set the threshold of CSMI
**/
UINT16 EmcaCsmiThreshold;
/** CSMI Dynamic Disable
Enable/Disable CSMI when error threshold reached
0:Disable, 1:Enable
**/
UINT8 CsmiDynamicDisable;
/** Ignore OS ELOG Opt-in
Enable/Disable Ignore OS ELOG Opt-in and log
0:Disable, 1:Enable
**/
UINT8 ElogIgnOptin;
/** Corrected Error eLog
Enable/Disable Corrected Error eLog
0:Disable, 1:Enable
**/
UINT8 ElogCorrErrEn;
/** Memory Error eLog
Enable/Disable Memory Error eLog
0:Disable, 1:Enable
**/
UINT8 ElogMemErrEn;
/** Processor Error eLog
Enable/Disable Processor Error eLog
0:Disable, 1:Enable
**/
UINT8 ElogProcErrEn;
/** Ubox Error Mask
Mask SMI generation for Ubox Error
0:Disable, 1:Enable
**/
UINT8 UboxErrorMask;
/** Corrected Error Cloaking
Mask Corrected errors from OS/SW visibility only when EMCA is enabled
0:Disable, 1:Enable
**/
UINT8 CeCloakingEn;
/** Memory Corrected Error
Enable/Disable Memory Corrected Error
0:Disable, 1:Enable, 2:Auto
**/
UINT8 CorrMemErrEn;
/** Mca Bank Error Injection Support
Enable/Disable Mca Bank Error Injection Support.
$EN_DIS
**/
UINT8 McaBankErrInjEn;
/** Whea Log Memory Error
Enable/Disable Whea Log Memory Error
0:Disabled, 1:Enabled
**/
UINT8 WheaLogMemoryEn;
/** Whea Log Processor Error
Enable/Disable Whea Log Processor Error
0:Disabled, 1:Enabled
**/
UINT8 WheaLogProcEn;
/** Whea Log PCI Error
Enable/Disable Whea Log PCI Error
0:Disabled, 1:Enabled
**/
UINT8 WheaLogPciEn;
/** Viral Status
Enable/Disable Viral
$EN_DIS
**/
UINT8 ViralEn;
/** System Memory Poison
Enable/Disable System Memory Poison.
$EN_DIS
**/
UINT8 DfxPoisonEn;
/** Clear Shadow Registers
Enable/Disable clearing shadow registers.
$EN_DIS
**/
UINT8 ClearShadowRegisters;
/** PCIE Corrected Error Threshold Counter
Enable/Disable PCIE Corrected Error Counter.
$EN_DIS
**/
UINT8 PcieCorErrCntr;
/** PCIE Corrected Error Threshold Counter
0x00000001 - 0x0000ffff.
**/
UINT32 PcieCorErrThres;
/** IIO eDPC Support
Enable/Disable IIO eDPC Support.
0:Disabled, 1:On Fatal Error, 2:On Fatal and Non-Fatal Errors
**/
UINT8 EdpcEn;
/** IIO eDPC Interrupt
Enable/Disable IIO eDPC Interrupt.
0:Disabled, 1:Enabled
**/
UINT8 EdpcInterrupt;
/** IpmiIoBase
Address of IpmiIoBase
**/
UINT16 IpmiIoBase;
/** Trigger SW Error Threshold
Enable or Disable Sparing trigger SW Error Match Threshold.
0:Disable, 1:Enable
**/
UINT8 TriggerSWErrThEn;
/** SW Per Row Threshold
SW Per Row Correctable Error Threshold (1 - 0x7FFF) used for row level error.
**/
UINT16 SparePerRowTh;
/** N/A
**/
UINT8 ReservedSiliconInitUpd[16];
UINT8 ReservedSmmInitUpd[16];
} FSPI_CONFIG;
@ -87,11 +302,15 @@ typedef struct {
/** N/A
**/
FSP_UPD_HEADER FspUpdHeader;
/** N/A
**/
FSPI_ARCH_UPD FspiArchUpd;
/** N/A
**/
FSPI_CONFIG FspiConfig;
/** N/A
**/
UINT16 UpdTerminator;

2571
src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspmUpd.h
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File diff suppressed because it is too large Load diff

333
src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FspsUpd.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -30,261 +30,224 @@ are permitted provided that the following conditions are met:
**/
#ifndef __FSPSUPD_H__
#define __FSPSUPD_H__
#ifndef __FSPS_UPD_H__
#define __FSPS_UPD_H__
#include <FspUpd.h>
#pragma pack(1)
/** FSP-S Configuration
**/
typedef struct {
/** Offset 0x0020 - Processor VmxEnable Function
Processor VmxEnable Function - <b>1: Enable(Default)</b>, 0: Disable Processor VmxEnable Function.
0: Disable, 1: Enable
/** PCIe Controller 0
Enable / Disable PCI Express controller 0
$EN_DIS
**/
UINT8 VmxEnable;
UINT8 EnablePcie0;
/** Offset 0x0021 - Processor TurboMode Function
Processor TurboMode Function - <b>1: Enable(Default)</b>, 0: Disable Processor TurboMode Function.
0: Disable, 1: Enable
/** PCIe Controller 1
Enable / Disable PCI Express controller 1
$EN_DIS
**/
UINT8 TurboMode;
UINT8 EnablePcie1;
/** Offset 0x0022 - Processor Safer Mode Extensions Function
Processor Safer Mode Extensions Function - <b>0: Disable(Default)</b>, 1: Enable
Processor Safer Mode Extensions Function.
0: Disable, 1: Enable
/** Embedded Multi-Media Controller (eMMC)
Enable / Disable Embedded Multi-Media controller
$EN_DIS
**/
UINT8 ProcessorSmxEnable;
UINT8 EnableEmmc;
/** Offset 0x0023 - SstCp
SstCp - 1: Enable, <b>0: Disable SstCp(Default)</b>.
0: Disable, 1: Enable
/** LAN Controllers
Enable / Disable LAN controllers, refer to FSP Integration Guide for details.
0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only
**/
UINT8 SstCpSetting;
UINT8 EnableGbE;
/** Offset 0x0024 - SstCp Capable Status
SST-CP Capable Status in system - <b>0: Disable(Default)</b>, 1: Enable.
0: Disable, 1: Enable
/** PCIe Root Port 0 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 SstCpCapableSystem;
UINT8 PcieRootPort0DeEmphasis;
/** Offset 0x0025
/** PCIe Root Port 1 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 UnusedUpdSpace0[1];
UINT8 PcieRootPort1DeEmphasis;
/** Offset 0x0026 - PCH Protect Range Limit
/** PCIe Root Port 2 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 PcieRootPort2DeEmphasis;
/** PCIe Root Port 3 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 PcieRootPort3DeEmphasis;
/** PCIe Root Port 4 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 PcieRootPort4DeEmphasis;
/** PCIe Root Port 5 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 PcieRootPort5DeEmphasis;
/** PCIe Root Port 6 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 PcieRootPort6DeEmphasis;
/** PCIe Root Port 7 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 PcieRootPort7DeEmphasis;
/** eMMC DLL Configuration Data
Pointer to eMMC DLL Configuration Data
**/
UINT32 EMMCDLLConfigPtr;
/** PCH Protect Range Limit
Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
limit comparison.
**/
UINT16 PchProtectedRangeLimit[5];
/** Offset 0x0030 - PCH Protect Range Base
/** PCH Protect Range Base
Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
**/
UINT16 PchProtectedRangeBase[5];
/** Offset 0x003A - PchAdrEn
PchAdr - <b>0: PLATFORM POR(Default)</b>, 1: FORCE ENABLE, 2:FORCE DISABLE.
0: PLATFORM POR, 1: FORCE ENABLE, 2: FORCE DISABLE
/** PchAdrEn
PchAdr 0:PLATFORM POR, <b>1:FORCE ENABLE(Default)</b>, 2:FORCE DISABLE
0:PLATFORM POR, 1:FORCE ENABLE, 2:FORCE DISABLE
**/
UINT8 PchAdrEn;
/** Enable Timed GPIO0
Enable/Disable Timed GPIO0. When disabled, it disables cross time stamp time-synchronization
as extension of Hammock Harbor time synchronization
$EN_DIS
**/
UINT8 EnableTimedGpio0;
/** Enable Timed GPIO1
Enable/Disable Timed GPIO0. When disabled, it disables cross time stamp time-synchronization
as extension of Hammock Harbor time synchronization
$EN_DIS
**/
UINT8 EnableTimedGpio1;
/** FSP smm init enable
Enable / Disable FSP smm init
$EN_DIS
**/
UINT8 FspSmmInitEn;
/** Offset 0x003B - EnableTme
EnableTme - <b>0: Disabled(Default)</b>, 1: Enabled, 2:Software Controlled.
0: Disabled, 1: Enabled, 2:Software Controlled
/** C2C3TT
Default = 0, means [AUTO]. C2 to C3 Transition Timer, PPDN_INIT = C2C3TT CSR Bit[11:0]
0: Default, Bit[11:0] : C2 to C3 Transition Timer
**/
UINT8 EnableTme;
UINT8 CpuPmC2c3tt;
/** Offset 0x003C - EnableTmeBypass
EnableTmeBypass - <b>0: Disabled(Default)</b>, 1: Enabled.
0: Disabled, 1: Enabled
**/
UINT8 EnableTmeBypass;
/** Offset 0x003D - SgxFactoryReset
SgxFactoryReset - <b>0: Disabled(Default)</b>, 1: Enabled.
0: Disabled, 1: Enabled
**/
UINT8 SgxFactoryReset;
/** Offset 0x003E - EnableSgx
EnableSgx - <b>0: Disabled(Default)</b>, 1: Enabled.
0: Disabled, 1: Enabled
**/
UINT8 EnableSgx;
/** Offset 0x003F - SgxPackageInfoInBandAccess
SgxPackageInfoInBandAccess - <b>0: Disabled(Default)</b>, 1: Enabled.
0: Disabled, 1: Enabled
**/
UINT8 SgxPackageInfoInBandAccess;
/** Offset 0x0040 - SgxQoS
SgxQoS - 0: Disabled, <b>1: Enabled(Default)</b>.
0: Disabled, 1: Enabled
**/
UINT8 SgxQoS;
/** Offset 0x0041 - EpochUpdate
EpochUpdate - 1: Change to New Random Owner EPOCHs, <b>2: Manual User Defined Owner
EPOCHs(Default)</b>.
1: Change to New Random Owner EPOCHs, 2: Manual User Defined Owner EPOCHs
**/
UINT8 EpochUpdate;
/** Offset 0x0042 - SgxLeWr
SgxLeWr - <b>0: Disabled(Default)</b>, 1: Enabled.
0: Disabled, 1: Enabled
**/
UINT8 SgxLeWr;
/** Offset 0x0043 - SgxDebugMode
SgxDebugMode - <b>0: Disabled(Default)</b>, 1: Enabled.
0: Disabled, 1: Enabled
**/
UINT8 SgxDebugMode;
/** Offset 0x0044 - SgxAutoRegistrationAgent
SgxAutoRegistrationAgent - <b>0: Disabled(Default)</b>, 1: Enabled.
0: Disabled, 1: Enabled
**/
UINT8 SgxAutoRegistrationAgent;
/** Offset 0x0045 - DfxSgxRegistrationServerSelect
DfxSgxRegistrationServerSelect - <b>0: SBX(Default)</b>, 1: PRX, 2:AUTO, 3:LIV,
4:SW Defined Server.
0: SBX, 1: PRX, 2:AUTO, 3:LIV, 4:SW Defined Server
**/
UINT8 DfxSgxRegistrationServerSelect;
/** Offset 0x0046 - Processor Enable Monitor MWAIT
Processor Enable Monitor MWAIT - <b>1: Enable(Default)</b>, 0: Disable Processor
Monitor MWAIT.
0: Disabled, 1: Enabled
/** Processor Enable Monitor MWAIT
Enable(Default) or Disable Processor Monitor MWAIT
$EN_DIS
**/
UINT8 CpuPmMonitorMWait;
/** Offset 0x0047 - Processor C6
Processor C6 - <b>1: Enable(Default)</b>, 0: Disable Processor C6 (ACPI C3) report to OS.
0: Disabled, 1: Enabled
/** Processor TurboMode Function
Enable(Default) or Disable Processor TurboMode Function
$EN_DIS
**/
UINT8 CpuPmC6Enable;
UINT8 CpuPmTurboMode;
/** Offset 0x0048 - Hardware P-States
Hardware P-States - 0: Disable: Hardware chooses a P-state based on OS Request
(Legacy P-States), <b>1:Native Mode:Hardware chooses a P-state based on OS guidance(Default)</b>,
2:Out of Band Mode:Hardware autonomously chooses a P-state (no OS guidance), 3:Native
Mode with No Legacy Support.
0: Disable, 1: Native Mode, 2: Out of Band Mode, 3: Native Mode with No Legacy Support
/** Hardware P-States
Disable: Hardware chooses a P-state based on OS Request (Legacy P-States)\n
Native Mode:Hardware chooses a P-state based on OS guidance\n
Out of Band Mode:Hardware autonomously chooses a P-state (no OS guidance)
0:Disable, 1:Native Mode (Default), 2:Out of Band Mode, 3:Native Mode with No Legacy Support
**/
UINT8 CpuPmProcessorHWPMEnable;
/** Offset 0x0049 - Power Performance Tuning
Power Performance Tuning - <b>0: OS Controls EPB (Default)</b>, 1: BIOS Controls
EPB, 2: PECI Controls EPB.
/** HardwarePM Interrupt
Enable or Disable (Default) Hardware PM Interrupt
$EN_DIS
**/
UINT8 CpuPmProcessorHWPMInterrupt;
/** EPP Profile
Choose an HWPM Profile, 0: Performance, 128: Balanced Performance, 192: Balanced
Power, 255: Power
0: Performance, 128: Balanced Performance, 192: Balanced Power, 255: Power
**/
UINT8 CpuPmProcessorEPPProfile;
/** Boot Performance Mode
Select the performance state that the BIOS will set before OS hand off, 0: Max Performance,
1: Max Efficiency
0: Max Performance (Default), 1: Max Efficiency
**/
UINT8 CpuPmBootPstate;
/** Power Performance Tuning
Power Performance Tuning <b>0: OS Controls EPB (Default)</b>, 1: BIOS Controls EPB,
2: PECI Controls EPB
0: OS Controls EPB, 1: BIOS Controls EPB, 2: PECI Controls EPB
**/
UINT8 CpuPmPwrPerfTuning;
/** Offset 0x004A - Configure SST-BF
Allow (Default)/Disallow BIOS to configure SST-BF High Priority Cores so that SW
does not have to configure - 0:Disable, <b>1:Enable(Default)</b>.
0:Disable, 1:Enable
/** Enable or Disable Thermal Monitor
Enable or Disable Thermal Monitor, 0: Disable, 1: Enable
$EN_DIS
**/
UINT8 CpuPmProcessorConfigurePbf;
UINT8 ThermalMonitor;
/** Offset 0x004B - CF9 Global Reset Promotion
CF9 Global Reset Promotion - 1: Enable promoting CF9 reset to global, <b>0: Disable
promoting CF9 reset to global(Default)</b>.
0: Disabled, 1: Enabled
/** FSPS Upd settings support
: FSPS Upd settings support
$EN_DIS
**/
UINT8 MeGrPromotionEnabled;
UINT8 FspsUpdSupport;
/** Offset 0x004C - Global Reset Lock
Global Reset Lock - <b>1: Enable locking the joint ME and host reset capability(Default)</b>,
0: Disable locking the joint ME and host reset capability.
0: Disabled, 1: Enabled
/** N/A
Pointer to node list which is used to initizalize security variables - CCT_VS_METADATA_NODE
**/
UINT8 MeGrLockEnabled;
EFI_PHYSICAL_ADDRESS SecurityCctVarStorageMetadataNodePtr;
/** Offset 0x004D - Delayed Authentication Mode
Enable or disable Delayed Authentication Mode - <b>0: Disable(Default)</b>, 1: Enable.
0:Disable, 1:Enable
**/
UINT8 DelayedAuthenticationMode;
/** Offset 0x004E - Delayed Authentication Mode Override
Enable or disable Delayed Authentication Mode Override - <b>0: Disable(Default)</b>,
1: Enable.
0:Disable, 1:Enable
**/
UINT8 DelayedAuthenticationModeOverride;
/** Offset 0x004F - Core Bios Done Message
Enable or disable Core Bios Done message sent to ME - 0: Disable, <b>1: Enable(Default)</b>.
0:Disable, 1:Enable
**/
UINT8 CoreBiosDoneEnabled;
/** Offset 0x0050 - End Of Post Message
Enable or disable sending END_OF_POST message to ME - 0: Disable, 1: Send in PEI,
<b>2: Send in DXE(Default)</b>.
0:Disable, 1:Send in PEI, 2:Send in DXE
**/
UINT8 EndOfPostMessage;
/** Offset 0x0051 - HMRFPO_LOCK Message
Enable or disable sending HMRFPO_LOCK message to ME - 0: Disable, <b>1: Enable(Default)</b>.
0:Disable, 1:Enable
**/
UINT8 MeHmrfpoLockEnabled;
/** Offset 0x0052 - HMRFPO_ENABLE Message
Enable or disable sending HMRFPO_ENABLE message to ME - <b>0: Disable(Default)</b>,
1: Enable.
0:Disable, 1:Enable
**/
UINT8 MeHmrfpoEnableEnabled;
/** Offset 0x0053
**/
UINT8 UnusedUpdSpace1[1];
/** Offset 0x0054
/** N/A
**/
UINT8 ReservedSiliconInitUpd[16];
} FSPS_CONFIG;
/** Fsp S UPD Configuration
**/
typedef struct {
/** Offset 0x0000
/** N/A
**/
FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0020
/** N/A
**/
FSPS_ARCH2_UPD FspsArchUpd;
/** N/A
**/
FSPS_CONFIG FspsConfig;
/** Offset 0x0064
**/
UINT8 UnusedUpdSpace2[2];
/** Offset 0x0066
/** N/A
**/
UINT16 UpdTerminator;
} FSPS_UPD;
#pragma pack()

26
src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/FsptUpd.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -38,19 +38,19 @@ are permitted provided that the following conditions are met:
#pragma pack(1)
typedef struct {
/** N/A
**/
UINT64 MicrocodeRegionBase;
/** N/A
**/
UINT64 MicrocodeRegionLength;
/** N/A
**/
UINT64 CodeRegionBase;
/** N/A
**/
UINT64 CodeRegionLength;
@ -60,13 +60,11 @@ typedef struct {
typedef struct {
/** Offset 0x0040 - Disable Port80 output in FSP-T
Select Port80 Control in FSP-T - 0:VPD-Style, <b>1:Enable Port80 Output (Default)</b>,
2:Disable Port80 Output, refer to FSP Integration Guide for details.
/** Disable Port80 output in FSP-T
0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output
**/
UINT8 FsptPort80RouteDisable;
/** N/A
**/
UINT8 ReservedTempRamInitUpd[31];
@ -75,23 +73,23 @@ typedef struct {
typedef struct {
/** N/A
**/
FSP_UPD_HEADER FspUpdHeader;
/** N/A
**/
FSPT_ARCH2_UPD FsptArchUpd;
/** N/A
**/
FSPT_CORE_UPD FsptCoreUpd;
/** N/A
**/
FSPT_CONFIG FsptConfig;
/** N/A
**/
UINT16 UpdTerminator;

340
src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioPcieConfigUpd.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -26,190 +26,45 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _IIO_PCIE_CONFIG_UPD_H_
#define _IIO_PCIE_CONFIG_UPD_H_
#ifndef MAX_SOCKET
#define MAX_SOCKET 4
#define MAX_SOCKET 2
#endif
#ifndef MAX_LOGIC_IIO_STACK
#define MAX_LOGIC_IIO_STACK 14
#endif
#ifndef MAX_IIO_PORTS_PER_SOCKET
#define MAX_IIO_PORTS_PER_SOCKET 57
#endif
#ifndef MAX_IOU_PER_SOCKET
#define MAX_IOU_PER_SOCKET 7
#define MAX_LOGIC_IIO_STACK 18
#endif
/**
* Maximum number of IIO ports per IIO stack.
*/
#ifndef MAX_IIO_PORTS_PER_STACK
#define MAX_IIO_PORTS_PER_STACK 1
#define MAX_IIO_PORTS_PER_STACK 8
#endif
#define MAX_IIO_STACK 16
#define MAX_IIO_STACKS_PER_SOCKET MAX_IIO_STACK
#define MAX_IIO_PORTS_PER_SOCKET (MAX_IIO_STACKS_PER_SOCKET * MAX_IIO_PORTS_PER_STACK)
#define MAX_IIO_PCIE_PER_SOCKET 1
#if MAX_SOCKET <= 4
#define MAX_VMD_STACKS_PER_SOCKET 8 // Max number of stacks per socket supported by VMD
//
// 10 PCIe stacks (PE) and 3 IO accelerator (IOAT) possible in Rich 1 Socket.
// However, we share R1S image with 4 socket SP image, no separate build for R1S.
// So use R1S definitions for 4 socket SP and 4 PE, 1 IOAT entry are just not used, never present.
//
#define MAX_IIO_PCIE_PER_SOCKET 10
#else
#define MAX_IIO_PCIE_PER_SOCKET 6
#endif
#pragma pack(1)
typedef enum {
PE0 = 0,
PE1,
PE2,
PE3,
PE4,
PE5,
PEa,
PEb,
PEc,
PEd,
PE_MAX,
PE_ = 0xFF // temporary unknown value
} IIO_PACKAGE_PE;
typedef struct {
UINT8 SLOTEIP[MAX_IIO_PORTS_PER_SOCKET]; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
UINT8 SLOTHPCAP[MAX_IIO_PORTS_PER_SOCKET]; // Slot Hot Plug capable - Slot Capabilities (D0-10 / F0 / R0xA4 / B6)
UINT8 SLOTHPSUP[MAX_IIO_PORTS_PER_SOCKET]; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
UINT8 SLOTPIP[MAX_IIO_PORTS_PER_SOCKET]; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
UINT8 SLOTAIP[MAX_IIO_PORTS_PER_SOCKET]; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
UINT8 SLOTMRLSP[MAX_IIO_PORTS_PER_SOCKET]; // MRL Sensor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B2)
UINT8 SLOTPCP[MAX_IIO_PORTS_PER_SOCKET]; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 /B1)
UINT8 SLOTABP[MAX_IIO_PORTS_PER_SOCKET]; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
UINT8 SLOTIMP[MAX_IIO_PORTS_PER_SOCKET];
UINT8 SLOTSPLS[MAX_IIO_PORTS_PER_SOCKET];
UINT8 SLOTSPLV[MAX_IIO_PORTS_PER_SOCKET];
UINT16 SLOTPSP[MAX_IIO_PORTS_PER_SOCKET];
BOOLEAN VppEnabled[MAX_IIO_PORTS_PER_SOCKET]; // 00 -- Disable, 01 -- Enable //no setup option defined- aj
UINT8 VppPort[MAX_IIO_PORTS_PER_SOCKET]; // 00 -- Port 0, 01 -- Port 1 //no setup option defined- aj
UINT8 VppAddress[MAX_IIO_PORTS_PER_SOCKET]; // 01-07 for SMBUS address of Vpp //no setup option defined- aj
UINT8 MuxAddress[MAX_IIO_PORTS_PER_SOCKET]; // SMBUS address of MUX //no setup option defined
UINT8 ChannelID[MAX_IIO_PORTS_PER_SOCKET]; // 00 -- channel 0, 01 -- channel 1 //no setup option defined
UINT8 PciePortEnable[MAX_IIO_PORTS_PER_SOCKET];
UINT8 PEXPHIDE[MAX_IIO_PORTS_PER_SOCKET]; // Hide any of the DMI or PCIE devices - SKT 0,1,2,3; Device 0-10 PRD
UINT8 HidePEXPMenu[MAX_IIO_PORTS_PER_SOCKET]; // to suppress /display the PCIe port menu
UINT8 PciePortOwnership[MAX_IIO_PORTS_PER_SOCKET];
UINT8 RetimerConnectCount[MAX_IIO_PORTS_PER_SOCKET];
UINT8 ConfigIOU[MAX_IOU_PER_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P1p2p3p4)
UINT8 PcieHotPlugOnPort[MAX_IIO_PORTS_PER_SOCKET]; // Manual override of hotplug for port
UINT8 VMDEnabled[MAX_VMD_STACKS_PER_SOCKET];
UINT8 VMDPortEnable[MAX_IIO_PORTS_PER_SOCKET];
UINT8 VMDHotPlugEnable[MAX_VMD_STACKS_PER_SOCKET];
UINT8 PcieMaxPayload[MAX_IIO_PORTS_PER_SOCKET];
UINT8 PciePortLinkSpeed[MAX_IIO_PORTS_PER_SOCKET]; // auto - 0(default); gen1 -1; gen2 -2; ... gen5 -5.
UINT8 DfxDnTxPresetGen3[MAX_IIO_PORTS_PER_SOCKET]; //auto - 0xFF(default); p0 - 0; p1 -1; ... p9 - 9.
UINT8 PcieGlobalAspm;
UINT8 PcieMaxReadRequestSize;
} UPD_IIO_PCIE_PORT_CONFIG;
typedef struct {
UINT8 Address;
UINT8 Port;
UINT8 MuxAddress;
UINT8 MuxChannel;
} IIO_VPP_CFG;
typedef struct {
UINT8 Eip : 1; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
UINT8 HotPlugSurprise : 1; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
UINT8 PowerInd : 1; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
UINT8 AttentionInd : 1; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
UINT8 PowerCtrl : 1; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B1)
UINT8 AttentionBtn : 1; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
UINT8 Reserved : 2;
} IIO_SLOT_CFG;
typedef struct {
UINT8 Address; // SMBUS address of IO expander which provides NPEM
UINT8 Bank; // Port or bank on IoExpander which provides NPEM
UINT8 MuxAddress; // SMBUS address of MUX used to access NPEM
UINT8 MuxChannel; // Channel of the MUX used to access NPEM
} IIO_NPEM_CFG;
typedef struct {
IIO_VPP_CFG Vpp;
IIO_NPEM_CFG Npem;
IIO_SLOT_CFG Slot;
UINT8 VppEnabled :1;
UINT8 VppExpType :1;
UINT8 NpemSupported :1;
UINT8 SlotImplemented :1;
UINT8 Retimer1Present :1;
UINT8 Retimer2Present :1;
UINT8 CommonClock :1;
UINT8 SRIS :1;
UINT16 HotPlug : 1; // If hotplug is supported on slot connected to this port
UINT16 MrlSensorPresent : 1; // If MRL is present on slot connected to this port
UINT16 SlotPowerLimitScale : 2; // Slot Power Scale for slot connected to this port
UINT16 SlotPowerLimitValue : 12; // Slot Power Value for slot connected to this port
UINT16 PhysicalSlotNumber; // Slot number for slot connected to this port
} IIO_BOARD_SETTINGS_PER_PORT;
typedef struct {
struct {
UINT8 Segment; ///< Remember segment, if it changes reset everything
UINT8 StackPciBusPoolSize[MAX_LOGIC_IIO_STACK]; ///< Number of bus numbers needed for IIO stack
} Socket[MAX_SOCKET];
} SYSTEM_PCI_BUS_CONFIGURATION;
typedef struct {
UINT64 Base; ///< Base (starting) address of a range (I/O, 32 and 64-bit mmio regions)
UINT64 Limit; ///< Limit (last valid) address of a range
} PCIE_BASE_LIMIT;
typedef struct {
UINT32 MmioLSize;
UINT64 MmioHSize;
} CXL11_LIMITS;
typedef struct {
PCIE_BASE_LIMIT Io; ///< Base and limit of I/O range assigned to entity
PCIE_BASE_LIMIT LowMmio; ///< Base and limit of low MMIO region for entity
PCIE_BASE_LIMIT HighMmio; ///< Base and limit of high (64-bit) MMIO region for entity
} PCI_BASE_LIMITS;
typedef struct {
PCI_BASE_LIMITS SocketLimits; ///< Base and Limit of all PCIe resources for the socket
PCI_BASE_LIMITS StackLimits[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of all PCIe resources for each stack of the socket
CXL11_LIMITS CxlStackReq[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of CXL11 resources for each stack of the socket
} SOCKET_PCI_BASE_LIMITS;
typedef struct {
//
// Save basic system configuration parameters along with the resource map to detect a change.
// Remember low and high I/O memory range when saving recource configuration. It is used to verify
// whether system memory map changed. Remember also stacks configured when creating the map.
// If anything changed reset the system PCI resource configuration.
//
UINT64 MmioHBase;
UINT64 MmioHGranularity;
UINT32 MmioLBase;
UINT32 MmioLLimit;
UINT32 MmioLGranularity;
UINT16 IoBase;
UINT16 IoLimit;
UINT16 IoGranularity;
UINT32 StackPresentBitmap[MAX_SOCKET];
//
// Used by the PciHostBridge DXE driver, these variables don't need to be exposed through setup options
// The variables are used as a communication vehicle from the PciHostBridge DXE driver to an OEM hook
// which updates the KTI resource map.
//
SOCKET_PCI_BASE_LIMITS Socket[MAX_SOCKET]; ///< Base and limit of all PCIe resources for each socket
} SYSTEM_PCI_BASE_LIMITS;
#define MAX_IOU_PER_SOCKET MAX_IIO_PCIE_PER_SOCKET
#define IIO_BIFURCATE_xxxxxxxx 0xFE
#define IIO_BIFURCATE_x4x4x4x4 0x0
@ -238,11 +93,150 @@ typedef struct {
#define IIO_BIFURCATE_x2x2x4x2x2x2x2 0x17
#define IIO_BIFURCATE_x4x2x2x2x2x2x2 0x18
#define IIO_BIFURCATE_x2x2x2x2x2x2x2x2 0x19
#define IIO_BIFURCATE_xxxxxxx4 0x40
#define IIO_BIFURCATE_xxx2xxx2 0x41
#define IIO_BIFURCATE_x1x1xxx2 0x42
#define IIO_BIFURCATE_xxx2x1x1 0x43
#define IIO_BIFURCATE_x1x1x1x1 0x44
#define IIO_BIFURCATE_AUTO 0xFF
#define C1_UID 2
#define C2_UID 3
/**
* VTBAR - Virtualization Technology BAR region size and alignment.
*/
#define IIO_VTBAR_LSB 16 // 64 kB
#define IIO_VTBAR_SIZE (1 << IIO_VTBAR_LSB)
#pragma pack(1)
typedef enum {
PE0 = 0,
PE1,
PE2,
PE3,
PE4,
PE5,
PEa,
PEb,
PEc,
PEd,
PE_MAX,
PE_ = 0xFF // temporary unknown value
} IIO_PACKAGE_PE;
typedef struct {
struct {
UINT8 Segment; ///< Remember segment, if it changes reset everything
UINT8 StackPciBusPoolSize[MAX_LOGIC_IIO_STACK]; ///< Number of bus numbers needed for IIO stack
} Socket[MAX_SOCKET];
} SYSTEM_PCI_BUS_CONFIGURATION;
typedef struct {
UINT64 Base; ///< Base (starting) address of a range (I/O, 32 and 64-bit mmio regions)
UINT64 Limit; ///< Limit (last valid) address of a range
} PCIE_BASE_LIMIT;
typedef struct {
UINT32 MmioLSize;
UINT64 MmioHSize;
} CXL11_LIMITS;
typedef struct {
PCIE_BASE_LIMIT Io; ///< Base and limit of I/O range assigned to entity
PCIE_BASE_LIMIT LowMmio; ///< Base and limit of low MMIO region for entity
PCIE_BASE_LIMIT HighMmio; ///< Base and limit of high (64-bit) MMIO region for entity
} PCI_BASE_LIMITS;
typedef struct {
PCI_BASE_LIMITS StackLimits[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of all PCIe resources for each stack of the socket
CXL11_LIMITS CxlStackReq[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of CXL11 resources for each stack of the socket
} SOCKET_PCI_BASE_LIMITS;
typedef struct {
//
// Save basic system configuration parameters along with the resource map to detect a change.
// Remember low and high I/O memory range when saving recource configuration. It is used to verify
// whether system memory map changed. Remember also stacks configured when creating the map.
// If anything changed reset the system PCI resource configuration.
//
UINT64 MmioHBase;
UINT64 MmioHGranularity;
UINT32 MmioLBase;
UINT32 MmioLLimit;
UINT32 MmioLGranularity;
UINT16 IoBase;
UINT16 IoLimit;
UINT16 IoGranularity;
UINT32 StackPresentBitmap[MAX_SOCKET];
//
// Used by the PciHostBridge DXE driver, these variables don't need to be exposed through setup options
// The variables are used as a communication vehicle from the PciHostBridge DXE driver to an OEM hook
// which updates the KTI resource map.
//
SOCKET_PCI_BASE_LIMITS Socket[MAX_SOCKET]; ///< Base and limit of all PCIe resources for each socket
} SYSTEM_PCI_BASE_LIMITS;
typedef struct {
UINT8 Address; // SMBUS address of IO expander which provides VPP register
UINT8 Port; // Port or bank on IoExpander which provides VPP register
UINT8 MuxAddress; // SMBUS address of MUX used to access VPP
UINT8 MuxChannel; // Channel of the MUX used to access VPP
} IIO_VPP_CFG;
typedef struct {
UINT8 Address; // SMBUS address of IO expander which provides NPEM
UINT8 Bank; // Port or bank on IoExpander which provides NPEM
UINT8 MuxAddress; // SMBUS address of MUX used to access NPEM
UINT8 MuxChannel; // Channel of the MUX used to access NPEM
} IIO_NPEM_CFG;
typedef struct {
UINT8 Eip : 1; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
UINT8 HotPlugSurprise : 1; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
UINT8 PowerInd : 1; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
UINT8 AttentionInd : 1; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
UINT8 PowerCtrl : 1; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B1)
UINT8 AttentionBtn : 1; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
UINT8 Reserved : 2;
} IIO_SLOT_CFG;
typedef struct {
//
// Below is an excerpt from structure PCIE_PORT_ENTERPRISE_CONFIG
//
IIO_VPP_CFG Vpp;
IIO_NPEM_CFG Npem;
IIO_SLOT_CFG Slot;
UINT8 VppEnabled :1; // If VPP is supported on given port
UINT8 VppExpType :1; // IO Expander type used for VPP (see IIO_VPP_EXPANDER_TYPE for values definitions)
UINT8 NpemSupported :1; // If NPEM is supported on given port
//
// Below is an excerpt IIO_PCIE_PORT_CONFIG
//
UINT8 SlotImplemented :1;
UINT8 Retimer1Present :1;
UINT8 Retimer2Present :1;
UINT8 CommonClock :1;
UINT8 SRIS :1;
//
// Below is an excerpt from structure PCIE_PORT_COMMON_CONFIG
//
UINT16 HotPlug : 1; // If hotplug is supported on slot connected to this port
UINT16 MrlSensorPresent : 1; // If MRL is present on slot connected to this port
UINT16 SlotPowerLimitScale : 2; // Slot Power Scale for slot connected to this port
UINT16 SlotPowerLimitValue : 12; // Slot Power Value for slot connected to this port
UINT16 PhysicalSlotNumber; // Slot number for slot connected to this port
} IIO_BOARD_SETTINGS_PER_PORT;
typedef enum {
IioBifurcation_UNKNOWN = IIO_BIFURCATE_xxxxxxxx,
IioBifurcation_x4x4x4x4 = IIO_BIFURCATE_x4x4x4x4,
@ -271,6 +265,13 @@ typedef enum {
IioBifurcation_x2x2x4x2x2x2x2 = IIO_BIFURCATE_x2x2x4x2x2x2x2,
IioBifurcation_x4x2x2x2x2x2x2 = IIO_BIFURCATE_x4x2x2x2x2x2x2,
IioBifurcation_x2x2x2x2x2x2x2x2 = IIO_BIFURCATE_x2x2x2x2x2x2x2x2,
IioBifurcation_xxxxxxx4 = IIO_BIFURCATE_xxxxxxx4,
IioBifurcation_xxx2xxx2 = IIO_BIFURCATE_xxx2xxx2,
IioBifurcation_x1x1xxx2 = IIO_BIFURCATE_x1x1xxx2,
IioBifurcation_xxx2x1x1 = IIO_BIFURCATE_xxx2x1x1,
IioBifurcation_x1x1x1x1 = IIO_BIFURCATE_x1x1x1x1,
IioBifurcation_Auto = IIO_BIFURCATE_AUTO
} IIO_BIFURCATION;
@ -286,6 +287,9 @@ typedef struct {
IIO_BOARD_SETTINGS_PER_PE Pe[MAX_IIO_PCIE_PER_SOCKET];
} IIO_BOARD_SETTINGS_PER_SOCKET;
//
// HOB to store board settings data created based on UBA data
//
typedef struct {
IIO_BOARD_SETTINGS_PER_SOCKET Socket[MAX_SOCKET];
} IIO_BOARD_SETTINGS_HOB;

323
src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/IioUniversalDataHob.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -26,108 +26,69 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _IIO_UNIVERSAL_DATA_HOB_H_
#define _IIO_UNIVERSAL_DATA_HOB_H_
#define DINO_UID 0
#define PC_UID 1
#define UB_UID 4
#define CPM0_UID 5
#define HQM0_UID 6
#define IIO_UNIVERSAL_DATA_GUID { \
0xa1, 0x96, 0xf3, 0x7f, 0x7d, 0xee, 0x1e, 0x43, \
0xba, 0x53, 0x8f, 0xCa, 0x12, 0x7c, 0x44, 0xc0 \
}
#define IIO_UNIVERSAL_DATA_GUID { 0x7FF396A1, 0xEE7D, 0x431E, { 0xBA, 0x53, 0x8F, 0xCA, 0x12, 0x7C, 0x44, 0xC0 } }
#ifndef MAX_SOCKET
#define MAX_SOCKET 4
#define MAX_SOCKET 2
#endif
#if (MAX_SOCKET == 1)
#define MAX_FW_KTI_PORTS 4 // Maximum KTI PORTS to be used in structure definition.
#define MAX_FW_KTI_PORTS 4 // Maximum KTI PORTS to be used in structure definition.
#else
#define MAX_FW_KTI_PORTS 6 // Maximum KTI PORTS to be used in structure definition
#define MAX_FW_KTI_PORTS 6 // Maximum KTI PORTS to be used in structure definition
#endif //(MAX_SOCKET == 1)
#ifndef MAX_IMC
#define MAX_IMC 4 // Maximum memory controllers per socket
#endif
#ifndef MAX_MC_CH
#define MAX_MC_CH 2 // Max number of channels per MC (3 for EP)
#endif
#ifndef MAX_CH
#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
#endif
#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max number of memory nodes
#ifndef MAX_IIO_PORTS_PER_SOCKET
#define MAX_IIO_PORTS_PER_SOCKET 57
#endif
#ifndef MAX_IIO_PORTS_PER_STACK
#define MAX_IIO_PORTS_PER_STACK 8
#endif
#define MAX_LOGIC_IIO_STACK 18
#ifndef MAX_IIO_PCIROOTS_PER_STACK
#define MAX_IIO_PCIROOTS_PER_STACK 1
#define MAX_IIO_PCIROOTS_PER_STACK 3 // PCI roots that can be created for a stack
#endif
#ifndef MAX_IIO_STACK
#define MAX_IIO_STACK 12
#define MAX_COMPUTE_DIE 3
#define MAX_CHA_MAP (2 * MAX_COMPUTE_DIE) //for GNR & SRF only, each compute die has its own CAPID6 & CAPID7 (i.e. 2 CAPID registers)
#ifndef MAX_MESSAGE_LENGTH
#define MAX_MESSAGE_LENGTH 500
#endif
#define MAX_LOGIC_IIO_STACK 14
#define DINO_UID 0
#define PC_UID 1
#define UB_UID 4
#define CPM0_UID 5
#define HQM0_UID 6
#define MAX_COMPUTE_DIE 1
#define MAX_CHA_MAP (2 * MAX_COMPUTE_DIE) //for GNR & SRF only, each compute die has its own CAPID6 & CAPID7 (i.e. 2 CAPID registers)
#pragma pack(1)
typedef struct _UINT64_STRUCT {
UINT32 lo;
UINT32 hi;
} UINT64_STRUCT, *PUINT64_STRUCT;
#ifndef MMIO_BARS_ENUM
#define MMIO_BARS_ENUM
typedef enum {
TYPE_SCF_BAR = 0,
TYPE_PCU_BAR,
TYPE_MEM_BAR0,
TYPE_MEM_BAR1,
TYPE_MEM_BAR2,
TYPE_MEM_BAR3,
TYPE_MEM_BAR4,
TYPE_MEM_BAR5,
TYPE_MEM_BAR6,
TYPE_MEM_BAR7,
TYPE_SBREG_BAR,
TYPE_MAX_MMIO_BAR
} MMIO_BARS;
#endif
typedef struct {
UINT8 Device;
UINT8 Function;
} IIO_PORT_INFO;
typedef struct {
UINT8 Major;
UINT8 Minor;
UINT8 Revision;
UINT16 BuildNumber;
} RC_VERSION;
IioStack0 = 0,
IioStack1 = 1,
IioStack2 = 2,
IioStack3 = 3,
IioStack4 = 4,
IioStack5 = 5,
IioStack6 = 6,
IioStack7 = 7,
IioStack8 = 8,
IioStack9 = 9,
IioStack10 = 10,
IioStack11 = 11,
IioStack12 = 12,
IioStack13 = 13,
IioStack14 = 14,
IioStack15 = 15,
IioStack16 = 16,
IioStackUnknown = 0xFF
} IIO_STACK;
//--------------------------------------------------------------------------------------//
// Structure definitions for Universal Data Store (UDS)
//--------------------------------------------------------------------------------------//
#pragma pack(1)
typedef struct {
UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation)
UINT8 PeerSocId; // Socket ID
@ -137,52 +98,16 @@ typedef struct {
typedef struct {
UINT8 Valid;
UINT32 MmioBar[TYPE_MAX_MMIO_BAR];
UINT8 PcieSegment;
UINT64_STRUCT SegMmcfgBase;
UINT64 SegMmcfgBase;
UINT32 StackPresentBitmap;
UINT16 CxlPresentBitmap;
UINT16 Cxl20CapableBitmap;
UINT8 TotM3Kti;
UINT16 Cxl1p1PresentBitmap; // Bitmap of stacks where CXL 1p1 is connected
UINT16 CxlCapableBitmap; // Bitmap of stacks capable of CXL
UINT8 TotCha;
UINT32 ChaList[MAX_CHA_MAP];
UINT32 SocId;
QPI_PEER_DATA PeerInfo[MAX_FW_KTI_PORTS]; // QPI LEP info
} QPI_CPU_DATA;
typedef struct {
UINT8 Valid;
UINT8 SocId;
QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info
} QPI_IIO_DATA;
typedef struct {
IIO_PORT_INFO PortInfo[MAX_IIO_PORTS_PER_SOCKET];
} IIO_DMI_PCIE_INFO;
typedef struct _STACK_RES {
UINT8 Personality;
UINT8 BusBase; // Base of Bus configured for this stack
UINT8 BusLimit; // Limit of Bus configured for this stack
UINT16 IoBase; // Base of IO configured for this stack
UINT16 IoLimit; // Limit of IO configured for this stack
UINT32 IoApicBase;
UINT32 IoApicLimit;
UINT32 Mmio32Base; // Base of low MMIO configured for this stack in memory map
UINT32 Mmio32Limit; // Limit of low MMIO configured for this stack in memory map
UINT64 Mmio64Base; // Base of high MMIO configured for this stack in memory map
UINT64 Mmio64Limit; // Limit of high MMIO configured for this stack in memory map
UINT8 PciResourceBusBase; // Base of Bus resource available for PCI devices
UINT8 PciResourceBusLimit; // Limit of Bus resource available for PCI devices
UINT16 PciResourceIoBase; // Base of IO resource available for PCI devices
UINT16 PciResourceIoLimit; // Limit of IO resource available for PCI devices
UINT32 PciResourceMem32Base; // Base of low MMIO resource available for PCI devices
UINT32 PciResourceMem32Limit; // Limit of low MMIO resource available for PCI devices
UINT64 PciResourceMem64Base; // Base of high MMIO resource available for PCI devices
UINT64 PciResourceMem64Limit; // Limit of high MMIO resource available for PCI devices
UINT32 VtdBarAddress; // NOTE: Obsolete, not used in next gen platforms
} STACK_RES;
/**
* PCI resources that establish one PCI hierarchy for PCI Enumerator.
*/
@ -198,122 +123,87 @@ typedef struct {
UINT64 Mmio64Limit; // Limit of high MMIO resources available for PCI devices
} UDS_PCIROOT_RES;
/**
* This structore keeps resources configured in Host I/O Processor (HIOP) for one stack.
* One HIOP may produce more than one PCI hierarchy, these are in PciRoot[] table.
*/
typedef struct {
UINT8 Personality;
UINT8 PciRootBridgeNum; // Number of valid entries in PciRoot[] table
UINT8 Segment; // Segment for this stack
UINT8 BusBase; // Base of Bus configured for this stack
UINT8 BusLimit; // Limit of Bus configured for this stack
UINT8 Reserved[3]; // Reserved for alignment
UINT16 IoBase; // Base of IO configured for this stack
UINT16 IoLimit; // Limit of IO configured for this stack
UINT32 IoApicBase;
UINT32 IoApicLimit;
UINT32 Mmio32Base; // Base of low MMIO configured for this stack in memory map
UINT32 Mmio32Limit; // Limit of low MMIO configured for this stack in memory map
UINT32 Mmio32MinSize; // The size of MMIO32 needed in PEI that must be preserved in rebalance
UINT64 Mmio64Base; // Base of high MMIO configured for this stack in memory map
UINT64 Mmio64Limit; // Limit of high MMIO configured for this stack in memory map
UDS_PCIROOT_RES PciRoot[MAX_IIO_PCIROOTS_PER_STACK];
UINT64 VtbarAddress; // VT-d Base Address
UINT64 ChbcrBarAddress;
UINT64 ChbcrBarAddress; // CXL Host Bridge Component Registers (CHBCR) region
UDS_PCIROOT_RES PciRoot[MAX_IIO_PCIROOTS_PER_STACK];
} UDS_STACK_RES;
/**
* This structore keeps resource ranges configured in one socket. It contains a table of IO stacks provided by
// the socket. The stacks are also groupded by IO dies, but dies are not reflected in UDS.
*/
typedef struct {
UINT8 Valid;
UINT8 SocketID; // Socket ID of the IIO (0..3)
UINT8 BusBase;
UINT8 BusLimit;
UINT8 SocketID; // Socket ID of the IIO (0..3)
UINT16 IoBase;
UINT16 IoLimit;
UINT32 IoApicBase;
UINT32 IoApicLimit;
UINT32 Mmio32Base; // Base of low MMIO configured for this socket in memory map
UINT32 Mmio32Limit; // Limit of low MMIO configured for this socket in memory map
UINT64 Mmio64Base; // Base of high MMIO configured for this socket in memory map
UINT64 Mmio64Limit; // Limit of high MMIO configured for this socket in memory map
UINT32 Mmio32Base; // Base of low MMIO configured for this socket in memory map
UINT32 Mmio32Limit; // Limit of low MMIO configured for this socket in memory map
UINT64 Mmio64Base; // Base of high MMIO configured for this socket in memory map
UINT64 Mmio64Limit; // Limit of high MMIO configured for this socket in memory map
UDS_STACK_RES StackRes[MAX_LOGIC_IIO_STACK];
} UDS_SOCKET_RES;
/**
* This structore keeps resource ranges configured in whole system.
*/
typedef struct {
UINT8 Valid;
UINT8 SocketID; // Socket ID of the IIO (0..3)
UINT8 BusBase;
UINT8 BusLimit;
UINT16 PciResourceIoBase;
UINT16 PciResourceIoLimit;
UINT32 IoApicBase;
UINT32 IoApicLimit;
UINT32 Mmio32Base; // Base of low MMIO configured for this socket in memory map
UINT32 Mmio32Limit; // Limit of low MMIO configured for this socket in memory map
UINT64 Mmio64Base; // Base of high MMIO configured for this socket in memory map
UINT64 Mmio64Limit; // Limit of high MMIO configured for this socket in memory map
UDS_STACK_RES StackRes[MAX_LOGIC_IIO_STACK];
IIO_DMI_PCIE_INFO PcieInfo; // NOTE: Obsolete, not used in next gen platforms
} IIO_RESOURCE_INSTANCE;
typedef struct {
UINT16 PlatGlobalIoBase; // Global IO Base
UINT16 PlatGlobalIoLimit; // Global IO Limit
UINT32 PlatGlobalMmio32Base; // Global Mmiol base
UINT32 PlatGlobalMmio32Limit; // Global Mmiol limit
UINT64 PlatGlobalMmio64Base; // Global Mmioh Base [43:0]
UINT64 PlatGlobalMmio64Limit; // Global Mmioh Limit [43:0]
QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU
QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO
UINT16 SystemIoBase; // System IO Base
UINT16 SystemIoLimit; // System IO Limit
UINT32 SystemMmio32Base; // System low MMIO base
UINT32 SystemMmio32Limit;
UINT32 Mmio32Granularity;
UINT64 SystemMmio64Base; // System high MMIO Base
UINT64 SystemMmio64Limit; // System high MMIO Limit
UINT64 Mmio64Granularity;
UINT32 MemTsegSize;
UINT64 PciExpressBase;
UINT32 PciExpressSize;
UINT32 MemTolm;
UDS_SOCKET_RES IIO_resource[MAX_SOCKET];
UINT8 numofIIO;
UINT8 MaxBusNumber;
UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
UINT8 EVMode;
UINT8 SkuPersonality[MAX_SOCKET];
UINT16 IoGranularity;
UINT32 MmiolGranularity;
UINT64_STRUCT MmiohGranularity;
UINT8 RemoteRequestThreshold; //5370389
UINT32 UboxMmioSize;
UINT32 MaxAddressBits;
UINT16 SystemIoBase; // System IO Base
UINT16 SystemIoLimit; // System IO Limit
UINT32 SystemIoApicBase; // Legacy IOAPIC base address, one in the system
UINT32 SystemIoApicLimit;
UINT32 SystemMmio32Base; // System low MMIO base
UINT32 SystemMmio32Limit; // System low MMIO limit
UINT64 SystemMmio64Base; // System high MMIO Base
UINT64 SystemMmio64Limit; // System high MMIO Limit
QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU
UINT64 PciExpressBase; // PCI Config Space base address
UINT64 PciExpressSize; // PCI Config Space size
UDS_SOCKET_RES IIO_resource[MAX_SOCKET];
UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
UINT16 IoGranularity;
UINT32 Mmio32Granularity;
UINT64 Mmio64Granularity;
UINT32 UboxMmioSize;
UINT32 MemTolm;
UINT32 MemTsegSize;
UINT32 MaxAddressBits;
} PLATFORM_DATA;
typedef struct {
UINT8 CurrentUpiiLinkSpeed;// Current programmed UPI Link speed (Slow/Full speed mode)
BOOLEAN FailFlag;
CHAR16 Message[MAX_MESSAGE_LENGTH];
} REBALANCE_FAIL_INFO;
typedef struct {
UINT8 CurrentUpiiLinkSpeed; // Current programmed UPI Link speed (Slow/Full speed mode)
UINT8 CurrentUpiLinkFrequency; // Current requested UPI Link frequency (in GT)
UINT8 OutKtiCpuSktHotPlugEn; // 0 - Disabled, 1 - Enabled for PM X2APIC
UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM
UINT8 IsocEnable;
UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB
UINT8 DmiVc1;
UINT8 DmiVcm;
UINT32 CpuPCPSInfo;
UINT8 cpuSubType;
UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB
UINT8 SystemRasType;
UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
UINT16 tolmLimit;
RC_VERSION RcVersion;
BOOLEAN MsrTraceEnable;
UINT8 DdrXoverMode; // DDR 2.2 Mode
// For RAS
UINT8 bootMode;
UINT8 OutClusterOnDieEn; // Whether RC enabled COD support
UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
UINT8 OutSncEn;
UINT8 OutNumOfCluster;
UINT8 imcEnabled[MAX_SOCKET][MAX_IMC];
UINT16 LlcSizeReg;
UINT8 chEnabled[MAX_SOCKET][MAX_CH];
UINT8 memNode[MC_MAX_NODE];
UINT8 IoDcMode;
UINT8 DfxRstCplBitsEn;
UINT8 BitsUsed; //For 5 Level Paging
REBALANCE_FAIL_INFO RebalanceFailInfo;
} SYSTEM_STATUS;
typedef struct {
@ -322,32 +212,7 @@ typedef struct {
UINT32 OemValue;
} IIO_UDS;
typedef enum {
//for ICX
IioStack0 = 0, // DmiAsPcie
IioStack1 = 1, // IOU0
IioStack2 = 2, // IOU1
IioStack3 = 3, // IOU2
IioStack4 = 4, // IOU3
IioStack5 = 5, // IOU4
//for SPR
IioStack6 = 6, // IOU5
IioStack7 = 7,
IioStack8 = 8,
IioStack9 = 9,
IioStack10 = 10,
IioStack11 = 11,
//for later SOC
IioStack12 = 12,
IioStack13 = 13,
IioStack14 = 14,
IioStack15 = 15,
IioStack16 = 16,
IioStack17 = 17,
IioStack18 = 18,
IioStackUnknown = 0xFF
} IIO_STACK;
#pragma pack()
#endif //#ifndef _IIO_UNIVERSAL_DATA_HOB_H_
#endif // _IIO_UNIVERSAL_DATA_HOB_H_

221
src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/MemoryMapDataHob.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -26,6 +26,8 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _MEMORY_MAP_DATA_HOB_H_
@ -34,37 +36,51 @@ are permitted provided that the following conditions are met:
#define MEMORY_MAP_HOB_GUID { 0xf8870015, 0x6994, 0x4b98, { 0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f } }
#ifndef MAX_SOCKET
#define MAX_SOCKET 4
#define MAX_SOCKET 2
#endif
#ifndef MAX_IMC
#define MAX_IMC 4 // Maximum memory controllers per socket
#define MAX_IMC 12 // Maximum memory controllers per socket
#endif
#ifndef MAX_MC_CH
#define MAX_MC_CH 2 // Max number of channels per MC (3 for EP)
#define MAX_MC_CH 1 // Max number of channels per MC (3 for EP)
#endif
#ifndef MAX_CH
#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
#endif
#define MAX_CXL_AMT 0
#ifndef MAX_CXL_HOST_BRIDGES
#define MAX_CXL_HOST_BRIDGES 0x6 // Maximum number of CXL host bridges per socket.
#endif
#ifndef MAX_CXL_HOST_BRIDGE_WAYS
#define MAX_CXL_HOST_BRIDGE_WAYS 0x4 // Maximum interleave ways of CXL host bridges per socket.
#endif
//
// Macro definitions for abstracted memory decoding target. The data structure is designed to
// iterate iMC and CXL host bridge host decoded memory in an unified way.
// definition for GNRSRF/GNRD/GRR
//
#define MAX_CXL_AMT MAX_CXL_HOST_BRIDGES // Max number of unique interleaves for NGN DIMM
#ifndef MAX_UNIQUE_NGN_DIMM_INTERLEAVE
#define MAX_UNIQUE_NGN_DIMM_INTERLEAVE 2 // Max number of unique interleaves for NGN DIMM
#define MAX_UNIQUE_NGN_DIMM_INTERLEAVE 2 // Max number of unique interleaves for NGN DIMM
#endif
#ifndef MAX_SPARE_RANK
#define MAX_SPARE_RANK 2 // Max number of spare ranks in a channel
#define MAX_SPARE_RANK 2 // Max number of spare ranks in a channel
#endif
#ifndef MAX_HBM_IO
#define MAX_HBM_IO 4
#define MAX_HBM_IO 4
#endif
#ifndef MAX_DIMM
#define MAX_DIMM 2 // Max DIMM per channel
#define MAX_DIMM 2 // Max DIMM per channel
#endif
#ifndef MAX_RANK_DIMM
@ -72,7 +88,7 @@ are permitted provided that the following conditions are met:
#endif
#ifndef MAX_DRAM_CLUSTERS
#define MAX_DRAM_CLUSTERS 4
#define MAX_DRAM_CLUSTERS 6
#endif
#ifndef MAX_SAD_RULES
@ -83,17 +99,17 @@ are permitted provided that the following conditions are met:
#define MAX_FPGA_REMOTE_SAD_RULES 2 // Maximum FPGA sockets exists on ICX platform
#endif
#define MAX_SI_SOCKET 8 // Maximum silicon supported socket number
#define MAX_SI_SOCKET 8 // Maximum silicon supported socket number
#define MAX_AMT (MAX_IMC+MAX_CXL_AMT) // Max abstract memory target per socket
#define AMT_MAX_NODE ((MAX_AMT)*(MAX_SOCKET)) // Max abstract memory target for all sockets
#define MAX_AMT (MAX_IMC+MAX_CXL_AMT) // Max abstract memory target per socket
#define AMT_MAX_NODE ((MAX_AMT)*(MAX_SOCKET)) // Max abstract memory target for all sockets
// NGN
#define NGN_MAX_SERIALNUMBER_STRLEN 4
#define NGN_MAX_PARTNUMBER_STRLEN 30
#define NGN_FW_VER_LEN 4
#define NGN_LOG_TYPE_NUM 2
#define NGN_LOG_LEVEL_NUM 2
#define NGN_MAX_SERIALNUMBER_STRLEN 4
#define NGN_MAX_PARTNUMBER_STRLEN 30
#define NGN_FW_VER_LEN 4
#define NGN_LOG_TYPE_NUM 2
#define NGN_LOG_LEVEL_NUM 2
/**
* Memory channel index conversion macros.
@ -115,25 +131,14 @@ are permitted provided that the following conditions are met:
#define MEM_KBYTES_TO_64MB(SizeKB) ((SizeKB) >> 16)
#define MEM_MBYTES_TO_64MB(SizeMB) ((SizeMB) >> 6)
typedef UINT8 CXL_INTLV_SET_KEY;
typedef UINT8 INTLV_SET_KEY;
#define FSP_RESERVED1_LEN 77
#define FSP_RESERVED2_LEN 2174
#define FSP_RESERVED3_LEN 21
#define FSP_RESERVED4_LEN 130
#define FSP_RESERVED5_LEN 10
#define FSP_RESERVED6_LEN 800
#define FSP_RESERVED1_LEN 5748
#define FSP_RESERVED2_LEN 1
#define FSP_RESERVED3_LEN 220
#define FSP_RESERVED4_LEN 10
#pragma pack(1)
typedef enum {
DIMM_RANK_MAP_OUT_UNKNOWN = 0,
DIMM_RANK_MAP_OUT_MEM_DECODE,
DIMM_RANK_MAP_OUT_POP_POR_VIOLATION,
DIMM_RANK_MAP_OUT_RANK_DISABLED,
DIMM_RANK_MAP_OUT_ADVMEMTEST_FAILURE,
DIMM_RANK_MAP_OUT_MAX
} DIMM_RANK_MAP_OUT_REASON;
struct RankDevice {
UINT8 enabled; // 0 = disabled, 1 = enabled
UINT8 logicalRank; // Logical Rank number (0 - 7)
@ -154,55 +159,58 @@ typedef struct firmwareRev {
} FIRMWARE_REV;
typedef struct DimmDevice {
UINT8 Present;
BOOLEAN Enabled;
UINT8 DcpmmPresent; // 1 - This is a DCPMM
UINT8 X4Present;
UINT8 DramIoWidth; // Actual DRAM IO Width (4, 8, 16)
UINT8 NumRanks;
UINT8 keyByte;
UINT8 actKeyByte2; // Actual module type reported by SPD
UINT8 actSPDModuleOrg; // Actual number of DRAM ranks and device width
UINT8 dimmTs; // Thermal sensor data.
UINT16 VolCap; // Volatile capacity (AEP DIMM only)
UINT16 nonVolCap; // Non-volatile capacity (AEP DIMM only)
UINT16 DimmSize;
UINT32 NVmemSize;
UINT16 SPDMMfgId; // Module Mfg Id from SPD
UINT16 VendorID;
UINT16 DeviceID;
UINT16 RevisionID;
UINT32 perRegionDPA; // DPA of PMEM that Nfit needs
struct PersisentDpaMap perDPAMap[MAX_UNIQUE_NGN_DIMM_INTERLEAVE]; // DPA map
UINT8 serialNumber[NGN_MAX_SERIALNUMBER_STRLEN]; // Serial Number
UINT8 PartNumber[NGN_MAX_PARTNUMBER_STRLEN]; // Part Number
UINT8 FirmwareVersionStr[NGN_FW_VER_LEN]; // Used to update the SMBIOS TYPE 17
struct firmwareRev FirmwareVersion; // Firmware revision
struct RankDevice rankList[MAX_RANK_DIMM];
UINT16 InterfaceFormatCode;
UINT16 SubsystemVendorID;
UINT16 SubsystemDeviceID;
UINT16 SubsystemRevisionID;
UINT16 FisVersion; // Firmware Interface Specification version
UINT8 DimmSku; // Dimm SKU info
UINT8 manufacturingLocation; // Manufacturing location for the NVDIMM
UINT16 manufacturingDate; // Date the NVDIMM was manufactured
INT32 commonTck;
UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
BOOLEAN NvDimmNPresent; // JEDEC NVDIMM-N Type Memory Present
UINT8 CidBitMap; // SubRankPer CS for DIMM device
UINT16 SPDRegVen; // Register Vendor ID in SPD
DIMM_RANK_MAP_OUT_REASON MapOutReason;
UINT8 Present;
BOOLEAN Enabled;
UINT8 DcpmmPresent; // 1 - This is a DCPMM
UINT8 X4Present;
UINT8 DramIoWidth; // Actual DRAM IO Width (4, 8, 16)
UINT8 NumRanks; // Number of ranks on dimm
UINT8 NumPackageRanks; // Number of Package ranks on dimm
// For DDR5 NumRanks and NumPackageRanks same
// For MCR NumRanks and NumPackageRanks may differ
UINT8 keyByte;
UINT8 actKeyByte2; // Actual module type reported by SPD
UINT8 actSPDModuleOrg; // Actual number of DRAM ranks and device width
UINT8 dimmTs; // Thermal sensor data.
UINT16 VolCap; // Volatile capacity (AEP DIMM only)
UINT16 nonVolCap; // Non-volatile capacity (AEP DIMM only)
UINT16 DimmSize;
UINT16 SPDMMfgId; // Module Mfg Id from SPD
UINT16 VendorID;
UINT16 DeviceID;
UINT16 RevisionID;
UINT32 perRegionDPA; // DPA of PMEM that Nfit needs
struct PersisentDpaMap perDPAMap[MAX_UNIQUE_NGN_DIMM_INTERLEAVE]; // DPA map
UINT8 serialNumber[NGN_MAX_SERIALNUMBER_STRLEN]; // Serial Number
UINT8 PartNumber[NGN_MAX_PARTNUMBER_STRLEN]; // Part Number
UINT8 FirmwareVersionStr[NGN_FW_VER_LEN]; // Used to update the SMBIOS TYPE 17
struct firmwareRev FirmwareVersion; // Firmware revision
struct RankDevice rankList[MAX_RANK_DIMM];
UINT16 InterfaceFormatCode;
UINT16 SubsystemVendorID;
UINT16 SubsystemDeviceID;
UINT16 SubsystemRevisionID;
UINT16 FisVersion; // Firmware Interface Specification version
UINT8 DimmSku; // Dimm SKU info
UINT8 manufacturingLocation; // Manufacturing location for the NVDIMM
UINT16 manufacturingDate; // Date the NVDIMM was manufactured
INT32 commonTck;
UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
BOOLEAN NvDimmNPresent; // JEDEC NVDIMM-N Type Memory Present
UINT8 CidBitMap; // SubRankPer CS for DIMM device
UINT16 SPDRegVen; // Register Vendor ID in SPD
UINT8 SPDOtherOptFeatures; // SDRAM Other Optional features
BOOLEAN DimmChanged;
} MEMMAP_DIMM_DEVICE_INFO_STRUCT;
struct ChannelDevice {
typedef struct ChannelDevice {
UINT8 Enabled; // 0 = channel disabled, 1 = channel enabled
UINT8 Features; // Bit mask of features to enable or disable
UINT8 MaxDimm; // Number of DIMM
UINT8 NumRanks; // Number of ranks on this channel
UINT8 chFailed;
UINT8 ngnChFailed;
UINT8 Is9x4DimmPresent; // 9x4 dimm present indicator
UINT8 Is4BitEccDimmPresent; // 4-bit Ecc dimm present indicator
UINT8 SpareLogicalRank[MAX_SPARE_RANK]; // Logical rank, selected as Spare
UINT8 SparePhysicalRank[MAX_SPARE_RANK]; // Physical rank, selected as spare
UINT16 SpareRankSize[MAX_SPARE_RANK]; // spare rank size
@ -210,11 +218,11 @@ struct ChannelDevice {
UINT8 DdrPopulationMap; // Bitmap to indicate location of DDR DIMMs within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
UINT8 PmemPopulationMap; // Bitmap to indicate location of PMem modules within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
MEMMAP_DIMM_DEVICE_INFO_STRUCT DimmInfo[MAX_DIMM];
};
} CHANNEL_DEVICE;
struct memcontroller {
typedef struct memcontroller {
UINT32 MemSize;
};
} MEMCONTROLLER;
typedef enum {
MemTypeNone = 0,
@ -251,8 +259,8 @@ typedef struct SADTable {
UINT8 FMchannelInterBitmap[MAX_AMT]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
UINT8 NmChWays; // Channel Interleave ways for SAD. Represents channelInterBitmap ways for DDR4/NM.
UINT8 FmChWays; // Channel Interleave ways for SAD. Represents FMchannelInterBitmap ways for DDRT.
UINT16 imcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket.
UINT16 NmImcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket as NM.
UINT32 imcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket.
UINT32 NmImcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket as NM.
BOOLEAN local; // 0 - Remote 1- Local
UINT8 IotEnabled; // To indicate if IOT is enabled
UINT8 mirrored; // To Indicate the SAD is mirrored while enabling partial mirroring
@ -260,8 +268,9 @@ typedef struct SADTable {
UINT8 tgtGranularity; // Interleave mode for target list
UINT8 Cluster; // SNC cluster, hemisphere, or quadrant index.
UINT8 HostBridgeGran; // Host bridge interleaving granularity.
UINT8 HostBridgeList[MAX_CXL_HOST_BRIDGE_WAYS]; // List of interleaved CXL host bridges.
UINT32 HotPlugPadSize; // Memory size padded for CXL hot plug. 0 if it is not a CXL hot plug SAD.
CXL_INTLV_SET_KEY CxlIntlvSetKey; // The unique key of CXL interleave set. (7nm)
INTLV_SET_KEY CxlIntlvSetKey; // The unique key of CXL interleave set. (7nm)
} SAD_TABLE;
typedef struct socket {
@ -271,10 +280,9 @@ typedef struct socket {
UINT8 imcEnabled[MAX_IMC];
UINT8 SadIntList[MAX_DRAM_CLUSTERS * MAX_SAD_RULES][AMT_MAX_NODE]; // SAD interleave list
UINT32 SktTotMemMapSPA; // Total memory mapped to SPA
UINT32 SktMemSize2LM; // Total memory excluded from Limit
SAD_TABLE SAD[MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; // SAD table
struct memcontroller imc[MAX_IMC];
struct ChannelDevice ChannelInfo[MAX_CH];
MEMCONTROLLER imc[MAX_IMC];
CHANNEL_DEVICE ChannelInfo[MAX_CH];
} MEMMAP_SOCKET;
typedef struct {
@ -287,9 +295,10 @@ typedef struct SystemMemoryMapElement {
UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
UINT8 NodeId; // Node ID of the HA Owning the memory
UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA
UINT8 ClusterId; // Logical cluster Id of SNC cluster - only 0 in UMA clustering and all2all
UINT8 SktInterBitmap; // Socket interleave bitmap, if more that on socket then ImcInterBitmap and ChInterBitmap are identical in all sockets
UINT16 ImcInterBitmap; // IMC interleave bitmap for this memory
UINT8 ChInterBitmap[MAX_IMC];//Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
UINT32 ImcInterBitmap; // IMC interleave bitmap for this memory
UINT8 ChInterBitmap[MAX_AMT];//Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
UINT32 BaseAddress; // Base Address of the element in 64MB chunks
UINT32 ElementSize; // Size of this memory element in 64MB chunks
} SYSTEM_MEMORY_MAP_ELEMENT;
@ -300,8 +309,6 @@ typedef struct SystemMemoryMapHob {
// All2All/Quad/Hemi modes can be considered as having only one cluster (i.e SNC1).
//
UINT8 TotalClusters;
UINT8 reserved1[FSP_RESERVED1_LEN]; // MEMORY_MAP_BLOCK_DECODER_DATA BlockDecoderData; // block decoder data structure
UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem.
UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem.
UINT32 highMemBase; // Mem base in 64MB units for above 4GB mem.
@ -310,14 +317,9 @@ typedef struct SystemMemoryMapHob {
UINT16 memFreq; // Mem Frequency
UINT16 HbmFreq; // HBM Frequency in MHz.
UINT8 memMode; // 0 - Independent, 1 - Lockstep
UINT8 volMemMode; // 0 - 1LM, 1 - 2LM
UINT8 CacheMemType; // 0 - DDR$DDRT, 1 - HBM$DDR. Only valid if volMemMode is 2LM
UINT8 VolMemMode; // 0 - 1LM, 1 - 2LM
UINT16 DramType;
UINT8 DdrVoltage;
BOOLEAN SupportedPMemPresent; // TRUE if at least one PMem is present and supported by BIOS
BOOLEAN EkvPresent; // Set if EKV controller on system
BOOLEAN BwvPresent; // Set if BWV controller on system
BOOLEAN CwvPresent; // Set if CWV controller on system
UINT8 XMPProfilesSup;
UINT8 XMPCapability;
//
@ -336,35 +338,20 @@ typedef struct SystemMemoryMapHob {
UINT8 NumChPerMC;
UINT8 numberEntries; // Number of Memory Map Elements
SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES];
UINT8 reserved2[FSP_RESERVED2_LEN]; // struct memSetup MemSetup;
UINT8 reserved3[FSP_RESERVED3_LEN]; // MEM_DFXMEMVARS DfxMemVar;
UINT8 reserved1[FSP_RESERVED1_LEN]; // struct memSetup MemSetup;
UINT8 reserved2[FSP_RESERVED2_LEN]; // MEM_DFXMEMVARS DfxMemVar;
MEMMAP_SOCKET Socket[MAX_SOCKET];
UINT8 reserved4[FSP_RESERVED4_LEN]; // struct memTiming profileMemTime[XMP_MAX_PROFILES];
UINT8 reserved3[FSP_RESERVED3_LEN]; // struct memTiming profileMemTime[XMP_MAX_PROFILES];
UINT8 reserved5[FSP_RESERVED5_LEN]; // RASMEMORYINFO RasMeminfo;
UINT8 LatchSystemShutdownState;
BOOLEAN IsWpqFlushSupported;
UINT8 EadrSupport;
UINT8 EadrCacheFlushMode;
UINT8 SetSecureEraseSktChHob[MAX_SOCKET][MAX_CH]; //MAX_CH * MAX_SOCKET * MAX_DCPMM_CH
UINT8 reserved6[FSP_RESERVED6_LEN]; // HOST_DDRT_DIMM_DEVICE_INFO_STRUCT HostDdrtDimmInfo[MAX_SOCKET][MAX_CH];
UINT8 reserved4[FSP_RESERVED4_LEN]; // RASMEMORYINFO RasMeminfo;
UINT32 DdrCacheSize[MAX_SOCKET][MAX_CH]; // Size of DDR memory reserved for 2LM cache (64MB granularity)
BOOLEAN AdrStateForPmemModule[MAX_SOCKET][MAX_CH]; // ADR state for Intel PMEM Modules
UINT16 BiosFisVersion; // Firmware Interface Specification version currently supported by BIOS
UINT16 MaxAveragePowerLimit; // Max Power limit in mW used for averaged power ( Valid range ends at 15000mW)
UINT16 MinAveragePowerLimit; // Min Power limit in mW used for averaged power ( Valid range starts from 10000mW)
UINT16 CurrAveragePowerLimit; // Current Power limit in mW used for average power
UINT16 MaxMbbPowerLimit; // Max MBB power limit ( Valid range ends at 18000mW).
UINT16 MinMbbPowerLimit; // Min MBB power limit ( Valid range starts from 15000mW).
UINT16 CurrMbbPowerLimit; // Current Power limit in mW used for MBB power
UINT32 MaxMbbAveragePowerTimeConstant; // Max MBB Average Power Time Constant
UINT32 MinMbbAveragePowerTimeConstant; // Min MBB Average Power Time Constant
UINT32 CurrMbbAveragePowerTimeConstant; // Current MBB Average Power Time Constant
UINT32 MmiohBase; // MMIOH base in 64MB granularity
UINT8 MaxSadRules; // Maximum SAD entries supported by silicon (24 for 14nm silicon, 16 for 10nm silicon)
UINT8 MaxSadRules; // Maximum SAD entries supported by silicon (16 for 10nm silicon)
UINT8 NumberofChaDramClusters; // Number of CHA DRAM decoder clusters
BOOLEAN VirtualNumaEnable; // Enable or Disable Virtual NUMA
UINT8 VirtualNumOfCluster; // Number of Virtual NUMA nodes in each physical NUMA node (Socket or SNC cluster)
UINT8 VirtualNumaNodes; // Number of virtual NUMA nodes per physical NUMA node (non-zero)
BOOLEAN McrMemFreqRangeEn; // MCR Memory Frequency range enabled.
} SYSTEM_MEMORY_MAP_HOB;
#pragma pack()

7
src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/PrevBootErrSrcHob.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -26,13 +26,14 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _PREV_BOOT_ERR_SRC_HOB_H_
#define _PREV_BOOT_ERR_SRC_HOB_H_
#define FSP_PREV_BOOT_ERR_SRC_HOB_GUID \
{ 0xc5, 0xb5, 0x38, 0x51, 0x69, 0x93, 0xec, 0x48, 0x5b, 0x97, 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 }
#define FSP_PREV_BOOT_ERR_SRC_HOB_GUID { 0x5138b5c5, 0x9369, 0x48ec, { 0x5b, 0x97, 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 } }
#define PREV_BOOT_ERR_SRC_HOB_SIZE 1000

52
src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/SystemInfoHob.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -26,42 +26,41 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _SYSTEM_INFO_HOB_H_
#define _SYSTEM_INFO_HOB_H_
#define SYSTEM_INFO_HOB_GUID { 0x7650A0F2, 0x0D91, 0x4B0C, { 0x92, 0x3B, 0xBD, 0xCF, 0x22, 0xD1, 0x64, 0x35 }}
#define SYSTEM_INFO_HOB_GUID { 0x7650A0F2, 0x0D91, 0x4B0C, { 0x92, 0x3B, 0xBD, 0xCF, 0x22, 0xD1, 0x64, 0x35 } }
#ifndef MAX_SOCKET
#define MAX_SOCKET 4
#define MAX_SOCKET 2
#endif
#ifndef MAX_IIO_STACK
#define MAX_IIO_STACK 12
#define MAX_IIO_STACK 16
#endif
#define MAX_LOGIC_IIO_STACK 14
#define MAX_LOGIC_IIO_STACK 18
#define MAX_HPM_PFS_ENTRY_NUM 15 // Number of entries in PFS structure
#define HPM_PFS_ENTRY_SIZE 2 // Entry size of PFS structure in DWORD
#ifndef MAX_IMC
#define MAX_IMC 4 // Maximum memory controllers per socket
#define MAX_IMC 12 // Maximum memory controllers per socket
#endif
#ifndef MAX_MC_CH
#define MAX_MC_CH 2 // Max number of channels per MC (3 for EP)
#define MAX_MC_CH 1 // Max number of channels per MC (3 for EP)
#endif
#ifndef MAX_CH
#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
#endif
#define MAX_HPM_PFS_ENTRY_NUM 15 // Number of entries in PFS structure
#define HPM_PFS_ENTRY_SIZE 2 // Entry size of PFS structure in DWORD
#pragma pack(1)
#ifndef MMIO_BARS_ENUM
#define MMIO_BARS_ENUM
typedef enum {
TYPE_SCF_BAR = 0,
TYPE_PCU_BAR,
@ -76,7 +75,6 @@ typedef enum {
TYPE_SBREG_BAR,
TYPE_MAX_MMIO_BAR
} MMIO_BARS;
#endif
typedef enum {
ReservedMemSs,
@ -95,7 +93,7 @@ typedef enum BootMode {
// in addition to the sub-boot type (WarmBoot, WarmBootFast, etc).
S3Resume = 1 // S3 flow through RC. Should do the bare minimum required for S3
// init and be optimized for speed.
} BootMode;
} BOOT_MODE;
//
// This is used to determine what type of die is connected to a UPI link
@ -163,19 +161,6 @@ typedef struct {
} HPM_VSEC_RESOURCE;
//
// Stack id swap information, which includes stack swap flag and the new stack id swap array.
//
typedef struct {
BOOLEAN StackSwapFlag;
UINT8 StackIdSwapArray[MAX_IIO_STACK];
} STACKID_SWAP_INFO;
typedef struct {
UINT64 Cxl1p1RcrbBase;
BOOLEAN Cxl1p1RcrbValid;
} CXL_1P1_RCRB;
typedef struct {
UINT32 StackPresentBitmap[MAX_SOCKET]; ///< bitmap of present stacks per socket
UINT8 StackBus[MAX_SOCKET][MAX_LOGIC_IIO_STACK];///< Bus of each stack
@ -188,7 +173,6 @@ typedef struct {
UINT8 segmentSocket[MAX_SOCKET];
UINT8 KtiPortCnt;
UINT32 socketPresentBitMap;
UINT32 SecondaryNodeBitMap;
UINT32 FpgaPresentBitMap;
UINT32 mmCfgBase;
UINT64 SocketMmCfgBase[MAX_SOCKET];
@ -220,13 +204,17 @@ typedef struct {
BOOLEAN DataPopulated; // CPU_CSR_ACCESS_VAR is unavailable when FALSE
HPM_VSEC_RESOURCE SocketHpmVsecRes[MAX_SOCKET]; // HPM VSEC info for all sockets
BOOLEAN HbmSku;
UINT8 HcxType[MAX_SOCKET];
STACKID_SWAP_INFO StackIdSwapInfo[MAX_SOCKET]; //StackID sync after do StackId swap,including Stack swap table and whether do stack swap
CXL_1P1_RCRB Cxl1p1Rcrb[MAX_SOCKET][MAX_IIO_STACK]; // CXL 1.1 RCRB, one per PI5 stack
UINT64 Cxl1p1Rcrb[MAX_SOCKET][MAX_IIO_STACK]; // CXL 1.1 RCRB, one per PI5 stack
UINT64 CxlRbBar[MAX_SOCKET][MAX_IIO_STACK]; // CXL RBBAR, one per PI5 stack
UINT32 DmiRcrb[MAX_SOCKET]; // DMI RCRB region, one per socket
UINT8 FabricType; //Compute die 10x6, 10x5, and 6x5 type is stored
UINT8 ChopType; //Compute Die Chop Type
UINT8 MdfInstCount;
UINT32 UboxMmioSize;
UINT32 UboxScfMmioSize;
UINT64 PpinValue[MAX_SOCKET]; // The Protected Processor Inventory Number from CPU MSRs
UINT32 OobMsmPciBaseAddress[MAX_SOCKET];
UINT32 S3mControlRegisterBaseAddress[MAX_SOCKET];
} CPU_CSR_ACCESS_VAR;
typedef struct {
@ -261,7 +249,7 @@ typedef struct {
UINT32 CheckPoint;
UINT8 ResetRequired;
UINT8 Emulation;
BootMode SysBootMode;
BOOT_MODE SysBootMode;
CPU_CSR_ACCESS_VAR CpuCsrAccessVarHost; // Common resource for CsrAccessRoutines
UINT64 CpuFreq;
UINT8 SocketId;

16
src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/CxlNodeHob.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -26,25 +26,32 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _CXL_NODE_HOB_
#define _CXL_NODE_HOB_
#define CXL_NODE_HOB_GUID { 0xdd8ae009, 0xda5a, 0x44a3, { 0xbe, 0x18, 0xda, 0x0c, 0x16, 0xc5, 0xaf, 0x5c } }
#define CXL_NODE_HOB_GUID { 0xdd8ae009, 0xda5a, 0x44a3, { 0xbe, 0x18, 0xda, 0x0c, 0x16, 0xc5, 0xaf, 0x5c } }
#ifndef MAX_IIO_STACK
#define MAX_IIO_STACK 16
#endif
#ifndef MAX_CXL_HDM_RANGES
#define MAX_CXL_HDM_RANGES 0x2 // Maximum number of CXL HDM ranges per CXL end device.
#endif
#ifndef MAX_CXL_PER_SOCKET
#define MAX_CXL_PER_SOCKET 8
#define MAX_CXL_PER_SOCKET MAX_IIO_STACK
#endif
#define CXL_NODE_ATTR_MEM BIT0
#define CXL_NODE_ATTR_PERSISTENT BIT1
#define CXL_NODE_ATTR_MEM_HW_INIT BIT2
#define CXL_NODE_ATTR_ACCELERATOR BIT3
#define CXL_NODE_ATTR_HOT_PLUGGABLE BIT4
typedef UINT32 CXL_NODE_ATTR;
@ -75,6 +82,7 @@ typedef struct {
UINT32 Size;
UINT8 Ways;
UINT8 SocketBitmap;
BOOLEAN AcpiSratSpMemFlag;
CXL_EFI_MEM_TYPE EfiMemType;
CXL_PERF_DATA InitiatorPerfData; // Performance data between device egress and initiator.
CXL_PERF_DATA TargetPerfData; // Performance data of entire target memory region.
@ -86,7 +94,7 @@ typedef struct {
//
// CXL node info for UEFI memory map and ACPI tables construction
//
CXL_NODE_INFO CxlNodeInfo[MAX_CXL_PER_SOCKET * MAX_CXL_HDM_RANGES];
CXL_NODE_INFO CxlNodeInfo[MAX_IIO_STACK * MAX_CXL_HDM_RANGES];
} CXL_NODE_SOCKET;
#pragma pack()

169
src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/EnhancedWarningLogLib.h
View file

@ -1,169 +0,0 @@
/** @file
Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
**/
#ifndef _ENHANCED_WARNING_LOG_LIB_
#define _ENHANCED_WARNING_LOG_LIB_
#define FSP_RESERVED_LEN 12
#pragma pack(1)
///
/// Enhanced Warning Log Header
///
typedef struct {
EFI_GUID EwlGuid; /// GUID that uniquely identifies the EWL revision
UINT32 Size; /// Total size in bytes including the header and buffer
UINT32 FreeOffset; /// Offset of the beginning of the free space from byte 0
/// of the buffer immediately following this structure
/// Can be used to determine if buffer has sufficient space for next entry
UINT32 Crc; /// 32-bit CRC generated over the whole size minus this crc field
/// Note: UEFI 32-bit CRC implementation (CalculateCrc32) (References [7])
/// Consumers can ignore CRC check if not needed.
UINT32 Reserved; /// Reserved for future use, must be initialized to 0
} EWL_HEADER;
///
/// List of all entry types supported by this revision of EWL
///
typedef enum {
EwlType0 = 0,
EwlType1 = 1,
EwlType2 = 2,
EwlType3 = 3,
EwlType4 = 4,
EwlType5 = 5,
EwlType6 = 6,
EwlType7 = 7,
EwlType8 = 8,
EwlType9 = 9,
EwlType10 = 10,
EwlType11 = 11,
EwlType12 = 12,
EwlType13 = 13,
EwlType14 = 14,
EwlType15 = 15,
EwlType16 = 16,
EwlType17 = 17,
EwlType18 = 18,
EwlType19 = 19,
EwlType20 = 20,
EwlType21 = 21,
EwlType22 = 22,
EwlType23 = 23,
EwlType24 = 24,
EwlType25 = 25,
EwlType26 = 26,
EwlType27 = 27,
EwlType28 = 28,
EwlType29 = 29,
EwlType30 = 30,
EwlType31 = 31,
EwlType32 = 32,
EwlTypeMax,
EwlTypeOem = 0x8000,
EwlTypeDelim = MAX_INT32
} EWL_TYPE;
///
/// EWL severities
///
typedef enum {
EwlSeverityInfo,
EwlSeverityWarning,
EwlSeverityFatal,
EwlSeverityMax,
EwlSeverityDelim = MAX_INT32
} EWL_SEVERITY;
///
/// Generic entry header for parsing the log
///
typedef struct {
EWL_TYPE Type;
UINT16 Size; /// Entries will be packed by byte in contiguous space
EWL_SEVERITY Severity; /// Warning, error, informational, this may be extended in the future
} EWL_ENTRY_HEADER;
///
/// Legacy content provides context of the warning
///
typedef struct {
UINT8 MajorCheckpoint; // EWL Spec - Appendix B
UINT8 MinorCheckpoint;
UINT8 MajorWarningCode; // EWL Spec - Appendix A
UINT8 MinorWarningCode;
} EWL_ENTRY_CONTEXT;
///
/// Legacy content to specify memory location
///
typedef struct {
UINT8 Socket; /// 0xFF = n/a
UINT8 Channel; /// 0xFF = n/a
UINT8 PseudoChannel; /// 0xFF = n/a
UINT8 Dimm; /// 0xFF = n/a
UINT8 Rank; /// 0xFF = n/a
} EWL_ENTRY_MEMORY_LOCATION;
///
/// Type 3 = Enhanced type for command, control IO errors
///
typedef struct {
EWL_ENTRY_HEADER Header;
EWL_ENTRY_CONTEXT Context;
EWL_ENTRY_MEMORY_LOCATION MemoryLocation;
UINT8 reserved1[FSP_RESERVED_LEN]; // MRC_LT Level; MRC_GT Group; GSM_CSN Signal;
UINT8 EyeSize; // 0xFF = n/a
} EWL_ENTRY_TYPE3;
#pragma pack()
///
/// Enhanced Warning Log Spec defined data log structure
///
typedef struct {
EWL_HEADER Header; /// The size will vary by implementation and should not be assumed
UINT8 Buffer[4 * 1024]; /// The spec requirement is that the buffer follow the header
} EWL_PUBLIC_DATA;
///
/// EWL private data structure. This is going to be implementation dependent
/// When we separate OEM hooks via a PPI, we can remove this
///
typedef struct {
UINT32 bufSizeOverflow; // Number of bytes that could not be added to buffer
UINT32 numEntries; // Number of entries currently logged
EWL_PUBLIC_DATA status; // Spec defined EWL
} EWL_PRIVATE_DATA;
#endif // #ifndef _ENHANCED_WARNING_LOG_LIB_

59
src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FirmwareVersionInfoHob.h
View file

@ -1,59 +0,0 @@
/** @file
Header file for Firmware Version Information
@copyright
Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
#define _FIRMWARE_VERSION_INFO_HOB_H_
#include <Uefi/UefiMultiPhase.h>
#include <Pi/PiBootMode.h>
#include <Pi/PiHob.h>
#pragma pack(1)
///
/// Firmware Version Structure
///
typedef struct {
UINT8 MajorVersion;
UINT8 MinorVersion;
UINT8 Revision;
UINT16 BuildNumber;
} FIRMWARE_VERSION;
///
/// Firmware Version Information Structure
///
typedef struct {
UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
} FIRMWARE_VERSION_INFO;
#ifndef __SMBIOS_STANDARD_H__
///
/// The Smbios structure header.
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Handle;
} SMBIOS_STRUCTURE;
#endif
///
/// Firmware Version Information HOB Structure
///
typedef struct {
EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
UINT8 Count; ///< Offset 28 Number of FVI elements included.
///
/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
///
} FIRMWARE_VERSION_INFO_HOB;
#pragma pack()
#endif // _FIRMWARE_VERSION_INFO_HOB_H_

21
src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspAcpiHobs.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -26,15 +26,28 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _FSP_ACPI_HOBS_H_
#define _FSP_ACPI_HOBS_H_
#ifndef __FSP_ACPI_HOBS__
#define __FSP_ACPI_HOBS__
//Typecast HOB pointer to APEI table structure of ACPI version 6.2
#define FSP_RAS_ACPI_HOB_GUID { 0x826785ee, 0xa8e0, 0x4d8f, { 0x82, 0x6f, 0x54, 0x29, 0x2c, 0xe7, 0x6f, 0xe6 } }
//Typecast HOB pointer to ACPI CXL CEDT table structure
#define FSP_CXL_CEDT_ACPI_HOB_GUID { 0x5CB7A12A, 0x8B2D, 0x485A, { 0xB7, 0x04, 0xC0, 0x52, 0x49, 0x56, 0x81, 0xE7 } }
// Typecast HOB pointer to MEM_TRAINING_DATA_HOB_HEADER.
// User with NDA clearance should refer to RC code for latest structure definition.
#define FSP_MEM_TRAINING_DATA_HOB_GUID { 0x7e8b89e2, 0x8b84, 0x4cb3, { 0x86, 0x8f, 0x10, 0xb6, 0x78, 0x71, 0xa2, 0xc0 }}
// Typecast HOB pointer to EWL_PRIVATE_DATA.
// User with NDA clearance should refer to RC code for latest structure definition.
#define FSP_EWL_ID_HOB_GUID { 0xd8e05800, 0x5e, 0x4462, { 0xaa, 0x3d, 0x9c, 0x6b, 0x47, 0x4, 0x92, 0xb } };
//Typecast HOB pointer to RAS_ACPI_PARAM_HOB_DATA;
#define RAS_ACPI_PARAM_HOB_GUID {0x594dfe5c, 0x7a87, 0x49dc, { 0x8f, 0x33, 0xea, 0x83, 0x4d, 0x6f, 0x18, 0x90 } }
#endif //#ifndef _FSP_ACPI_HOBS_H_
#endif // __FSP_ACPI_HOBS__

17
src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspEas.h
View file

@ -1,17 +0,0 @@
/** @file
Intel FSP definition from Intel Firmware Support Package External
Architecture Specification v2.2.
@copyright
Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _FSP_EAS_H_
#define _FSP_EAS_H_
#include <Uefi.h>
#include <Guid/GuidHobFspEas.h>
#include <Guid/FspHeaderFile.h>
#include <FspEas/FspApi.h>
#endif // _FSP_EAS_H_

4
src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspEdpcParam.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -26,6 +26,8 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSP_EDPC_PARAM__

21
src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspErrorInfoHob.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -26,20 +26,23 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _FSP_ERROR_INFO_HOB_H_
#define _FSP_ERROR_INFO_HOB_H_
#include <Uefi/UefiMultiPhase.h>
#include <Pi/PiBootMode.h>
#include <Pi/PiHob.h>
#include <Pi/PiStatusCode.h>
#define FSP_ERROR_INFO_HOB_GUID { 0x611e6a88, 0xadb7, 0x4301, { 0x93, 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6 }}
///
/// GUID value indicating the FSP error information.
///
#define FSP_ERROR_INFO_HOB_GUID { 0x611e6a88, 0xadb7, 0x4301, { 0x93, 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6 } }
#define FSP_ERROR_INFO_STATUS_CODE_TYPE (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED)
///
/// FSP Error Information Block.
///
#pragma pack(1)
typedef struct {
///
/// GUID HOB header.
@ -81,4 +84,4 @@ typedef struct {
#pragma pack()
#endif //#ifndef _FSP_ERROR_INFO_HOB_H_
#endif //_FSP_ERROR_INFO_H_

70
src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspExtMemoryPprHob.h Normal file
View file

@ -0,0 +1,70 @@
/** @file
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _FSP_EXT_MEMORY_PPR_HOB_H_
#define _FSP_EXT_MEMORY_PPR_HOB_H_
#include "FspGlobals.h"
#define FSP_EXT_MEMORY_PPR_HOB_GUID { 0x3956C6DA, 0x35B6, 0x4036, { 0x93, 0xE4, 0xB1, 0x51, 0x38, 0x60, 0x21, 0x1E } }
#pragma pack(1)
typedef struct FspExtPprAddr {
UINT8 Status;
UINT8 ErrorType;
UINT8 Socket;
UINT8 MemoryController;
UINT8 Channel;
UINT8 Dimm;
UINT8 Bank;
UINT32 Row;
UINT8 Rank;
} FSP_EXT_PPR_ADDR;
typedef struct FspExtPprDdrInfo {
UINT8 Count;
FSP_EXT_PPR_ADDR PprAddresses[FSP_MAX_PPR_ADDR_ENTRIES_DDR];
} FSP_EXT_DDR_PPR_INFO;
typedef struct FspExtMemoryPprData {
FSP_EXT_DDR_PPR_INFO DdrPprInfo;
} FSP_EXT_MEMORY_PPR_DATA;
typedef struct FspExtMemoryPprHob {
FSP_EXT_HEADER Header;
FSP_EXT_MEMORY_PPR_DATA Data;
} FSP_EXT_MEMORY_PPR_HOB;
#pragma pack()
#endif // _FSP_EXT_MEMORY_PPR_HOB_H_

161
src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspExtSystemMemoryMapHob.h Normal file
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@ -0,0 +1,161 @@
/** @file
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _FSP_EXT_SYSTEM_MEMORY_MAP_HOB_H_
#define _FSP_EXT_SYSTEM_MEMORY_MAP_HOB_H_
#include "FspGlobals.h"
#define FSP_EXT_SYSTEM_MEMORY_MAP_HOB_GUID { 0xDF310DE8, 0x579F, 0x419C, { 0xB6, 0xAB, 0x4D, 0x4B, 0xE7, 0xCA, 0xB0, 0x83 } }
#pragma pack(1)
typedef struct FspDimmDevice {
UINT8 Present;
BOOLEAN Enabled;
UINT8 DramIoWidth; // Actual DRAM IO Width (4, 8, 16)
UINT8 NumRanks; // Number of ranks on dimm
UINT8 NumPackageRanks; // Number of Package ranks on dimm
// For DDR5 NumRanks and NumPackageRanks same
// For MCR NumRanks and NumPackageRanks may differ
UINT8 ActKeyByte2; // Actual module type reported by SPD
UINT16 DimmSize;
UINT16 VendorID;
UINT16 DeviceID;
UINT16 RevisionID;
UINT8 SerialNumber[FSP_DIMM_MAX_SERIALNUMBER_LEN]; // Serial Number
UINT8 PartNumber[FSP_DIMM_MAX_PARTNUMBER_LEN]; // Part Number
UINT16 SubsystemVendorID;
UINT16 SubsystemDeviceID;
UINT16 SubsystemRevisionID;
UINT16 FisVersion; // Firmware Interface Specification version
INT32 CommonTck;
UINT16 SpdRegVen; // Register Vendor ID in SPD
UINT8 DataWidth;
} FSP_EXT_DIMM_DEVICE;
typedef struct FspExtMemoryDimmDeviceInfo {
UINT8 Count;
FSP_EXT_DIMM_DEVICE Dimms[FSP_MAX_DIMM];
} FSP_EXT_DIMM_DEVICE_INFO;
typedef struct FspMemoryChannelDevice {
UINT8 Enabled; // 0 = channel disabled, 1 = channel enabled
UINT8 Features; // Bit mask of features to enable or disable
UINT8 MaxDimm; // Number of DIMM
UINT8 ChFailed;
UINT8 NgnChFailed;
UINT8 Is4BitEccDimmPresent; // 4-bit Ecc dimm present indicator
UINT8 DdrPopulationMap; // Bitmap to indicate location of DDR DIMMs within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
UINT8 PmemPopulationMap; // Bitmap to indicate location of PMem modules within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
FSP_EXT_DIMM_DEVICE_INFO DimmInfo;
} FSP_EXT_MEMORY_CHANNEL_DEVICE;
typedef struct FspMemoryController {
UINT8 ImcEnabled;
UINT32 MemSize;
} FSP_EXT_MEMORY_CONTROLLER;
typedef struct FspExtMemoryChannelDeviceInfo {
UINT8 Count;
FSP_EXT_MEMORY_CHANNEL_DEVICE Devices[FSP_MAX_CH];
} FSP_EXT_MEMORY_CHANNEL_DEVICE_INFO;
typedef struct FspExtMemoryControllerInfo {
UINT8 Count;
UINT8 NumChPerMC;
FSP_EXT_MEMORY_CONTROLLER MemControllers[FSP_MAX_IMC];
} FSP_EXT_MEMORY_CONTROLLER_INFO;
typedef struct FspMemoryMapSocket {
UINT8 SocketEnabled;
UINT32 IioStackBitmap;
UINT32 SktTotMemMapSPA; // Total memory mapped to SPA
FSP_EXT_MEMORY_CONTROLLER_INFO MemoryControllerInfo;
FSP_EXT_MEMORY_CHANNEL_DEVICE_INFO MemoryChannelDeviceInfo;
} FSP_EXT_MEMORY_MAP_SOCKET;
typedef struct FspExtMemMapSocketInfo {
UINT8 Count;
FSP_EXT_MEMORY_MAP_SOCKET Sockets[FSP_MAX_SOCKET];
} FSP_EXT_MEMORY_MAP_SOCKET_INFO;
typedef struct FspMemoryMapElement {
UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
UINT8 NodeId; // Node ID of the HA Owning the memory
UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA
UINT8 ClusterId; // Logical cluster Id of SNC cluster - only 0 in UMA clustering and all2all
UINT32 BaseAddress; // Base Address of the element in 64MB chunks
UINT32 ElementSize; // Size of this memory element in 64MB chunks
} FSP_EXT_MEMORY_MAP_ELEMENT;
typedef struct FspExtMemMapElementInfo {
UINT8 Count;
FSP_EXT_MEMORY_MAP_ELEMENT Elements[FSP_MAX_MEMORY_MAP_ELEMENTS];
} FSP_EXT_MEMORY_MAP_ELEMENT_INFO;
typedef struct FspExtRasInfo {
UINT8 SystemRasType;
UINT8 RasModesEnabled; // RAS modes that are enabled
UINT16 ExRasModesEnabled; // Extended RAS modes that are enabled
} FSP_EXT_RAS_INFO;
typedef struct FspExtMemoryConfigurationInfo {
UINT32 LowMemBase; // Mem base in 64MB units for below 4GB mem.
UINT32 LowMemSize; // Mem size in 64MB units for below 4GB mem.
UINT32 HighMemBase; // Mem base in 64MB units for above 4GB mem.
UINT32 HighMemSize; // Mem size in 64MB units for above 4GB mem.
UINT32 MmiohBase; // MMIOH base in 64MB granularity
UINT32 MemSize; // Total physical memory size
UINT16 MemFreq;
UINT8 MemMode; // 0 - Independent, 1 - Lockstep
UINT8 VolMemMode; // 0 - 1LM, 1 - 2LM
UINT16 DramType;
UINT8 DdrVoltage; // Mem Frequency
UINT8 ErrorCorrectionType;
} FSP_EXT_MEMORY_CONFIGURATION_INFO;
typedef struct FspExtSystemMemoryMapData {
FSP_EXT_MEMORY_CONFIGURATION_INFO MemoryConfigurationInfo;
FSP_EXT_RAS_INFO RasInfo;
FSP_EXT_MEMORY_MAP_ELEMENT_INFO MemoryMapElementInfo;
FSP_EXT_MEMORY_MAP_SOCKET_INFO MemoryMapSocketInfo;
} FSP_EXT_SYSTEM_MEMORY_MAP_DATA;
typedef struct FspExtSystemMemoryMapDataHob{
FSP_EXT_HEADER Header;
FSP_EXT_SYSTEM_MEMORY_MAP_DATA Data;
} FSP_EXT_SYSTEM_MEMORY_MAP_HOB;
#pragma pack()
#endif // _FSP_EXT_SYSTEM_MEMORY_MAP_HOB_H_

61
src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspGlobals.h Normal file
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@ -0,0 +1,61 @@
/** @file
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _FSP_EXT_GLOBALS_
#define _FSP_EXT_GLOBALS_
#define FSP_MAX_SOCKET MAX_SOCKET
#define FSP_MAX_IMC MAX_IMC
#define FSP_MAX_MC_CH MAX_MC_CH
#define FSP_MAX_DIMM MAX_DIMM
#define FSP_DIMM_MAX_SERIALNUMBER_LEN NGN_MAX_SERIALNUMBER_STRLEN
#define FSP_DIMM_MAX_PARTNUMBER_LEN NGN_MAX_PARTNUMBER_STRLEN
#define FSP_MAX_CH ((FSP_MAX_IMC)*(FSP_MAX_MC_CH))
#define FSP_MAX_MEMORY_MAP_ELEMENTS 150
#define MEM_64MB_TO_BYTES(Size64M) ((UINT64)(Size64M) << 26)
#define MEM_64MB_TO_KBYTES(Size64M) ((UINT64)(Size64M) << 16)
#define MEM_64MB_TO_MBYTES(Size64M) ((UINT64)(Size64M) << 6)
#define MEM_64MB_TO_GBYTES(Size64M) ((Size64M) >> 4)
#define MEM_BYTES_TO_64MB(SizeB) ((SizeB) >> 26)
#define MEM_KBYTES_TO_64MB(SizeKB) ((SizeKB) >> 16)
#define MEM_MBYTES_TO_64MB(SizeMB) ((SizeMB) >> 6)
#define FSP_MAX_PPR_ADDR_ENTRIES_DDR MAX_PPR_ADDR_ENTRIES_DDR
typedef struct FspExtHeader {
UINT64 Magic;
UINT32 DataLength;
UINT32 CheckSum;
} FSP_EXT_HEADER;
#endif // _FSP_EXT_GLOBALS_

8
src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspUpd.h
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@ -1,6 +1,6 @@
/** @file
Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -37,11 +37,11 @@ are permitted provided that the following conditions are met:
#pragma pack(1)
#define FSPT_UPD_SIGNATURE 0x545F445055525053 /* 'SPRUPD_T' */
#define FSPT_UPD_SIGNATURE 0x545F445055524E47 /* 'GNRUPD_T' */
#define FSPM_UPD_SIGNATURE 0x4D5F445055525053 /* 'SPRUPD_M' */
#define FSPM_UPD_SIGNATURE 0x4D5F445055524E47 /* 'GNRUPD_M' */
#define FSPS_UPD_SIGNATURE 0x535F445055525053 /* 'SPRUPD_S' */
#define FSPS_UPD_SIGNATURE 0x535F445055524E47 /* 'GNRUPD_S' */
#define FSPI_UPD_SIGNATURE 0x495F445055524E47 /* 'GNRUPD_I' */

231
src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspiUpd.h
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@ -1,6 +1,6 @@
/** @file
Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -35,12 +35,26 @@ are permitted provided that the following conditions are met:
#include <FspUpd.h>
#define FSP_RAS_ACPI_HOB_GUID { 0x826785ee, 0xa8e0, 0x4d8f, { 0x82, 0x6f, 0x54, 0x29, 0x2c, 0xe7, 0x6f, 0xe6 } };
#pragma pack(1)
typedef struct {
/** RAS Log Level.
RAS Log setup options.
0:None, 1:MIN (BASIC_FLOW), 2:MID (BASIC_FLOW, FUNC_FLOW), 3:MAX (BASIC_FLOW, FUNC_FLOW, REG)
**/
UINT8 RasLogLevel;
/** WHEA FV Base Address
The physical memory-mapped base address of the WHEA (FV).
**/
UINT64 WheaFvBase;
/** WHEA FV Base Size
The size of the WHEA FV region in bytes
**/
UINT64 WheaFvBaseSize;
/** WHEA Support
Enable/Disable WHEA support.
0:Disable, 1:Enable
@ -69,15 +83,216 @@ typedef struct {
**/
UINT8 PcieErrInjActionTable;
/** SGX Memory Error Injection Support
Enable/Disable Error Injection Support in SGX Memory.
0:6dB, 1:3.5dB
**/
UINT8 SgxErrorInjEn;
/** Os Native AER Support
Select FFM or OS native for AER error handling. If select OS native, BIOS also initialize
FFM first until handshake, which depends on OS capability in FSP.
0:Disable, 1:Enable
**/
UINT8 OsNativeAerSupport;
/** IIO MCA Support.
Enable/Disable IIO MCA Support.
0:Disable, 1:Enable
**/
UINT8 IoMcaEn;
/** System Errors
System Error Enable/Disable setup options.
0:Disabled, 1:Enabled
**/
UINT8 SystemErrorEn;
/** CPU CrashLog Feature
The feature helps collecting crash data from OOBMSM SSRAM
0:Disabled, 1:Enabled,2:Auto
**/
UINT8 CpuCrashLogFeature;
/** MCERR Trigger CrashLog Disable
The feature helps to disable MCERR to trigger crash log
0:No, 1:Yes
**/
UINT8 McerrTriggerDisable;
/** Smbus Error Recovery
Enable or Disable(Default) Smbus Error Recovery
0:Disabled, 1:SMI, 2:Error Pin
**/
UINT8 SmbusErrorRecovery;
/** EMCA Error Support
Enable/Disable EMCA Error support
0:Disable, 1:Enable
**/
UINT8 EmcaEn;
/** EMCA Logging Support
Enable/Disable EMCA Logging
0:Disable, 1:Enable
**/
UINT8 ElogEn;
/** LMCE Support
Enable/Disable Local MCE firmware support
0:Disable, 1:Enable
**/
UINT8 LmceEn;
/** EMCA MCE-SMI Enable
Enable/Disable EMCA Uncorrected SMI for gen2
0:Disable, 2:EMCA gen2 MSMI
**/
UINT8 EmcaMsmiEn;
/** EMCA CMCI-SMI Morphing
Enable/Disable EMCA CSMI
0:Disable, 2:EMCA gen2 CSMI
**/
UINT8 EmcaCsmiEn;
/** EMCA CMCI-SMI Threshold
Set the threshold of CSMI
**/
UINT16 EmcaCsmiThreshold;
/** CSMI Dynamic Disable
Enable/Disable CSMI when error threshold reached
0:Disable, 1:Enable
**/
UINT8 CsmiDynamicDisable;
/** Ignore OS ELOG Opt-in
Enable/Disable Ignore OS ELOG Opt-in and log
0:Disable, 1:Enable
**/
UINT8 ElogIgnOptin;
/** Corrected Error eLog
Enable/Disable Corrected Error eLog
0:Disable, 1:Enable
**/
UINT8 ElogCorrErrEn;
/** Memory Error eLog
Enable/Disable Memory Error eLog
0:Disable, 1:Enable
**/
UINT8 ElogMemErrEn;
/** Processor Error eLog
Enable/Disable Processor Error eLog
0:Disable, 1:Enable
**/
UINT8 ElogProcErrEn;
/** Ubox Error Mask
Mask SMI generation for Ubox Error
0:Disable, 1:Enable
**/
UINT8 UboxErrorMask;
/** Corrected Error Cloaking
Mask Corrected errors from OS/SW visibility only when EMCA is enabled
0:Disable, 1:Enable
**/
UINT8 CeCloakingEn;
/** Memory Corrected Error
Enable/Disable Memory Corrected Error
0:Disable, 1:Enable, 2:Auto
**/
UINT8 CorrMemErrEn;
/** Mca Bank Error Injection Support
Enable/Disable Mca Bank Error Injection Support.
$EN_DIS
**/
UINT8 McaBankErrInjEn;
/** Whea Log Memory Error
Enable/Disable Whea Log Memory Error
0:Disabled, 1:Enabled
**/
UINT8 WheaLogMemoryEn;
/** Whea Log Processor Error
Enable/Disable Whea Log Processor Error
0:Disabled, 1:Enabled
**/
UINT8 WheaLogProcEn;
/** Whea Log PCI Error
Enable/Disable Whea Log PCI Error
0:Disabled, 1:Enabled
**/
UINT8 WheaLogPciEn;
/** Viral Status
Enable/Disable Viral
$EN_DIS
**/
UINT8 ViralEn;
/** System Memory Poison
Enable/Disable System Memory Poison.
$EN_DIS
**/
UINT8 DfxPoisonEn;
/** Clear Shadow Registers
Enable/Disable clearing shadow registers.
$EN_DIS
**/
UINT8 ClearShadowRegisters;
/** PCIE Corrected Error Threshold Counter
Enable/Disable PCIE Corrected Error Counter.
$EN_DIS
**/
UINT8 PcieCorErrCntr;
/** PCIE Corrected Error Threshold Counter
0x00000001 - 0x0000ffff.
**/
UINT32 PcieCorErrThres;
/** IIO eDPC Support
Enable/Disable IIO eDPC Support.
0:Disabled, 1:On Fatal Error, 2:On Fatal and Non-Fatal Errors
**/
UINT8 EdpcEn;
/** IIO eDPC Interrupt
Enable/Disable IIO eDPC Interrupt.
0:Disabled, 1:Enabled
**/
UINT8 EdpcInterrupt;
/** IpmiIoBase
Address of IpmiIoBase
**/
UINT16 IpmiIoBase;
/** Trigger SW Error Threshold
Enable or Disable Sparing trigger SW Error Match Threshold.
0:Disable, 1:Enable
**/
UINT8 TriggerSWErrThEn;
/** SW Per Row Threshold
SW Per Row Correctable Error Threshold (1 - 0x7FFF) used for row level error.
**/
UINT16 SparePerRowTh;
/** N/A
**/
UINT8 ReservedSiliconInitUpd[16];
UINT8 ReservedSmmInitUpd[16];
} FSPI_CONFIG;
@ -87,11 +302,15 @@ typedef struct {
/** N/A
**/
FSP_UPD_HEADER FspUpdHeader;
/** N/A
**/
FSPI_ARCH_UPD FspiArchUpd;
/** N/A
**/
FSPI_CONFIG FspiConfig;
/** N/A
**/
UINT16 UpdTerminator;

2571
src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspmUpd.h
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333
src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FspsUpd.h
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@ -1,6 +1,6 @@
/** @file
Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -30,261 +30,224 @@ are permitted provided that the following conditions are met:
**/
#ifndef __FSPSUPD_H__
#define __FSPSUPD_H__
#ifndef __FSPS_UPD_H__
#define __FSPS_UPD_H__
#include <FspUpd.h>
#pragma pack(1)
/** FSP-S Configuration
**/
typedef struct {
/** Offset 0x0020 - Processor VmxEnable Function
Processor VmxEnable Function - <b>1: Enable(Default)</b>, 0: Disable Processor VmxEnable Function.
0: Disable, 1: Enable
/** PCIe Controller 0
Enable / Disable PCI Express controller 0
$EN_DIS
**/
UINT8 VmxEnable;
UINT8 EnablePcie0;
/** Offset 0x0021 - Processor TurboMode Function
Processor TurboMode Function - <b>1: Enable(Default)</b>, 0: Disable Processor TurboMode Function.
0: Disable, 1: Enable
/** PCIe Controller 1
Enable / Disable PCI Express controller 1
$EN_DIS
**/
UINT8 TurboMode;
UINT8 EnablePcie1;
/** Offset 0x0022 - Processor Safer Mode Extensions Function
Processor Safer Mode Extensions Function - <b>0: Disable(Default)</b>, 1: Enable
Processor Safer Mode Extensions Function.
0: Disable, 1: Enable
/** Embedded Multi-Media Controller (eMMC)
Enable / Disable Embedded Multi-Media controller
$EN_DIS
**/
UINT8 ProcessorSmxEnable;
UINT8 EnableEmmc;
/** Offset 0x0023 - SstCp
SstCp - 1: Enable, <b>0: Disable SstCp(Default)</b>.
0: Disable, 1: Enable
/** LAN Controllers
Enable / Disable LAN controllers, refer to FSP Integration Guide for details.
0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only
**/
UINT8 SstCpSetting;
UINT8 EnableGbE;
/** Offset 0x0024 - SstCp Capable Status
SST-CP Capable Status in system - <b>0: Disable(Default)</b>, 1: Enable.
0: Disable, 1: Enable
/** PCIe Root Port 0 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 SstCpCapableSystem;
UINT8 PcieRootPort0DeEmphasis;
/** Offset 0x0025
/** PCIe Root Port 1 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 UnusedUpdSpace0[1];
UINT8 PcieRootPort1DeEmphasis;
/** Offset 0x0026 - PCH Protect Range Limit
/** PCIe Root Port 2 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 PcieRootPort2DeEmphasis;
/** PCIe Root Port 3 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 PcieRootPort3DeEmphasis;
/** PCIe Root Port 4 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 PcieRootPort4DeEmphasis;
/** PCIe Root Port 5 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 PcieRootPort5DeEmphasis;
/** PCIe Root Port 6 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 PcieRootPort6DeEmphasis;
/** PCIe Root Port 7 DeEmphasis
Desired DeEmphasis level for PCIE root port
0:6dB, 1:3.5dB
**/
UINT8 PcieRootPort7DeEmphasis;
/** eMMC DLL Configuration Data
Pointer to eMMC DLL Configuration Data
**/
UINT32 EMMCDLLConfigPtr;
/** PCH Protect Range Limit
Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
limit comparison.
**/
UINT16 PchProtectedRangeLimit[5];
/** Offset 0x0030 - PCH Protect Range Base
/** PCH Protect Range Base
Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
**/
UINT16 PchProtectedRangeBase[5];
/** Offset 0x003A - PchAdrEn
PchAdr - <b>0: PLATFORM POR(Default)</b>, 1: FORCE ENABLE, 2:FORCE DISABLE.
0: PLATFORM POR, 1: FORCE ENABLE, 2: FORCE DISABLE
/** PchAdrEn
PchAdr 0:PLATFORM POR, <b>1:FORCE ENABLE(Default)</b>, 2:FORCE DISABLE
0:PLATFORM POR, 1:FORCE ENABLE, 2:FORCE DISABLE
**/
UINT8 PchAdrEn;
/** Enable Timed GPIO0
Enable/Disable Timed GPIO0. When disabled, it disables cross time stamp time-synchronization
as extension of Hammock Harbor time synchronization
$EN_DIS
**/
UINT8 EnableTimedGpio0;
/** Enable Timed GPIO1
Enable/Disable Timed GPIO0. When disabled, it disables cross time stamp time-synchronization
as extension of Hammock Harbor time synchronization
$EN_DIS
**/
UINT8 EnableTimedGpio1;
/** FSP smm init enable
Enable / Disable FSP smm init
$EN_DIS
**/
UINT8 FspSmmInitEn;
/** Offset 0x003B - EnableTme
EnableTme - <b>0: Disabled(Default)</b>, 1: Enabled, 2:Software Controlled.
0: Disabled, 1: Enabled, 2:Software Controlled
/** C2C3TT
Default = 0, means [AUTO]. C2 to C3 Transition Timer, PPDN_INIT = C2C3TT CSR Bit[11:0]
0: Default, Bit[11:0] : C2 to C3 Transition Timer
**/
UINT8 EnableTme;
UINT8 CpuPmC2c3tt;
/** Offset 0x003C - EnableTmeBypass
EnableTmeBypass - <b>0: Disabled(Default)</b>, 1: Enabled.
0: Disabled, 1: Enabled
**/
UINT8 EnableTmeBypass;
/** Offset 0x003D - SgxFactoryReset
SgxFactoryReset - <b>0: Disabled(Default)</b>, 1: Enabled.
0: Disabled, 1: Enabled
**/
UINT8 SgxFactoryReset;
/** Offset 0x003E - EnableSgx
EnableSgx - <b>0: Disabled(Default)</b>, 1: Enabled.
0: Disabled, 1: Enabled
**/
UINT8 EnableSgx;
/** Offset 0x003F - SgxPackageInfoInBandAccess
SgxPackageInfoInBandAccess - <b>0: Disabled(Default)</b>, 1: Enabled.
0: Disabled, 1: Enabled
**/
UINT8 SgxPackageInfoInBandAccess;
/** Offset 0x0040 - SgxQoS
SgxQoS - 0: Disabled, <b>1: Enabled(Default)</b>.
0: Disabled, 1: Enabled
**/
UINT8 SgxQoS;
/** Offset 0x0041 - EpochUpdate
EpochUpdate - 1: Change to New Random Owner EPOCHs, <b>2: Manual User Defined Owner
EPOCHs(Default)</b>.
1: Change to New Random Owner EPOCHs, 2: Manual User Defined Owner EPOCHs
**/
UINT8 EpochUpdate;
/** Offset 0x0042 - SgxLeWr
SgxLeWr - <b>0: Disabled(Default)</b>, 1: Enabled.
0: Disabled, 1: Enabled
**/
UINT8 SgxLeWr;
/** Offset 0x0043 - SgxDebugMode
SgxDebugMode - <b>0: Disabled(Default)</b>, 1: Enabled.
0: Disabled, 1: Enabled
**/
UINT8 SgxDebugMode;
/** Offset 0x0044 - SgxAutoRegistrationAgent
SgxAutoRegistrationAgent - <b>0: Disabled(Default)</b>, 1: Enabled.
0: Disabled, 1: Enabled
**/
UINT8 SgxAutoRegistrationAgent;
/** Offset 0x0045 - DfxSgxRegistrationServerSelect
DfxSgxRegistrationServerSelect - <b>0: SBX(Default)</b>, 1: PRX, 2:AUTO, 3:LIV,
4:SW Defined Server.
0: SBX, 1: PRX, 2:AUTO, 3:LIV, 4:SW Defined Server
**/
UINT8 DfxSgxRegistrationServerSelect;
/** Offset 0x0046 - Processor Enable Monitor MWAIT
Processor Enable Monitor MWAIT - <b>1: Enable(Default)</b>, 0: Disable Processor
Monitor MWAIT.
0: Disabled, 1: Enabled
/** Processor Enable Monitor MWAIT
Enable(Default) or Disable Processor Monitor MWAIT
$EN_DIS
**/
UINT8 CpuPmMonitorMWait;
/** Offset 0x0047 - Processor C6
Processor C6 - <b>1: Enable(Default)</b>, 0: Disable Processor C6 (ACPI C3) report to OS.
0: Disabled, 1: Enabled
/** Processor TurboMode Function
Enable(Default) or Disable Processor TurboMode Function
$EN_DIS
**/
UINT8 CpuPmC6Enable;
UINT8 CpuPmTurboMode;
/** Offset 0x0048 - Hardware P-States
Hardware P-States - 0: Disable: Hardware chooses a P-state based on OS Request
(Legacy P-States), <b>1:Native Mode:Hardware chooses a P-state based on OS guidance(Default)</b>,
2:Out of Band Mode:Hardware autonomously chooses a P-state (no OS guidance), 3:Native
Mode with No Legacy Support.
0: Disable, 1: Native Mode, 2: Out of Band Mode, 3: Native Mode with No Legacy Support
/** Hardware P-States
Disable: Hardware chooses a P-state based on OS Request (Legacy P-States)\n
Native Mode:Hardware chooses a P-state based on OS guidance\n
Out of Band Mode:Hardware autonomously chooses a P-state (no OS guidance)
0:Disable, 1:Native Mode (Default), 2:Out of Band Mode, 3:Native Mode with No Legacy Support
**/
UINT8 CpuPmProcessorHWPMEnable;
/** Offset 0x0049 - Power Performance Tuning
Power Performance Tuning - <b>0: OS Controls EPB (Default)</b>, 1: BIOS Controls
EPB, 2: PECI Controls EPB.
/** HardwarePM Interrupt
Enable or Disable (Default) Hardware PM Interrupt
$EN_DIS
**/
UINT8 CpuPmProcessorHWPMInterrupt;
/** EPP Profile
Choose an HWPM Profile, 0: Performance, 128: Balanced Performance, 192: Balanced
Power, 255: Power
0: Performance, 128: Balanced Performance, 192: Balanced Power, 255: Power
**/
UINT8 CpuPmProcessorEPPProfile;
/** Boot Performance Mode
Select the performance state that the BIOS will set before OS hand off, 0: Max Performance,
1: Max Efficiency
0: Max Performance (Default), 1: Max Efficiency
**/
UINT8 CpuPmBootPstate;
/** Power Performance Tuning
Power Performance Tuning <b>0: OS Controls EPB (Default)</b>, 1: BIOS Controls EPB,
2: PECI Controls EPB
0: OS Controls EPB, 1: BIOS Controls EPB, 2: PECI Controls EPB
**/
UINT8 CpuPmPwrPerfTuning;
/** Offset 0x004A - Configure SST-BF
Allow (Default)/Disallow BIOS to configure SST-BF High Priority Cores so that SW
does not have to configure - 0:Disable, <b>1:Enable(Default)</b>.
0:Disable, 1:Enable
/** Enable or Disable Thermal Monitor
Enable or Disable Thermal Monitor, 0: Disable, 1: Enable
$EN_DIS
**/
UINT8 CpuPmProcessorConfigurePbf;
UINT8 ThermalMonitor;
/** Offset 0x004B - CF9 Global Reset Promotion
CF9 Global Reset Promotion - 1: Enable promoting CF9 reset to global, <b>0: Disable
promoting CF9 reset to global(Default)</b>.
0: Disabled, 1: Enabled
/** FSPS Upd settings support
: FSPS Upd settings support
$EN_DIS
**/
UINT8 MeGrPromotionEnabled;
UINT8 FspsUpdSupport;
/** Offset 0x004C - Global Reset Lock
Global Reset Lock - <b>1: Enable locking the joint ME and host reset capability(Default)</b>,
0: Disable locking the joint ME and host reset capability.
0: Disabled, 1: Enabled
/** N/A
Pointer to node list which is used to initizalize security variables - CCT_VS_METADATA_NODE
**/
UINT8 MeGrLockEnabled;
EFI_PHYSICAL_ADDRESS SecurityCctVarStorageMetadataNodePtr;
/** Offset 0x004D - Delayed Authentication Mode
Enable or disable Delayed Authentication Mode - <b>0: Disable(Default)</b>, 1: Enable.
0:Disable, 1:Enable
**/
UINT8 DelayedAuthenticationMode;
/** Offset 0x004E - Delayed Authentication Mode Override
Enable or disable Delayed Authentication Mode Override - <b>0: Disable(Default)</b>,
1: Enable.
0:Disable, 1:Enable
**/
UINT8 DelayedAuthenticationModeOverride;
/** Offset 0x004F - Core Bios Done Message
Enable or disable Core Bios Done message sent to ME - 0: Disable, <b>1: Enable(Default)</b>.
0:Disable, 1:Enable
**/
UINT8 CoreBiosDoneEnabled;
/** Offset 0x0050 - End Of Post Message
Enable or disable sending END_OF_POST message to ME - 0: Disable, 1: Send in PEI,
<b>2: Send in DXE(Default)</b>.
0:Disable, 1:Send in PEI, 2:Send in DXE
**/
UINT8 EndOfPostMessage;
/** Offset 0x0051 - HMRFPO_LOCK Message
Enable or disable sending HMRFPO_LOCK message to ME - 0: Disable, <b>1: Enable(Default)</b>.
0:Disable, 1:Enable
**/
UINT8 MeHmrfpoLockEnabled;
/** Offset 0x0052 - HMRFPO_ENABLE Message
Enable or disable sending HMRFPO_ENABLE message to ME - <b>0: Disable(Default)</b>,
1: Enable.
0:Disable, 1:Enable
**/
UINT8 MeHmrfpoEnableEnabled;
/** Offset 0x0053
**/
UINT8 UnusedUpdSpace1[1];
/** Offset 0x0054
/** N/A
**/
UINT8 ReservedSiliconInitUpd[16];
} FSPS_CONFIG;
/** Fsp S UPD Configuration
**/
typedef struct {
/** Offset 0x0000
/** N/A
**/
FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0020
/** N/A
**/
FSPS_ARCH2_UPD FspsArchUpd;
/** N/A
**/
FSPS_CONFIG FspsConfig;
/** Offset 0x0064
**/
UINT8 UnusedUpdSpace2[2];
/** Offset 0x0066
/** N/A
**/
UINT16 UpdTerminator;
} FSPS_UPD;
#pragma pack()

26
src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/FsptUpd.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -38,19 +38,19 @@ are permitted provided that the following conditions are met:
#pragma pack(1)
typedef struct {
/** N/A
**/
UINT64 MicrocodeRegionBase;
/** N/A
**/
UINT64 MicrocodeRegionLength;
/** N/A
**/
UINT64 CodeRegionBase;
/** N/A
**/
UINT64 CodeRegionLength;
@ -60,13 +60,11 @@ typedef struct {
typedef struct {
/** Offset 0x0040 - Disable Port80 output in FSP-T
Select Port80 Control in FSP-T - 0:VPD-Style, <b>1:Enable Port80 Output (Default)</b>,
2:Disable Port80 Output, refer to FSP Integration Guide for details.
/** Disable Port80 output in FSP-T
0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output
**/
UINT8 FsptPort80RouteDisable;
/** N/A
**/
UINT8 ReservedTempRamInitUpd[31];
@ -75,23 +73,23 @@ typedef struct {
typedef struct {
/** N/A
**/
FSP_UPD_HEADER FspUpdHeader;
/** N/A
**/
FSPT_ARCH2_UPD FsptArchUpd;
/** N/A
**/
FSPT_CORE_UPD FsptCoreUpd;
/** N/A
**/
FSPT_CONFIG FsptConfig;
/** N/A
**/
UINT16 UpdTerminator;

340
src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioPcieConfigUpd.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -26,190 +26,45 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _IIO_PCIE_CONFIG_UPD_H_
#define _IIO_PCIE_CONFIG_UPD_H_
#ifndef MAX_SOCKET
#define MAX_SOCKET 4
#define MAX_SOCKET 2
#endif
#ifndef MAX_LOGIC_IIO_STACK
#define MAX_LOGIC_IIO_STACK 14
#endif
#ifndef MAX_IIO_PORTS_PER_SOCKET
#define MAX_IIO_PORTS_PER_SOCKET 57
#endif
#ifndef MAX_IOU_PER_SOCKET
#define MAX_IOU_PER_SOCKET 7
#define MAX_LOGIC_IIO_STACK 18
#endif
/**
* Maximum number of IIO ports per IIO stack.
*/
#ifndef MAX_IIO_PORTS_PER_STACK
#define MAX_IIO_PORTS_PER_STACK 1
#define MAX_IIO_PORTS_PER_STACK 8
#endif
#define MAX_IIO_STACK 16
#define MAX_IIO_STACKS_PER_SOCKET MAX_IIO_STACK
#define MAX_IIO_PORTS_PER_SOCKET (MAX_IIO_STACKS_PER_SOCKET * MAX_IIO_PORTS_PER_STACK)
#define MAX_IIO_PCIE_PER_SOCKET 1
#if MAX_SOCKET <= 4
#define MAX_VMD_STACKS_PER_SOCKET 8 // Max number of stacks per socket supported by VMD
//
// 10 PCIe stacks (PE) and 3 IO accelerator (IOAT) possible in Rich 1 Socket.
// However, we share R1S image with 4 socket SP image, no separate build for R1S.
// So use R1S definitions for 4 socket SP and 4 PE, 1 IOAT entry are just not used, never present.
//
#define MAX_IIO_PCIE_PER_SOCKET 10
#else
#define MAX_IIO_PCIE_PER_SOCKET 6
#endif
#pragma pack(1)
typedef enum {
PE0 = 0,
PE1,
PE2,
PE3,
PE4,
PE5,
PEa,
PEb,
PEc,
PEd,
PE_MAX,
PE_ = 0xFF // temporary unknown value
} IIO_PACKAGE_PE;
typedef struct {
UINT8 Address; // SMBUS address of IO expander which provides NPEM
UINT8 Bank; // Port or bank on IoExpander which provides NPEM
UINT8 MuxAddress; // SMBUS address of MUX used to access NPEM
UINT8 MuxChannel; // Channel of the MUX used to access NPEM
} IIO_NPEM_CFG;
typedef struct {
UINT8 SLOTEIP[MAX_IIO_PORTS_PER_SOCKET]; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
UINT8 SLOTHPCAP[MAX_IIO_PORTS_PER_SOCKET]; // Slot Hot Plug capable - Slot Capabilities (D0-10 / F0 / R0xA4 / B6)
UINT8 SLOTHPSUP[MAX_IIO_PORTS_PER_SOCKET]; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
UINT8 SLOTPIP[MAX_IIO_PORTS_PER_SOCKET]; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
UINT8 SLOTAIP[MAX_IIO_PORTS_PER_SOCKET]; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
UINT8 SLOTMRLSP[MAX_IIO_PORTS_PER_SOCKET]; // MRL Sensor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B2)
UINT8 SLOTPCP[MAX_IIO_PORTS_PER_SOCKET]; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 /B1)
UINT8 SLOTABP[MAX_IIO_PORTS_PER_SOCKET]; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
UINT8 SLOTIMP[MAX_IIO_PORTS_PER_SOCKET];
UINT8 SLOTSPLS[MAX_IIO_PORTS_PER_SOCKET];
UINT8 SLOTSPLV[MAX_IIO_PORTS_PER_SOCKET];
UINT16 SLOTPSP[MAX_IIO_PORTS_PER_SOCKET];
BOOLEAN VppEnabled[MAX_IIO_PORTS_PER_SOCKET]; // 00 -- Disable, 01 -- Enable //no setup option defined- aj
UINT8 VppPort[MAX_IIO_PORTS_PER_SOCKET]; // 00 -- Port 0, 01 -- Port 1 //no setup option defined- aj
UINT8 VppAddress[MAX_IIO_PORTS_PER_SOCKET]; // 01-07 for SMBUS address of Vpp //no setup option defined- aj
UINT8 MuxAddress[MAX_IIO_PORTS_PER_SOCKET]; // SMBUS address of MUX //no setup option defined
UINT8 ChannelID[MAX_IIO_PORTS_PER_SOCKET]; // 00 -- channel 0, 01 -- channel 1 //no setup option defined
UINT8 PciePortEnable[MAX_IIO_PORTS_PER_SOCKET];
UINT8 PEXPHIDE[MAX_IIO_PORTS_PER_SOCKET]; // Hide any of the DMI or PCIE devices - SKT 0,1,2,3; Device 0-10 PRD
UINT8 HidePEXPMenu[MAX_IIO_PORTS_PER_SOCKET]; // to suppress /display the PCIe port menu
UINT8 PciePortOwnership[MAX_IIO_PORTS_PER_SOCKET];
UINT8 RetimerConnectCount[MAX_IIO_PORTS_PER_SOCKET];
UINT8 ConfigIOU[MAX_IOU_PER_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P1p2p3p4)
UINT8 PcieHotPlugOnPort[MAX_IIO_PORTS_PER_SOCKET]; // Manual override of hotplug for port
UINT8 VMDEnabled[MAX_VMD_STACKS_PER_SOCKET];
UINT8 VMDPortEnable[MAX_IIO_PORTS_PER_SOCKET];
UINT8 VMDHotPlugEnable[MAX_VMD_STACKS_PER_SOCKET];
UINT8 PcieMaxPayload[MAX_IIO_PORTS_PER_SOCKET];
UINT8 PciePortLinkSpeed[MAX_IIO_PORTS_PER_SOCKET]; // auto - 0(default); gen1 -1; gen2 -2; ... gen5 -5.
UINT8 DfxDnTxPresetGen3[MAX_IIO_PORTS_PER_SOCKET]; //auto - 0xFF(default); p0 - 0; p1 -1; ... p9 - 9.
UINT8 PcieGlobalAspm;
UINT8 PcieMaxReadRequestSize;
} UPD_IIO_PCIE_PORT_CONFIG;
typedef struct {
UINT8 Address;
UINT8 Port;
UINT8 MuxAddress;
UINT8 MuxChannel;
} IIO_VPP_CFG;
typedef struct {
UINT8 Eip : 1; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
UINT8 HotPlugSurprise : 1; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
UINT8 PowerInd : 1; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
UINT8 AttentionInd : 1; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
UINT8 PowerCtrl : 1; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B1)
UINT8 AttentionBtn : 1; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
UINT8 Reserved : 2;
} IIO_SLOT_CFG;
typedef struct {
IIO_VPP_CFG Vpp;
IIO_NPEM_CFG Npem;
IIO_SLOT_CFG Slot;
UINT8 VppEnabled :1;
UINT8 VppExpType :1;
UINT8 NpemSupported :1;
UINT8 SlotImplemented :1;
UINT8 Retimer1Present :1;
UINT8 Retimer2Present :1;
UINT8 CommonClock :1;
UINT8 SRIS :1;
UINT16 HotPlug : 1; // If hotplug is supported on slot connected to this port
UINT16 MrlSensorPresent : 1; // If MRL is present on slot connected to this port
UINT16 SlotPowerLimitScale : 2; // Slot Power Scale for slot connected to this port
UINT16 SlotPowerLimitValue : 12; // Slot Power Value for slot connected to this port
UINT16 PhysicalSlotNumber; // Slot number for slot connected to this port
} IIO_BOARD_SETTINGS_PER_PORT;
typedef struct {
struct {
UINT8 Segment; ///< Remember segment, if it changes reset everything
UINT8 StackPciBusPoolSize[MAX_LOGIC_IIO_STACK]; ///< Number of bus numbers needed for IIO stack
} Socket[MAX_SOCKET];
} SYSTEM_PCI_BUS_CONFIGURATION;
typedef struct {
UINT64 Base; ///< Base (starting) address of a range (I/O, 32 and 64-bit mmio regions)
UINT64 Limit; ///< Limit (last valid) address of a range
} PCIE_BASE_LIMIT;
typedef struct {
UINT32 MmioLSize;
UINT64 MmioHSize;
} CXL11_LIMITS;
typedef struct {
PCIE_BASE_LIMIT Io; ///< Base and limit of I/O range assigned to entity
PCIE_BASE_LIMIT LowMmio; ///< Base and limit of low MMIO region for entity
PCIE_BASE_LIMIT HighMmio; ///< Base and limit of high (64-bit) MMIO region for entity
} PCI_BASE_LIMITS;
typedef struct {
PCI_BASE_LIMITS SocketLimits; ///< Base and Limit of all PCIe resources for the socket
PCI_BASE_LIMITS StackLimits[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of all PCIe resources for each stack of the socket
CXL11_LIMITS CxlStackReq[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of CXL11 resources for each stack of the socket
} SOCKET_PCI_BASE_LIMITS;
typedef struct {
//
// Save basic system configuration parameters along with the resource map to detect a change.
// Remember low and high I/O memory range when saving recource configuration. It is used to verify
// whether system memory map changed. Remember also stacks configured when creating the map.
// If anything changed reset the system PCI resource configuration.
//
UINT64 MmioHBase;
UINT64 MmioHGranularity;
UINT32 MmioLBase;
UINT32 MmioLLimit;
UINT32 MmioLGranularity;
UINT16 IoBase;
UINT16 IoLimit;
UINT16 IoGranularity;
UINT32 StackPresentBitmap[MAX_SOCKET];
//
// Used by the PciHostBridge DXE driver, these variables don't need to be exposed through setup options
// The variables are used as a communication vehicle from the PciHostBridge DXE driver to an OEM hook
// which updates the KTI resource map.
//
SOCKET_PCI_BASE_LIMITS Socket[MAX_SOCKET]; ///< Base and limit of all PCIe resources for each socket
} SYSTEM_PCI_BASE_LIMITS;
#define MAX_IOU_PER_SOCKET MAX_IIO_PCIE_PER_SOCKET
#define IIO_BIFURCATE_xxxxxxxx 0xFE
#define IIO_BIFURCATE_x4x4x4x4 0x0
@ -238,11 +93,150 @@ typedef struct {
#define IIO_BIFURCATE_x2x2x4x2x2x2x2 0x17
#define IIO_BIFURCATE_x4x2x2x2x2x2x2 0x18
#define IIO_BIFURCATE_x2x2x2x2x2x2x2x2 0x19
#define IIO_BIFURCATE_xxxxxxx4 0x40
#define IIO_BIFURCATE_xxx2xxx2 0x41
#define IIO_BIFURCATE_x1x1xxx2 0x42
#define IIO_BIFURCATE_xxx2x1x1 0x43
#define IIO_BIFURCATE_x1x1x1x1 0x44
#define IIO_BIFURCATE_AUTO 0xFF
#define C1_UID 2
#define C2_UID 3
/**
* VTBAR - Virtualization Technology BAR region size and alignment.
*/
#define IIO_VTBAR_LSB 16 // 64 kB
#define IIO_VTBAR_SIZE (1 << IIO_VTBAR_LSB)
#pragma pack(1)
typedef enum {
PE0 = 0,
PE1,
PE2,
PE3,
PE4,
PE5,
PEa,
PEb,
PEc,
PEd,
PE_MAX,
PE_ = 0xFF // temporary unknown value
} IIO_PACKAGE_PE;
typedef struct {
struct {
UINT8 Segment; ///< Remember segment, if it changes reset everything
UINT8 StackPciBusPoolSize[MAX_LOGIC_IIO_STACK]; ///< Number of bus numbers needed for IIO stack
} Socket[MAX_SOCKET];
} SYSTEM_PCI_BUS_CONFIGURATION;
typedef struct {
UINT64 Base; ///< Base (starting) address of a range (I/O, 32 and 64-bit mmio regions)
UINT64 Limit; ///< Limit (last valid) address of a range
} PCIE_BASE_LIMIT;
typedef struct {
UINT32 MmioLSize;
UINT64 MmioHSize;
} CXL11_LIMITS;
typedef struct {
PCIE_BASE_LIMIT Io; ///< Base and limit of I/O range assigned to entity
PCIE_BASE_LIMIT LowMmio; ///< Base and limit of low MMIO region for entity
PCIE_BASE_LIMIT HighMmio; ///< Base and limit of high (64-bit) MMIO region for entity
} PCI_BASE_LIMITS;
typedef struct {
PCI_BASE_LIMITS StackLimits[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of all PCIe resources for each stack of the socket
CXL11_LIMITS CxlStackReq[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of CXL11 resources for each stack of the socket
} SOCKET_PCI_BASE_LIMITS;
typedef struct {
//
// Save basic system configuration parameters along with the resource map to detect a change.
// Remember low and high I/O memory range when saving recource configuration. It is used to verify
// whether system memory map changed. Remember also stacks configured when creating the map.
// If anything changed reset the system PCI resource configuration.
//
UINT64 MmioHBase;
UINT64 MmioHGranularity;
UINT32 MmioLBase;
UINT32 MmioLLimit;
UINT32 MmioLGranularity;
UINT16 IoBase;
UINT16 IoLimit;
UINT16 IoGranularity;
UINT32 StackPresentBitmap[MAX_SOCKET];
//
// Used by the PciHostBridge DXE driver, these variables don't need to be exposed through setup options
// The variables are used as a communication vehicle from the PciHostBridge DXE driver to an OEM hook
// which updates the KTI resource map.
//
SOCKET_PCI_BASE_LIMITS Socket[MAX_SOCKET]; ///< Base and limit of all PCIe resources for each socket
} SYSTEM_PCI_BASE_LIMITS;
typedef struct {
UINT8 Address; // SMBUS address of IO expander which provides VPP register
UINT8 Port; // Port or bank on IoExpander which provides VPP register
UINT8 MuxAddress; // SMBUS address of MUX used to access VPP
UINT8 MuxChannel; // Channel of the MUX used to access VPP
} IIO_VPP_CFG;
typedef struct {
UINT8 Address; // SMBUS address of IO expander which provides NPEM
UINT8 Bank; // Port or bank on IoExpander which provides NPEM
UINT8 MuxAddress; // SMBUS address of MUX used to access NPEM
UINT8 MuxChannel; // Channel of the MUX used to access NPEM
} IIO_NPEM_CFG;
typedef struct {
UINT8 Eip : 1; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
UINT8 HotPlugSurprise : 1; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
UINT8 PowerInd : 1; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
UINT8 AttentionInd : 1; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
UINT8 PowerCtrl : 1; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B1)
UINT8 AttentionBtn : 1; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
UINT8 Reserved : 2;
} IIO_SLOT_CFG;
typedef struct {
//
// Below is an excerpt from structure PCIE_PORT_ENTERPRISE_CONFIG
//
IIO_VPP_CFG Vpp;
IIO_NPEM_CFG Npem;
IIO_SLOT_CFG Slot;
UINT8 VppEnabled :1; // If VPP is supported on given port
UINT8 VppExpType :1; // IO Expander type used for VPP (see IIO_VPP_EXPANDER_TYPE for values definitions)
UINT8 NpemSupported :1; // If NPEM is supported on given port
//
// Below is an excerpt IIO_PCIE_PORT_CONFIG
//
UINT8 SlotImplemented :1;
UINT8 Retimer1Present :1;
UINT8 Retimer2Present :1;
UINT8 CommonClock :1;
UINT8 SRIS :1;
//
// Below is an excerpt from structure PCIE_PORT_COMMON_CONFIG
//
UINT16 HotPlug : 1; // If hotplug is supported on slot connected to this port
UINT16 MrlSensorPresent : 1; // If MRL is present on slot connected to this port
UINT16 SlotPowerLimitScale : 2; // Slot Power Scale for slot connected to this port
UINT16 SlotPowerLimitValue : 12; // Slot Power Value for slot connected to this port
UINT16 PhysicalSlotNumber; // Slot number for slot connected to this port
} IIO_BOARD_SETTINGS_PER_PORT;
typedef enum {
IioBifurcation_UNKNOWN = IIO_BIFURCATE_xxxxxxxx,
IioBifurcation_x4x4x4x4 = IIO_BIFURCATE_x4x4x4x4,
@ -271,6 +265,13 @@ typedef enum {
IioBifurcation_x2x2x4x2x2x2x2 = IIO_BIFURCATE_x2x2x4x2x2x2x2,
IioBifurcation_x4x2x2x2x2x2x2 = IIO_BIFURCATE_x4x2x2x2x2x2x2,
IioBifurcation_x2x2x2x2x2x2x2x2 = IIO_BIFURCATE_x2x2x2x2x2x2x2x2,
IioBifurcation_xxxxxxx4 = IIO_BIFURCATE_xxxxxxx4,
IioBifurcation_xxx2xxx2 = IIO_BIFURCATE_xxx2xxx2,
IioBifurcation_x1x1xxx2 = IIO_BIFURCATE_x1x1xxx2,
IioBifurcation_xxx2x1x1 = IIO_BIFURCATE_xxx2x1x1,
IioBifurcation_x1x1x1x1 = IIO_BIFURCATE_x1x1x1x1,
IioBifurcation_Auto = IIO_BIFURCATE_AUTO
} IIO_BIFURCATION;
@ -286,6 +287,9 @@ typedef struct {
IIO_BOARD_SETTINGS_PER_PE Pe[MAX_IIO_PCIE_PER_SOCKET];
} IIO_BOARD_SETTINGS_PER_SOCKET;
//
// HOB to store board settings data created based on UBA data
//
typedef struct {
IIO_BOARD_SETTINGS_PER_SOCKET Socket[MAX_SOCKET];
} IIO_BOARD_SETTINGS_HOB;

321
src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/IioUniversalDataHob.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -26,107 +26,70 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _IIO_UNIVERSAL_DATA_HOB_H_
#define _IIO_UNIVERSAL_DATA_HOB_H_
#define DINO_UID 0
#define PC_UID 1
#define UB_UID 4
#define CPM0_UID 5
#define HQM0_UID 6
#define IIO_UNIVERSAL_DATA_GUID { \
0xa1, 0x96, 0xf3, 0x7f, 0x7d, 0xee, 0x1e, 0x43, \
0xba, 0x53, 0x8f, 0xCa, 0x12, 0x7c, 0x44, 0xc0 \
}
#define IIO_UNIVERSAL_DATA_GUID { 0x7FF396A1, 0xEE7D, 0x431E, { 0xBA, 0x53, 0x8F, 0xCA, 0x12, 0x7C, 0x44, 0xC0 } }
#ifndef MAX_SOCKET
#define MAX_SOCKET 4
#define MAX_SOCKET 2
#endif
#if (MAX_SOCKET == 1)
#define MAX_FW_KTI_PORTS 4 // Maximum KTI PORTS to be used in structure definition.
#define MAX_FW_KTI_PORTS 4 // Maximum KTI PORTS to be used in structure definition.
#else
#define MAX_FW_KTI_PORTS 6 // Maximum KTI PORTS to be used in structure definition
#define MAX_FW_KTI_PORTS 6 // Maximum KTI PORTS to be used in structure definition
#endif //(MAX_SOCKET == 1)
#ifndef MAX_IMC
#define MAX_IMC 4 // Maximum memory controllers per socket
#endif
#ifndef MAX_MC_CH
#define MAX_MC_CH 2 // Max number of channels per MC (3 for EP)
#endif
#ifndef MAX_CH
#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
#endif
#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max number of memory nodes
#ifndef MAX_IIO_PORTS_PER_SOCKET
#define MAX_IIO_PORTS_PER_SOCKET 57
#endif
#ifndef MAX_IIO_PORTS_PER_STACK
#define MAX_IIO_PORTS_PER_STACK 8
#endif
#define MAX_LOGIC_IIO_STACK 18
#ifndef MAX_IIO_PCIROOTS_PER_STACK
#define MAX_IIO_PCIROOTS_PER_STACK 1
#define MAX_IIO_PCIROOTS_PER_STACK 3 // PCI roots that can be created for a stack
#endif
#ifndef MAX_IIO_STACK
#define MAX_IIO_STACK 12
#define MAX_COMPUTE_DIE 3
#define MAX_CHA_MAP (2 * MAX_COMPUTE_DIE) //for GNR & SRF only, each compute die has its own CAPID6 & CAPID7 (i.e. 2 CAPID registers)
#ifndef MAX_MESSAGE_LENGTH
#define MAX_MESSAGE_LENGTH 500
#endif
#define MAX_LOGIC_IIO_STACK 14
#define DINO_UID 0
#define PC_UID 1
#define UB_UID 4
#define CPM0_UID 5
#define HQM0_UID 6
#define MAX_COMPUTE_DIE 1
#define MAX_CHA_MAP (2 * MAX_COMPUTE_DIE) //for GNR & SRF only, each compute die has its own CAPID6 & CAPID7 (i.e. 2 CAPID registers)
#pragma pack(1)
typedef struct _UINT64_STRUCT {
UINT32 lo;
UINT32 hi;
} UINT64_STRUCT, *PUINT64_STRUCT;
#ifndef MMIO_BARS_ENUM
#define MMIO_BARS_ENUM
typedef enum {
TYPE_SCF_BAR = 0,
TYPE_PCU_BAR,
TYPE_MEM_BAR0,
TYPE_MEM_BAR1,
TYPE_MEM_BAR2,
TYPE_MEM_BAR3,
TYPE_MEM_BAR4,
TYPE_MEM_BAR5,
TYPE_MEM_BAR6,
TYPE_MEM_BAR7,
TYPE_SBREG_BAR,
TYPE_MAX_MMIO_BAR
} MMIO_BARS;
#endif
typedef struct {
UINT8 Device;
UINT8 Function;
} IIO_PORT_INFO;
typedef struct {
UINT8 Major;
UINT8 Minor;
UINT8 Revision;
UINT16 BuildNumber;
} RC_VERSION;
IioStack0 = 0,
IioStack1 = 1,
IioStack2 = 2,
IioStack3 = 3,
IioStack4 = 4,
IioStack5 = 5,
IioStack6 = 6,
IioStack7 = 7,
IioStack8 = 8,
IioStack9 = 9,
IioStack10 = 10,
IioStack11 = 11,
IioStack12 = 12,
IioStack13 = 13,
IioStack14 = 14,
IioStack15 = 15,
IioStack16 = 16,
IioStackUnknown = 0xFF
} IIO_STACK;
//--------------------------------------------------------------------------------------//
// Structure definitions for Universal Data Store (UDS)
//--------------------------------------------------------------------------------------//
#pragma pack(1)
typedef struct {
UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation)
UINT8 PeerSocId; // Socket ID
@ -136,52 +99,16 @@ typedef struct {
typedef struct {
UINT8 Valid;
UINT32 MmioBar[TYPE_MAX_MMIO_BAR];
UINT8 PcieSegment;
UINT64_STRUCT SegMmcfgBase;
UINT64 SegMmcfgBase;
UINT32 StackPresentBitmap;
UINT16 CxlPresentBitmap;
UINT16 Cxl20CapableBitmap;
UINT8 TotM3Kti;
UINT16 Cxl1p1PresentBitmap; // Bitmap of stacks where CXL 1p1 is connected
UINT16 CxlCapableBitmap; // Bitmap of stacks capable of CXL
UINT8 TotCha;
UINT32 ChaList[MAX_CHA_MAP];
UINT32 SocId;
QPI_PEER_DATA PeerInfo[MAX_FW_KTI_PORTS]; // QPI LEP info
} QPI_CPU_DATA;
typedef struct {
UINT8 Valid;
UINT8 SocId;
QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info
} QPI_IIO_DATA;
typedef struct {
IIO_PORT_INFO PortInfo[MAX_IIO_PORTS_PER_SOCKET];
} IIO_DMI_PCIE_INFO;
typedef struct _STACK_RES {
UINT8 Personality;
UINT8 BusBase; // Base of Bus configured for this stack
UINT8 BusLimit; // Limit of Bus configured for this stack
UINT16 IoBase; // Base of IO configured for this stack
UINT16 IoLimit; // Limit of IO configured for this stack
UINT32 IoApicBase;
UINT32 IoApicLimit;
UINT32 Mmio32Base; // Base of low MMIO configured for this stack in memory map
UINT32 Mmio32Limit; // Limit of low MMIO configured for this stack in memory map
UINT64 Mmio64Base; // Base of high MMIO configured for this stack in memory map
UINT64 Mmio64Limit; // Limit of high MMIO configured for this stack in memory map
UINT8 PciResourceBusBase; // Base of Bus resource available for PCI devices
UINT8 PciResourceBusLimit; // Limit of Bus resource available for PCI devices
UINT16 PciResourceIoBase; // Base of IO resource available for PCI devices
UINT16 PciResourceIoLimit; // Limit of IO resource available for PCI devices
UINT32 PciResourceMem32Base; // Base of low MMIO resource available for PCI devices
UINT32 PciResourceMem32Limit; // Limit of low MMIO resource available for PCI devices
UINT64 PciResourceMem64Base; // Base of high MMIO resource available for PCI devices
UINT64 PciResourceMem64Limit; // Limit of high MMIO resource available for PCI devices
UINT32 VtdBarAddress; // NOTE: Obsolete, not used in next gen platforms
} STACK_RES;
/**
* PCI resources that establish one PCI hierarchy for PCI Enumerator.
*/
@ -197,122 +124,87 @@ typedef struct {
UINT64 Mmio64Limit; // Limit of high MMIO resources available for PCI devices
} UDS_PCIROOT_RES;
/**
* This structore keeps resources configured in Host I/O Processor (HIOP) for one stack.
* One HIOP may produce more than one PCI hierarchy, these are in PciRoot[] table.
*/
typedef struct {
UINT8 Personality;
UINT8 PciRootBridgeNum; // Number of valid entries in PciRoot[] table
UINT8 Segment; // Segment for this stack
UINT8 BusBase; // Base of Bus configured for this stack
UINT8 BusLimit; // Limit of Bus configured for this stack
UINT8 Reserved[3]; // Reserved for alignment
UINT16 IoBase; // Base of IO configured for this stack
UINT16 IoLimit; // Limit of IO configured for this stack
UINT32 IoApicBase;
UINT32 IoApicLimit;
UINT32 Mmio32Base; // Base of low MMIO configured for this stack in memory map
UINT32 Mmio32Limit; // Limit of low MMIO configured for this stack in memory map
UINT32 Mmio32MinSize; // The size of MMIO32 needed in PEI that must be preserved in rebalance
UINT64 Mmio64Base; // Base of high MMIO configured for this stack in memory map
UINT64 Mmio64Limit; // Limit of high MMIO configured for this stack in memory map
UDS_PCIROOT_RES PciRoot[MAX_IIO_PCIROOTS_PER_STACK];
UINT64 VtbarAddress; // VT-d Base Address
UINT64 ChbcrBarAddress;
UINT64 ChbcrBarAddress; // CXL Host Bridge Component Registers (CHBCR) region
UDS_PCIROOT_RES PciRoot[MAX_IIO_PCIROOTS_PER_STACK];
} UDS_STACK_RES;
/**
* This structore keeps resource ranges configured in one socket. It contains a table of IO stacks provided by
// the socket. The stacks are also groupded by IO dies, but dies are not reflected in UDS.
*/
typedef struct {
UINT8 Valid;
UINT8 SocketID; // Socket ID of the IIO (0..3)
UINT8 BusBase;
UINT8 BusLimit;
UINT8 SocketID; // Socket ID of the IIO (0..3)
UINT16 IoBase;
UINT16 IoLimit;
UINT32 IoApicBase;
UINT32 IoApicLimit;
UINT32 Mmio32Base; // Base of low MMIO configured for this socket in memory map
UINT32 Mmio32Limit; // Limit of low MMIO configured for this socket in memory map
UINT64 Mmio64Base; // Base of high MMIO configured for this socket in memory map
UINT64 Mmio64Limit; // Limit of high MMIO configured for this socket in memory map
UINT32 Mmio32Base; // Base of low MMIO configured for this socket in memory map
UINT32 Mmio32Limit; // Limit of low MMIO configured for this socket in memory map
UINT64 Mmio64Base; // Base of high MMIO configured for this socket in memory map
UINT64 Mmio64Limit; // Limit of high MMIO configured for this socket in memory map
UDS_STACK_RES StackRes[MAX_LOGIC_IIO_STACK];
} UDS_SOCKET_RES;
/**
* This structore keeps resource ranges configured in whole system.
*/
typedef struct {
UINT8 Valid;
UINT8 SocketID; // Socket ID of the IIO (0..3)
UINT8 BusBase;
UINT8 BusLimit;
UINT16 PciResourceIoBase;
UINT16 PciResourceIoLimit;
UINT32 IoApicBase;
UINT32 IoApicLimit;
UINT32 Mmio32Base; // Base of low MMIO configured for this socket in memory map
UINT32 Mmio32Limit; // Limit of low MMIO configured for this socket in memory map
UINT64 Mmio64Base; // Base of high MMIO configured for this socket in memory map
UINT64 Mmio64Limit; // Limit of high MMIO configured for this socket in memory map
UDS_STACK_RES StackRes[MAX_LOGIC_IIO_STACK];
IIO_DMI_PCIE_INFO PcieInfo; // NOTE: Obsolete, not used in next gen platforms
} IIO_RESOURCE_INSTANCE;
typedef struct {
UINT16 PlatGlobalIoBase; // Global IO Base
UINT16 PlatGlobalIoLimit; // Global IO Limit
UINT32 PlatGlobalMmio32Base; // Global Mmiol base
UINT32 PlatGlobalMmio32Limit; // Global Mmiol limit
UINT64 PlatGlobalMmio64Base; // Global Mmioh Base [43:0]
UINT64 PlatGlobalMmio64Limit; // Global Mmioh Limit [43:0]
QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU
QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO
UINT16 SystemIoBase; // System IO Base
UINT16 SystemIoLimit; // System IO Limit
UINT32 SystemMmio32Base; // System low MMIO base
UINT32 SystemMmio32Limit;
UINT32 Mmio32Granularity;
UINT64 SystemMmio64Base; // System high MMIO Base
UINT64 SystemMmio64Limit; // System high MMIO Limit
UINT64 Mmio64Granularity;
UINT32 MemTsegSize;
UINT64 PciExpressBase;
UINT32 PciExpressSize;
UINT32 MemTolm;
UDS_SOCKET_RES IIO_resource[MAX_SOCKET];
UINT8 numofIIO;
UINT8 MaxBusNumber;
UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
UINT8 EVMode;
UINT8 SkuPersonality[MAX_SOCKET];
UINT16 IoGranularity;
UINT32 MmiolGranularity;
UINT64_STRUCT MmiohGranularity;
UINT8 RemoteRequestThreshold; //5370389
UINT32 UboxMmioSize;
UINT32 MaxAddressBits;
UINT16 SystemIoBase; // System IO Base
UINT16 SystemIoLimit; // System IO Limit
UINT32 SystemIoApicBase; // Legacy IOAPIC base address, one in the system
UINT32 SystemIoApicLimit;
UINT32 SystemMmio32Base; // System low MMIO base
UINT32 SystemMmio32Limit; // System low MMIO limit
UINT64 SystemMmio64Base; // System high MMIO Base
UINT64 SystemMmio64Limit; // System high MMIO Limit
QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU
UINT64 PciExpressBase; // PCI Config Space base address
UINT64 PciExpressSize; // PCI Config Space size
UDS_SOCKET_RES IIO_resource[MAX_SOCKET];
UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
UINT16 IoGranularity;
UINT32 Mmio32Granularity;
UINT64 Mmio64Granularity;
UINT32 UboxMmioSize;
UINT32 MemTolm;
UINT32 MemTsegSize;
UINT32 MaxAddressBits;
} PLATFORM_DATA;
typedef struct {
UINT8 CurrentUpiiLinkSpeed;// Current programmed UPI Link speed (Slow/Full speed mode)
BOOLEAN FailFlag;
CHAR16 Message[MAX_MESSAGE_LENGTH];
} REBALANCE_FAIL_INFO;
typedef struct {
UINT8 CurrentUpiiLinkSpeed; // Current programmed UPI Link speed (Slow/Full speed mode)
UINT8 CurrentUpiLinkFrequency; // Current requested UPI Link frequency (in GT)
UINT8 OutKtiCpuSktHotPlugEn; // 0 - Disabled, 1 - Enabled for PM X2APIC
UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM
UINT8 IsocEnable;
UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB
UINT8 DmiVc1;
UINT8 DmiVcm;
UINT32 CpuPCPSInfo;
UINT8 cpuSubType;
UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB
UINT8 SystemRasType;
UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
UINT16 tolmLimit;
RC_VERSION RcVersion;
BOOLEAN MsrTraceEnable;
UINT8 DdrXoverMode; // DDR 2.2 Mode
// For RAS
UINT8 bootMode;
UINT8 OutClusterOnDieEn; // Whether RC enabled COD support
UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
UINT8 OutSncEn;
UINT8 OutNumOfCluster;
UINT8 imcEnabled[MAX_SOCKET][MAX_IMC];
UINT16 LlcSizeReg;
UINT8 chEnabled[MAX_SOCKET][MAX_CH];
UINT8 memNode[MC_MAX_NODE];
UINT8 IoDcMode;
UINT8 DfxRstCplBitsEn;
UINT8 BitsUsed; //For 5 Level Paging
REBALANCE_FAIL_INFO RebalanceFailInfo;
} SYSTEM_STATUS;
typedef struct {
@ -321,32 +213,7 @@ typedef struct {
UINT32 OemValue;
} IIO_UDS;
typedef enum {
//for ICX
IioStack0 = 0, // DmiAsPcie
IioStack1 = 1, // IOU0
IioStack2 = 2, // IOU1
IioStack3 = 3, // IOU2
IioStack4 = 4, // IOU3
IioStack5 = 5, // IOU4
//for SPR
IioStack6 = 6, // IOU5
IioStack7 = 7,
IioStack8 = 8,
IioStack9 = 9,
IioStack10 = 10,
IioStack11 = 11,
//for later SOC
IioStack12 = 12,
IioStack13 = 13,
IioStack14 = 14,
IioStack15 = 15,
IioStack16 = 16,
IioStack17 = 17,
IioStack18 = 18,
IioStackUnknown = 0xFF
} IIO_STACK;
#pragma pack()
#endif //#ifndef _IIO_UNIVERSAL_DATA_HOB_H_
#endif // _IIO_UNIVERSAL_DATA_HOB_H_

221
src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/MemoryMapDataHob.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -26,6 +26,8 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _MEMORY_MAP_DATA_HOB_H_
@ -34,37 +36,51 @@ are permitted provided that the following conditions are met:
#define MEMORY_MAP_HOB_GUID { 0xf8870015, 0x6994, 0x4b98, { 0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f } }
#ifndef MAX_SOCKET
#define MAX_SOCKET 4
#define MAX_SOCKET 2
#endif
#ifndef MAX_IMC
#define MAX_IMC 4 // Maximum memory controllers per socket
#define MAX_IMC 8 // Maximum memory controllers per socket
#endif
#ifndef MAX_MC_CH
#define MAX_MC_CH 2 // Max number of channels per MC (3 for EP)
#define MAX_MC_CH 1 // Max number of channels per MC (3 for EP)
#endif
#ifndef MAX_CH
#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
#endif
#define MAX_CXL_AMT 0
#ifndef MAX_CXL_HOST_BRIDGES
#define MAX_CXL_HOST_BRIDGES 0x6 // Maximum number of CXL host bridges per socket.
#endif
#ifndef MAX_CXL_HOST_BRIDGE_WAYS
#define MAX_CXL_HOST_BRIDGE_WAYS 0x4 // Maximum interleave ways of CXL host bridges per socket.
#endif
//
// Macro definitions for abstracted memory decoding target. The data structure is designed to
// iterate iMC and CXL host bridge host decoded memory in an unified way.
// definition for GNRSRF/GNRD/GRR
//
#define MAX_CXL_AMT MAX_CXL_HOST_BRIDGES // Max number of unique interleaves for NGN DIMM
#ifndef MAX_UNIQUE_NGN_DIMM_INTERLEAVE
#define MAX_UNIQUE_NGN_DIMM_INTERLEAVE 2 // Max number of unique interleaves for NGN DIMM
#define MAX_UNIQUE_NGN_DIMM_INTERLEAVE 2 // Max number of unique interleaves for NGN DIMM
#endif
#ifndef MAX_SPARE_RANK
#define MAX_SPARE_RANK 2 // Max number of spare ranks in a channel
#define MAX_SPARE_RANK 2 // Max number of spare ranks in a channel
#endif
#ifndef MAX_HBM_IO
#define MAX_HBM_IO 4
#define MAX_HBM_IO 4
#endif
#ifndef MAX_DIMM
#define MAX_DIMM 2 // Max DIMM per channel
#define MAX_DIMM 2 // Max DIMM per channel
#endif
#ifndef MAX_RANK_DIMM
@ -72,7 +88,7 @@ are permitted provided that the following conditions are met:
#endif
#ifndef MAX_DRAM_CLUSTERS
#define MAX_DRAM_CLUSTERS 4
#define MAX_DRAM_CLUSTERS 6
#endif
#ifndef MAX_SAD_RULES
@ -83,17 +99,17 @@ are permitted provided that the following conditions are met:
#define MAX_FPGA_REMOTE_SAD_RULES 2 // Maximum FPGA sockets exists on ICX platform
#endif
#define MAX_SI_SOCKET 8 // Maximum silicon supported socket number
#define MAX_SI_SOCKET 8 // Maximum silicon supported socket number
#define MAX_AMT (MAX_IMC+MAX_CXL_AMT) // Max abstract memory target per socket
#define AMT_MAX_NODE ((MAX_AMT)*(MAX_SOCKET)) // Max abstract memory target for all sockets
#define MAX_AMT (MAX_IMC+MAX_CXL_AMT) // Max abstract memory target per socket
#define AMT_MAX_NODE ((MAX_AMT)*(MAX_SOCKET)) // Max abstract memory target for all sockets
// NGN
#define NGN_MAX_SERIALNUMBER_STRLEN 4
#define NGN_MAX_PARTNUMBER_STRLEN 30
#define NGN_FW_VER_LEN 4
#define NGN_LOG_TYPE_NUM 2
#define NGN_LOG_LEVEL_NUM 2
#define NGN_MAX_SERIALNUMBER_STRLEN 4
#define NGN_MAX_PARTNUMBER_STRLEN 30
#define NGN_FW_VER_LEN 4
#define NGN_LOG_TYPE_NUM 2
#define NGN_LOG_LEVEL_NUM 2
/**
* Memory channel index conversion macros.
@ -115,25 +131,14 @@ are permitted provided that the following conditions are met:
#define MEM_KBYTES_TO_64MB(SizeKB) ((SizeKB) >> 16)
#define MEM_MBYTES_TO_64MB(SizeMB) ((SizeMB) >> 6)
typedef UINT8 CXL_INTLV_SET_KEY;
typedef UINT8 INTLV_SET_KEY;
#define FSP_RESERVED1_LEN 77
#define FSP_RESERVED2_LEN 2174
#define FSP_RESERVED3_LEN 21
#define FSP_RESERVED4_LEN 130
#define FSP_RESERVED5_LEN 10
#define FSP_RESERVED6_LEN 800
#define FSP_RESERVED1_LEN 5476
#define FSP_RESERVED2_LEN 1
#define FSP_RESERVED3_LEN 220
#define FSP_RESERVED4_LEN 10
#pragma pack(1)
typedef enum {
DIMM_RANK_MAP_OUT_UNKNOWN = 0,
DIMM_RANK_MAP_OUT_MEM_DECODE,
DIMM_RANK_MAP_OUT_POP_POR_VIOLATION,
DIMM_RANK_MAP_OUT_RANK_DISABLED,
DIMM_RANK_MAP_OUT_ADVMEMTEST_FAILURE,
DIMM_RANK_MAP_OUT_MAX
} DIMM_RANK_MAP_OUT_REASON;
struct RankDevice {
UINT8 enabled; // 0 = disabled, 1 = enabled
UINT8 logicalRank; // Logical Rank number (0 - 7)
@ -154,55 +159,58 @@ typedef struct firmwareRev {
} FIRMWARE_REV;
typedef struct DimmDevice {
UINT8 Present;
BOOLEAN Enabled;
UINT8 DcpmmPresent; // 1 - This is a DCPMM
UINT8 X4Present;
UINT8 DramIoWidth; // Actual DRAM IO Width (4, 8, 16)
UINT8 NumRanks;
UINT8 keyByte;
UINT8 actKeyByte2; // Actual module type reported by SPD
UINT8 actSPDModuleOrg; // Actual number of DRAM ranks and device width
UINT8 dimmTs; // Thermal sensor data.
UINT16 VolCap; // Volatile capacity (AEP DIMM only)
UINT16 nonVolCap; // Non-volatile capacity (AEP DIMM only)
UINT16 DimmSize;
UINT32 NVmemSize;
UINT16 SPDMMfgId; // Module Mfg Id from SPD
UINT16 VendorID;
UINT16 DeviceID;
UINT16 RevisionID;
UINT32 perRegionDPA; // DPA of PMEM that Nfit needs
struct PersisentDpaMap perDPAMap[MAX_UNIQUE_NGN_DIMM_INTERLEAVE]; // DPA map
UINT8 serialNumber[NGN_MAX_SERIALNUMBER_STRLEN]; // Serial Number
UINT8 PartNumber[NGN_MAX_PARTNUMBER_STRLEN]; // Part Number
UINT8 FirmwareVersionStr[NGN_FW_VER_LEN]; // Used to update the SMBIOS TYPE 17
struct firmwareRev FirmwareVersion; // Firmware revision
struct RankDevice rankList[MAX_RANK_DIMM];
UINT16 InterfaceFormatCode;
UINT16 SubsystemVendorID;
UINT16 SubsystemDeviceID;
UINT16 SubsystemRevisionID;
UINT16 FisVersion; // Firmware Interface Specification version
UINT8 DimmSku; // Dimm SKU info
UINT8 manufacturingLocation; // Manufacturing location for the NVDIMM
UINT16 manufacturingDate; // Date the NVDIMM was manufactured
INT32 commonTck;
UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
BOOLEAN NvDimmNPresent; // JEDEC NVDIMM-N Type Memory Present
UINT8 CidBitMap; // SubRankPer CS for DIMM device
UINT16 SPDRegVen; // Register Vendor ID in SPD
DIMM_RANK_MAP_OUT_REASON MapOutReason;
UINT8 Present;
BOOLEAN Enabled;
UINT8 DcpmmPresent; // 1 - This is a DCPMM
UINT8 X4Present;
UINT8 DramIoWidth; // Actual DRAM IO Width (4, 8, 16)
UINT8 NumRanks; // Number of ranks on dimm
UINT8 NumPackageRanks; // Number of Package ranks on dimm
// For DDR5 NumRanks and NumPackageRanks same
// For MCR NumRanks and NumPackageRanks may differ
UINT8 keyByte;
UINT8 actKeyByte2; // Actual module type reported by SPD
UINT8 actSPDModuleOrg; // Actual number of DRAM ranks and device width
UINT8 dimmTs; // Thermal sensor data.
UINT16 VolCap; // Volatile capacity (AEP DIMM only)
UINT16 nonVolCap; // Non-volatile capacity (AEP DIMM only)
UINT16 DimmSize;
UINT16 SPDMMfgId; // Module Mfg Id from SPD
UINT16 VendorID;
UINT16 DeviceID;
UINT16 RevisionID;
UINT32 perRegionDPA; // DPA of PMEM that Nfit needs
struct PersisentDpaMap perDPAMap[MAX_UNIQUE_NGN_DIMM_INTERLEAVE]; // DPA map
UINT8 serialNumber[NGN_MAX_SERIALNUMBER_STRLEN]; // Serial Number
UINT8 PartNumber[NGN_MAX_PARTNUMBER_STRLEN]; // Part Number
UINT8 FirmwareVersionStr[NGN_FW_VER_LEN]; // Used to update the SMBIOS TYPE 17
struct firmwareRev FirmwareVersion; // Firmware revision
struct RankDevice rankList[MAX_RANK_DIMM];
UINT16 InterfaceFormatCode;
UINT16 SubsystemVendorID;
UINT16 SubsystemDeviceID;
UINT16 SubsystemRevisionID;
UINT16 FisVersion; // Firmware Interface Specification version
UINT8 DimmSku; // Dimm SKU info
UINT8 manufacturingLocation; // Manufacturing location for the NVDIMM
UINT16 manufacturingDate; // Date the NVDIMM was manufactured
INT32 commonTck;
UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
BOOLEAN NvDimmNPresent; // JEDEC NVDIMM-N Type Memory Present
UINT8 CidBitMap; // SubRankPer CS for DIMM device
UINT16 SPDRegVen; // Register Vendor ID in SPD
UINT8 SPDOtherOptFeatures; // SDRAM Other Optional features
BOOLEAN DimmChanged;
} MEMMAP_DIMM_DEVICE_INFO_STRUCT;
struct ChannelDevice {
typedef struct ChannelDevice {
UINT8 Enabled; // 0 = channel disabled, 1 = channel enabled
UINT8 Features; // Bit mask of features to enable or disable
UINT8 MaxDimm; // Number of DIMM
UINT8 NumRanks; // Number of ranks on this channel
UINT8 chFailed;
UINT8 ngnChFailed;
UINT8 Is9x4DimmPresent; // 9x4 dimm present indicator
UINT8 Is4BitEccDimmPresent; // 4-bit Ecc dimm present indicator
UINT8 SpareLogicalRank[MAX_SPARE_RANK]; // Logical rank, selected as Spare
UINT8 SparePhysicalRank[MAX_SPARE_RANK]; // Physical rank, selected as spare
UINT16 SpareRankSize[MAX_SPARE_RANK]; // spare rank size
@ -210,11 +218,11 @@ struct ChannelDevice {
UINT8 DdrPopulationMap; // Bitmap to indicate location of DDR DIMMs within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
UINT8 PmemPopulationMap; // Bitmap to indicate location of PMem modules within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
MEMMAP_DIMM_DEVICE_INFO_STRUCT DimmInfo[MAX_DIMM];
};
} CHANNEL_DEVICE;
struct memcontroller {
typedef struct memcontroller {
UINT32 MemSize;
};
} MEMCONTROLLER;
typedef enum {
MemTypeNone = 0,
@ -251,8 +259,8 @@ typedef struct SADTable {
UINT8 FMchannelInterBitmap[MAX_AMT]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
UINT8 NmChWays; // Channel Interleave ways for SAD. Represents channelInterBitmap ways for DDR4/NM.
UINT8 FmChWays; // Channel Interleave ways for SAD. Represents FMchannelInterBitmap ways for DDRT.
UINT16 imcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket.
UINT16 NmImcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket as NM.
UINT32 imcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket.
UINT32 NmImcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket as NM.
BOOLEAN local; // 0 - Remote 1- Local
UINT8 IotEnabled; // To indicate if IOT is enabled
UINT8 mirrored; // To Indicate the SAD is mirrored while enabling partial mirroring
@ -260,8 +268,9 @@ typedef struct SADTable {
UINT8 tgtGranularity; // Interleave mode for target list
UINT8 Cluster; // SNC cluster, hemisphere, or quadrant index.
UINT8 HostBridgeGran; // Host bridge interleaving granularity.
UINT8 HostBridgeList[MAX_CXL_HOST_BRIDGE_WAYS]; // List of interleaved CXL host bridges.
UINT32 HotPlugPadSize; // Memory size padded for CXL hot plug. 0 if it is not a CXL hot plug SAD.
CXL_INTLV_SET_KEY CxlIntlvSetKey; // The unique key of CXL interleave set. (7nm)
INTLV_SET_KEY CxlIntlvSetKey; // The unique key of CXL interleave set. (7nm)
} SAD_TABLE;
typedef struct socket {
@ -271,10 +280,9 @@ typedef struct socket {
UINT8 imcEnabled[MAX_IMC];
UINT8 SadIntList[MAX_DRAM_CLUSTERS * MAX_SAD_RULES][AMT_MAX_NODE]; // SAD interleave list
UINT32 SktTotMemMapSPA; // Total memory mapped to SPA
UINT32 SktMemSize2LM; // Total memory excluded from Limit
SAD_TABLE SAD[MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; // SAD table
struct memcontroller imc[MAX_IMC];
struct ChannelDevice ChannelInfo[MAX_CH];
MEMCONTROLLER imc[MAX_IMC];
CHANNEL_DEVICE ChannelInfo[MAX_CH];
} MEMMAP_SOCKET;
typedef struct {
@ -287,9 +295,10 @@ typedef struct SystemMemoryMapElement {
UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
UINT8 NodeId; // Node ID of the HA Owning the memory
UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA
UINT8 ClusterId; // Logical cluster Id of SNC cluster - only 0 in UMA clustering and all2all
UINT8 SktInterBitmap; // Socket interleave bitmap, if more that on socket then ImcInterBitmap and ChInterBitmap are identical in all sockets
UINT16 ImcInterBitmap; // IMC interleave bitmap for this memory
UINT8 ChInterBitmap[MAX_IMC];//Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
UINT32 ImcInterBitmap; // IMC interleave bitmap for this memory
UINT8 ChInterBitmap[MAX_AMT];//Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
UINT32 BaseAddress; // Base Address of the element in 64MB chunks
UINT32 ElementSize; // Size of this memory element in 64MB chunks
} SYSTEM_MEMORY_MAP_ELEMENT;
@ -300,8 +309,6 @@ typedef struct SystemMemoryMapHob {
// All2All/Quad/Hemi modes can be considered as having only one cluster (i.e SNC1).
//
UINT8 TotalClusters;
UINT8 reserved1[FSP_RESERVED1_LEN]; // MEMORY_MAP_BLOCK_DECODER_DATA BlockDecoderData; // block decoder data structure
UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem.
UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem.
UINT32 highMemBase; // Mem base in 64MB units for above 4GB mem.
@ -310,14 +317,9 @@ typedef struct SystemMemoryMapHob {
UINT16 memFreq; // Mem Frequency
UINT16 HbmFreq; // HBM Frequency in MHz.
UINT8 memMode; // 0 - Independent, 1 - Lockstep
UINT8 volMemMode; // 0 - 1LM, 1 - 2LM
UINT8 CacheMemType; // 0 - DDR$DDRT, 1 - HBM$DDR. Only valid if volMemMode is 2LM
UINT8 VolMemMode; // 0 - 1LM, 1 - 2LM
UINT16 DramType;
UINT8 DdrVoltage;
BOOLEAN SupportedPMemPresent; // TRUE if at least one PMem is present and supported by BIOS
BOOLEAN EkvPresent; // Set if EKV controller on system
BOOLEAN BwvPresent; // Set if BWV controller on system
BOOLEAN CwvPresent; // Set if CWV controller on system
UINT8 XMPProfilesSup;
UINT8 XMPCapability;
//
@ -336,35 +338,20 @@ typedef struct SystemMemoryMapHob {
UINT8 NumChPerMC;
UINT8 numberEntries; // Number of Memory Map Elements
SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES];
UINT8 reserved2[FSP_RESERVED2_LEN]; // struct memSetup MemSetup;
UINT8 reserved3[FSP_RESERVED3_LEN]; // MEM_DFXMEMVARS DfxMemVar;
UINT8 reserved1[FSP_RESERVED1_LEN]; // struct memSetup MemSetup;
UINT8 reserved2[FSP_RESERVED2_LEN]; // MEM_DFXMEMVARS DfxMemVar;
MEMMAP_SOCKET Socket[MAX_SOCKET];
UINT8 reserved4[FSP_RESERVED4_LEN]; // struct memTiming profileMemTime[XMP_MAX_PROFILES];
UINT8 reserved3[FSP_RESERVED3_LEN]; // struct memTiming profileMemTime[XMP_MAX_PROFILES];
UINT8 reserved5[FSP_RESERVED5_LEN]; // RASMEMORYINFO RasMeminfo;
UINT8 LatchSystemShutdownState;
BOOLEAN IsWpqFlushSupported;
UINT8 EadrSupport;
UINT8 EadrCacheFlushMode;
UINT8 SetSecureEraseSktChHob[MAX_SOCKET][MAX_CH]; //MAX_CH * MAX_SOCKET * MAX_DCPMM_CH
UINT8 reserved6[FSP_RESERVED6_LEN]; // HOST_DDRT_DIMM_DEVICE_INFO_STRUCT HostDdrtDimmInfo[MAX_SOCKET][MAX_CH];
UINT8 reserved4[FSP_RESERVED4_LEN]; // RASMEMORYINFO RasMeminfo;
UINT32 DdrCacheSize[MAX_SOCKET][MAX_CH]; // Size of DDR memory reserved for 2LM cache (64MB granularity)
BOOLEAN AdrStateForPmemModule[MAX_SOCKET][MAX_CH]; // ADR state for Intel PMEM Modules
UINT16 BiosFisVersion; // Firmware Interface Specification version currently supported by BIOS
UINT16 MaxAveragePowerLimit; // Max Power limit in mW used for averaged power ( Valid range ends at 15000mW)
UINT16 MinAveragePowerLimit; // Min Power limit in mW used for averaged power ( Valid range starts from 10000mW)
UINT16 CurrAveragePowerLimit; // Current Power limit in mW used for average power
UINT16 MaxMbbPowerLimit; // Max MBB power limit ( Valid range ends at 18000mW).
UINT16 MinMbbPowerLimit; // Min MBB power limit ( Valid range starts from 15000mW).
UINT16 CurrMbbPowerLimit; // Current Power limit in mW used for MBB power
UINT32 MaxMbbAveragePowerTimeConstant; // Max MBB Average Power Time Constant
UINT32 MinMbbAveragePowerTimeConstant; // Min MBB Average Power Time Constant
UINT32 CurrMbbAveragePowerTimeConstant; // Current MBB Average Power Time Constant
UINT32 MmiohBase; // MMIOH base in 64MB granularity
UINT8 MaxSadRules; // Maximum SAD entries supported by silicon (24 for 14nm silicon, 16 for 10nm silicon)
UINT8 MaxSadRules; // Maximum SAD entries supported by silicon (16 for 10nm silicon)
UINT8 NumberofChaDramClusters; // Number of CHA DRAM decoder clusters
BOOLEAN VirtualNumaEnable; // Enable or Disable Virtual NUMA
UINT8 VirtualNumOfCluster; // Number of Virtual NUMA nodes in each physical NUMA node (Socket or SNC cluster)
UINT8 VirtualNumaNodes; // Number of virtual NUMA nodes per physical NUMA node (non-zero)
BOOLEAN McrMemFreqRangeEn; // MCR Memory Frequency range enabled.
} SYSTEM_MEMORY_MAP_HOB;
#pragma pack()

7
src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/PrevBootErrSrcHob.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -26,13 +26,14 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _PREV_BOOT_ERR_SRC_HOB_H_
#define _PREV_BOOT_ERR_SRC_HOB_H_
#define FSP_PREV_BOOT_ERR_SRC_HOB_GUID \
{ 0xc5, 0xb5, 0x38, 0x51, 0x69, 0x93, 0xec, 0x48, 0x5b, 0x97, 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 }
#define FSP_PREV_BOOT_ERR_SRC_HOB_GUID { 0x5138b5c5, 0x9369, 0x48ec, { 0x5b, 0x97, 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 } }
#define PREV_BOOT_ERR_SRC_HOB_SIZE 1000

52
src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/SystemInfoHob.h
View file

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -26,42 +26,41 @@ are permitted provided that the following conditions are met:
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef _SYSTEM_INFO_HOB_H_
#define _SYSTEM_INFO_HOB_H_
#define SYSTEM_INFO_HOB_GUID { 0x7650A0F2, 0x0D91, 0x4B0C, { 0x92, 0x3B, 0xBD, 0xCF, 0x22, 0xD1, 0x64, 0x35 }}
#define SYSTEM_INFO_HOB_GUID { 0x7650A0F2, 0x0D91, 0x4B0C, { 0x92, 0x3B, 0xBD, 0xCF, 0x22, 0xD1, 0x64, 0x35 } }
#ifndef MAX_SOCKET
#define MAX_SOCKET 4
#define MAX_SOCKET 2
#endif
#ifndef MAX_IIO_STACK
#define MAX_IIO_STACK 12
#define MAX_IIO_STACK 16
#endif
#define MAX_LOGIC_IIO_STACK 14
#define MAX_LOGIC_IIO_STACK 18
#define MAX_HPM_PFS_ENTRY_NUM 15 // Number of entries in PFS structure
#define HPM_PFS_ENTRY_SIZE 2 // Entry size of PFS structure in DWORD
#ifndef MAX_IMC
#define MAX_IMC 4 // Maximum memory controllers per socket
#define MAX_IMC 8 // Maximum memory controllers per socket
#endif
#ifndef MAX_MC_CH
#define MAX_MC_CH 2 // Max number of channels per MC (3 for EP)
#define MAX_MC_CH 1 // Max number of channels per MC (3 for EP)
#endif
#ifndef MAX_CH
#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
#endif
#define MAX_HPM_PFS_ENTRY_NUM 15 // Number of entries in PFS structure
#define HPM_PFS_ENTRY_SIZE 2 // Entry size of PFS structure in DWORD
#pragma pack(1)
#ifndef MMIO_BARS_ENUM
#define MMIO_BARS_ENUM
typedef enum {
TYPE_SCF_BAR = 0,
TYPE_PCU_BAR,
@ -76,7 +75,6 @@ typedef enum {
TYPE_SBREG_BAR,
TYPE_MAX_MMIO_BAR
} MMIO_BARS;
#endif
typedef enum {
ReservedMemSs,
@ -95,7 +93,7 @@ typedef enum BootMode {
// in addition to the sub-boot type (WarmBoot, WarmBootFast, etc).
S3Resume = 1 // S3 flow through RC. Should do the bare minimum required for S3
// init and be optimized for speed.
} BootMode;
} BOOT_MODE;
//
// This is used to determine what type of die is connected to a UPI link
@ -163,19 +161,6 @@ typedef struct {
} HPM_VSEC_RESOURCE;
//
// Stack id swap information, which includes stack swap flag and the new stack id swap array.
//
typedef struct {
BOOLEAN StackSwapFlag;
UINT8 StackIdSwapArray[MAX_IIO_STACK];
} STACKID_SWAP_INFO;
typedef struct {
UINT64 Cxl1p1RcrbBase;
BOOLEAN Cxl1p1RcrbValid;
} CXL_1P1_RCRB;
typedef struct {
UINT32 StackPresentBitmap[MAX_SOCKET]; ///< bitmap of present stacks per socket
UINT8 StackBus[MAX_SOCKET][MAX_LOGIC_IIO_STACK];///< Bus of each stack
@ -188,7 +173,6 @@ typedef struct {
UINT8 segmentSocket[MAX_SOCKET];
UINT8 KtiPortCnt;
UINT32 socketPresentBitMap;
UINT32 SecondaryNodeBitMap;
UINT32 FpgaPresentBitMap;
UINT32 mmCfgBase;
UINT64 SocketMmCfgBase[MAX_SOCKET];
@ -220,13 +204,17 @@ typedef struct {
BOOLEAN DataPopulated; // CPU_CSR_ACCESS_VAR is unavailable when FALSE
HPM_VSEC_RESOURCE SocketHpmVsecRes[MAX_SOCKET]; // HPM VSEC info for all sockets
BOOLEAN HbmSku;
UINT8 HcxType[MAX_SOCKET];
STACKID_SWAP_INFO StackIdSwapInfo[MAX_SOCKET]; //StackID sync after do StackId swap,including Stack swap table and whether do stack swap
CXL_1P1_RCRB Cxl1p1Rcrb[MAX_SOCKET][MAX_IIO_STACK]; // CXL 1.1 RCRB, one per PI5 stack
UINT64 Cxl1p1Rcrb[MAX_SOCKET][MAX_IIO_STACK]; // CXL 1.1 RCRB, one per PI5 stack
UINT64 CxlRbBar[MAX_SOCKET][MAX_IIO_STACK]; // CXL RBBAR, one per PI5 stack
UINT32 DmiRcrb[MAX_SOCKET]; // DMI RCRB region, one per socket
UINT8 FabricType; //Compute die 10x6, 10x5, and 6x5 type is stored
UINT8 ChopType; //Compute Die Chop Type
UINT8 MdfInstCount;
UINT32 UboxMmioSize;
UINT32 UboxScfMmioSize;
UINT64 PpinValue[MAX_SOCKET]; // The Protected Processor Inventory Number from CPU MSRs
UINT32 OobMsmPciBaseAddress[MAX_SOCKET];
UINT32 S3mControlRegisterBaseAddress[MAX_SOCKET];
} CPU_CSR_ACCESS_VAR;
typedef struct {
@ -261,7 +249,7 @@ typedef struct {
UINT32 CheckPoint;
UINT8 ResetRequired;
UINT8 Emulation;
BootMode SysBootMode;
BOOT_MODE SysBootMode;
CPU_CSR_ACCESS_VAR CpuCsrAccessVarHost; // Common resource for CsrAccessRoutines
UINT64 CpuFreq;
UINT8 SocketId;