Transition library acts as a common interface for handling exceptions. The only
thing that needs to be implemented by exception.c is the exc_dispatch routine to
handle the exceptions as required.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully and exceptions are tested using test_exc
Change-Id: Ibb643d7ea2f9aabbc66439549ea2168fd66ced5e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/217143
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Transition library provides the following functionalities:
1) Setup the environment for switching to any particular EL and jump to the
loaded program at that EL. In short "Execute program X at exception level Y
using the state Z"
2) Provides routines for exception entry and exception exit that can be used by
any program to implement exception handling. The only routine required by the
program would be exc_dispatch which handles the exception in its own required
way and returns by making a call to exc_exit. On exc_exit, the transition
library unwinds the whole stack by popping out the saved state of xregs
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully and exceptions are tested for ramstage on ryu
Change-Id: I90f664ac657258724dc0c79bd9f6ceef70064f90
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/216375
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
If mmu_init is called more than once then, free_idx should be reset to
1. Here, the assumption would be that mmu_init will not be called more than
once. However, this is not necessarily true. Thus, free_idx should be reset to 1
every time we are initializing ttb from scratch.
BUG=None
BRANCH=None
TEST=Compiles sucessfully and boots to kernel
Change-Id: Idb7424df7dd577f263f12d1527dbd7fb89216d40
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/216906
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
this allows vb2_working_data to be accessed from stages running on different cpu
architectures.
BUG=none
TEST=Built firmware for Blaze with USE=+/-vboot2. Ran faft on Blaze.
BRANCH=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: Ife2844637af8bf9e0d032a50fb516d98b8f80497
Reviewed-on: https://chromium-review.googlesource.com/217835
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Disable Root Port0 only when there is no PCIe device
present on any root port.
BUG=None
TEST=Boot Rambi with PCIe installed/non-installed on RP0 to
confirm the RP0 is correctly enabled/disabled. However, I still
need someone to help check if RP0(no device) is still enabled
if there is device on other RPs since since I have no devices
having slots from RP1/2/3.
Change-Id: I7147569e78b2d1ecea070bc933773cdcae59f9e7
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/217791
Tested-by: Ted Kuo <tedkuo@ami.com.tw>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Rush builds were throwing a _sync_sp_el0 exception due
to commit 65af2f3d (tegra132: support arm64 SMP bringup).
Fixed by copying over the rush_ryu devicetree.db, which
adds all the CPUs to the device tree. Basically the same
as commit 8f61ca2da but for rush.
BUG=None
BRANCH=None
TEST=Booted rush OK, brought up rush kernel from USB.
Change-Id: Ic9e34494ec8e6ad82e6020df6ad6fecd8763ac7e
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/217792
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With CONFIG_RETURN_FROM_VERSTAGE false, the verstage loads the romstage over
the bootblock, then exits to the romstage. this is necessary for some SOC
(e.g. tegra124) which runs the bootblock on a different architecture.
With CONFIG_RETURN_FROM_VERSTAGE true, the verstage returns to the bootblock.
Then, the bootblock loads the romstage over the verstage and exits to the
romstage. this is probably necessary for some SOC (e.g. rockchip) which does not
have SRAM big enough to fit the verstage and the romstage at the same time.
BUG=none
TEST=Built Blaze with USE=+/-vboot2. Ran faft on Blaze.
BRANCH=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I673945c5e21afc800d523fbb25d49fdc83693544
Reviewed-on: https://chromium-review.googlesource.com/212365
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If there are no devices underneath a device in a devicetree the
bus pointer in a struct device is NULL. Check for this condition
before proceeding in walking through the children devices.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Ran through coreboot w/o any devices under the cpu_cluster device.
No more exceptions.
Change-Id: I891aeb36319dce67ce9e431156c85c74177c7ab7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217511
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Intel will be making slight changes to USB3 PLL VCO and iCLK PLL current
on C0 stepping of BYT-M/D C0 stepping in order to meet the high demands
for these processors.
Pre-conversion materials are compatible with USB PLL VCO current increase.
Post-conversion materials ARE REQUIRED to be run with increased USB3 PLL
VCO current.
BUG=chrome-os-partner:31199
TEST=Boot Rambi, then read USHPHY_CDN_PLL_CONTROL and verify register
has new value.
Change-Id: Ie9c3d0afd54ea7ced2c76ebb948de95be0828fa0
Signed-off-by: Kein Yuan <kein.yuan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/211337
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit df20eca47ca0ff33baf5d554ef11dd2b35706a5d)
Reviewed-on: https://chromium-review.googlesource.com/205970
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217772
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Kenji Chen <kenji.chen@intel.com>
Tested-by: Kenji Chen <kenji.chen@intel.com>
This patch adds code to read the board ID from Pinky and put it into the
coreboot table.
(Note: This implementation differs slightly from Tegra since it pinmuxes
the GPIOs inside board_id(). That means the pinmuxing might be set more
than once if called in multiple stages, which is perfectly harmless and
in my opinion cleaner than having to (remember to) do it manually in one
of the per-stage files.)
BUG=chrome-os-partner:30167
TEST=With depthcharge patch, select -rev1 device tree for board ID 0.
Change-Id: I5b5689373e1e47b1e0944b5fe5f2e70a285b931f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217675
Reviewed-by: David Hendricks <dhendrix@chromium.org>
We retroactively decided to use the variant name "pinky" for the Rk3288
board we're currently bringing up, and retcon the unadorned "veyron"
name to refer to the Rockchip evaluation board. Since we currently have
no interest to maintain coreboot support for that board in our tree,
let's rename everything to "veyron_pinky" and forget about "veyron".
CQ-DEPEND=CL:217592
BUG=chrome-os-partner:30167
TEST='emerge-veyron libpayload coreboot' fails but
'emerge-veyron_pinky libpayload coreboot' succeeds.
Change-Id: I366391efc8e0a7c610584b50cea331a0164da6f3
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217674
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Some files for the veyron project were checked in with execute
permissions where it doesn't make sense. Fix.
BUG=chrome-os-partner:30167
TEST=None
Change-Id: Ia3788abf3755baf028518efb975701cf6cb37e46
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217673
Reviewed-by: David Hendricks <dhendrix@chromium.org>
In some cases, we need to use 1 common VGA device ID to share
among different VGA devices.
But it will show error when it can't find a specific pci rom
by PCI DID.
in fact, it will find the pci rom with common vga ID.
Without this commit, you may need to skip error check during
suspend_stress_test
BUG=none
BRANCH=none
TEST=build OK, and check no error on Auron and Samus
Change-Id: Ib743e960f772b7e2e73a1feb80790a13bd8c06c7
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/217415
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
The actual level required to take the ethernet switch out of reset is
low, not high.
BUG=chrome-os-partner:31780
TEST=with this patch applied, when proto0.2 boots, the ethernet
switch's LED blink once, as was the case with proto0.
Change-Id: I81eeb73b85cf113709b6d4ac3aa7639a40fa6719
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217416
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The ALC283 needs a double function reset to ensure that all settings
are reset and the firmware beep is functional.
This is based on dlaurie's change from:
https://chromium-review.googlesource.com/#/c/167651/
BUG=chrome-os-partner:31824
BRANCH=None
TEST=build, boot, beep
Change-Id: I9109b598234ceaea365591468dd6766b89eb3cf0
Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217127
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Mark GPIO42 as unused according to Samus schematics
BUG=None
TEST=Make the chnage; Pass the build process; Need someone having
the board perform the verification.
Change-Id: Ifd6a0d2de8af0fe3af4a14f44ce572b41b77509c
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/217344
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
By default we dont want to use the special DC instruction. Thus getting rid of
the DONT_USE_DC macro and enabling code appropriately in memset.S
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Compiles successfully and memset works fine for mmu init
Change-Id: Id89ec2c1731d21496eca617a3c03abaf48062908
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/216820
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
For now storm bootblock runs with DRAM fully initialized, this patch
puts the early console between bootblock and rom phase.
BUG=chrome-os-partner:31734
TEST=verified that preram_cbmem_console is set:
$ grep preram_cbmem_console cbfs/fallback/bootblock.map
40618000 A preram_cbmem_console
Change-Id: I132a0cbcc82e713c36fc5031706d9afbf3e9b879
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217291
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of relying on config variables to determine the current el, use
{read/write}_current macros for accessing registers.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully and boots to kernel login prompt
Change-Id: If4a5d1e9aa50ab180c8012862e2a6c37384f7f91
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/217148
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Allow read/write to registers at a given el. Also, make read/write registers at
current el call this newly added function.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully
Change-Id: I17de4c4f3bc1ee804422efe5f4703b4dd65b51f2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/216904
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Required for arm64 platforms: rmodules used for arm64 require module_params and
rodata to be placed at 8-byte boundary in order to avoid unaligned access.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully and address verified during boot
Change-Id: I4820efad2b408ebd3930943f7771805a7bbb62e9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/216374
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
In order to ease the process of reading and writing any register at current EL,
provide read_current and write_current assembly macros. These are included in
arch/lib_helpers.h under the __ASSEMBLY__ macro condition. This is done to allow
the same header file to be included by .c and .S files.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully
Change-Id: I1258850438624abfe3b1ed7240df0db0e7905be6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/216373
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
According to BIOS spec 8.14
B0:D28:F0[5:4] should be set to 11
BRANCH=none
BUG=chrome-os-partner:28234
TEST=build ok, boot to Auron and Samus
make sure register is set and PCIE is working
Change-Id: I7c37245053ceae460dac0f18363f585244db72f8
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/217414
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit 27d5d6a3 (t132: Fix clock apis) broke the Rush build.
Rush needs SBC1 (for EC) and SDMMC3 (for SD-card) added to the
table/enum in clock.h. To make future T132 board ports easier,
all periphs should have an entry in this table/enum - I just
added the 2 needed to fix the Rush build in this change.
BUG=None
BRANCH=None
TEST=Built and booted all Tegra132 boards (Rush and Ryu)
Change-Id: I6659858c24e925aec9495bf64344c0000ad19b4c
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/217342
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The proto0.2 hardware connects gpio26 (sw reset) to the ethernet
switch reset pit. The output stays low (or high-z) after power up,
which holds the switch in reset. Deassert the signal at startup on
hardware rev 1 and later.
BUG=chrome-os-partner:31780
TEST=with this patch applied, when proto0.2 boots, the ethernet
switch's LED blink once, as was the case with proto0.
Change-Id: I81b3dccb1d1d43c5c1e6dcb5400af8eed6dee870
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217087
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This memory is also x16 and needs slight tweak to tRFCmin
in order to be functional.
BUG=chrome-os-partner:31833
BRANCH=None
TEST=build and boot on EVT unit with this config
Change-Id: I01163ee7e70f08ccad84a3da39f1aac96e4c4771
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217190
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Nvidia tracks their MTS versions using decimals. Update
the format so there isn't an extra step in communicating
versions while debugging things.
BUG=chrome-os-partner:31864
BRANCH=None
TEST=Booted and confirmed decimal print out.
Change-Id: Ia7d0bc49318a4b4c969ee37e762e084ec65de543
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217260
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Figuring out board_id on storm requires reading tertiary gpios, which
takes time. Let's calculate it once and reuse it when necessary.
BUG=none
TEST=verified board ID reported as 0 and 1 on proto0 and proto0.2
respectively.
Change-Id: I4e237077d1d9a96daebba462cd00f3f40be14518
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217086
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Now that there is cpu devicetree support retire the
bring_up_secondary_cpu option as the devicetree is the
way going forward to do other CPU bring up.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and booted with 2nd core.
Change-Id: Ic213fbf56a1846e73462886f876a0a70e48b3158
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216929
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Now that arm64 and tegra132 has cpu devicetree support stop
using the bring_up_secondary_cpu option.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and brought up 2nd core.
Change-Id: I210bea73f8249de15f99d0c062600e789184eefd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216928
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Since coreboot is a third-party project, we use standard copyright
headers instead of the ChromiumOS version which refers to a LICENSE
file we don't have.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6caf0268ab0dd7d1734d4ee98c1321607d2bd66a
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216478
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
revert this change will cause auron show ERROR
CBFS: ERROR: No file header found at 0x7ff480
and need to add skip ERROR while running suspend_stress_test
But we need to support diff CPU sku, so I revert this change
This reverts commit 5e11145fb3.
BUG=none
TEST=build ok, boot to OS
Change-Id: I29da779f9e0d9a3a8bae46c49250c769a18d0c10
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/216810
Reviewed-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
The original purpose of soc_secondary_cpu_init() was to provide
a way for the SoC to run code on the secondary processors as
they come up. Now that devicetree based bringup is supported
there's no need to have this functionality.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Booted SMP into linux.
Change-Id: Ie5c38ef33efadb2d6fdb2f892b4d08f33eee5c42
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216927
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Use the formal devicetree way for bringing up each of
the cpus. This includes providing a cpu_driver as well
as calling arch_initialize_cpus() with the proper
operations to start the cores.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Booted SMP on ryu.
Change-Id: I13d8bfd645abf66f270d56d48eff4331c4ea1200
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216926
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This adds SMP bring up support for arm64 cpus. It's
reliant on DEVICE_PATH_CPU devices in the devicetree.
Then for each enabled device it attempts to start then
initialize each CPU. Additionally, there is a cpu_action
construct which allows for running actions on an individual
cpu.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Booted both cores on ryu into linux.
Change-Id: I407eabd0b6985fc4e86de57a9e034548ec8f3d81
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216925
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Add a cpu-internal.h for internal prototypes to the
architecture specific code.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and booted.
Change-Id: I8ab520478954a3b43e8e0831d1883f9a791850aa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216924
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Provide a simple spinlock implentation for arm64. A value
of 0 is unlocked and a value of 1 is locked.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and ran SMP bringup on ryu.
Change-Id: I3bf2d80b91112d04442455ff0fa3f16900b7327f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216923
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The spinlock header file was not residing in the correct place.
It needs to live under 'arch/smp'.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built with SMP. spinlock.h found.
Change-Id: I0e594cacfafcd6f30802c9563785ca09a2f7a2af
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216922
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The load-acquire/store-release operations (including exclusive
variants) form a basis for atomic operations. Also remove
the dmb, dsb, and isb functions from lib_helpers as barrier.h
already included these. Lastly, utilize barrier.h.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and ran SMP bringup using barriers.
Change-Id: I77ff160c635297a2c7cab71cb0d3f49f2536f6ff
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216921
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
printk() shouldn't be called until the consoles have been
initialized. This just so happened to work by luck. Once
CONFIG_SMP is enabled that breaks because of spinlock
usage in uncached memory.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built with CONFIG_SMP and ramstage doesn't hang early.
Change-Id: I6091b1e949e648b3435231946e5924260bf1807f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216920
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
printk() shouldn't be called until the consoles have been
initialized. This just so happened to work by luck. Once
CONFIG_SMP is enabled that breaks because of spinlock
usage in uncached memory.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built with CONFIG_SMP and ramstage doesn't hang early.
Change-Id: I247caac410894fb896dfb25a27c3a3213ef7f020
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216429
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Add all the CPUs to the device tree.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Brought up 2nd core on ryu in kernel.
Change-Id: I682f23a9b68f49206aa99d55e800540d8d0f8900
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216426
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
In order to enumerate CPU devices that are non-x86 (read: no lapic)
provide a generic 'cpu' device.
Upstream patch: http://review.coreboot.org/#/c/6824/
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built a device tree with 'cpu' entries.
Change-Id: Ic3aa09970e5dd3d175048d698f74e2cce790dff0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216424
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
BUG=chrome-os-partner:31812
TEST=check if TS is found by the kernel
Change-Id: I22e6a9b65253bd17b639ce4d0742d1e7d3109e0c
Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216527
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
