Baytrail: changes to USB3 PLL VCO and iCLK PLL current on BYT-M/D CPU

Intel will be making slight changes to USB3 PLL VCO and iCLK PLL current
on C0 stepping of BYT-M/D C0 stepping in order to meet the high demands
for these processors.

Pre-conversion materials are compatible with USB PLL VCO current increase.
Post-conversion materials ARE REQUIRED to be run with increased USB3 PLL
VCO current.

BUG=chrome-os-partner:31199
TEST=Boot Rambi, then read USHPHY_CDN_PLL_CONTROL and verify register
has new value.

Change-Id: Ie9c3d0afd54ea7ced2c76ebb948de95be0828fa0
Signed-off-by: Kein Yuan <kein.yuan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/211337
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit df20eca47ca0ff33baf5d554ef11dd2b35706a5d)
Reviewed-on: https://chromium-review.googlesource.com/205970
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217772
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Kenji Chen <kenji.chen@intel.com>
Tested-by: Kenji Chen <kenji.chen@intel.com>
This commit is contained in:
Kein Yuan 2014-06-27 09:12:57 -07:00 committed by chrome-internal-fetch
commit bc01a3df80

View file

@ -27,6 +27,8 @@
#include <baytrail/iomap.h>
#include <baytrail/iosf.h>
#include <baytrail/lpc.h>
#include <baytrail/pattrs.h>
#include <baytrail/pci_devs.h>
#include <baytrail/pmc.h>
#include <baytrail/ramstage.h>
@ -227,6 +229,13 @@ static void xhci_init(device_t dev)
else
reg_script_run_on_dev(dev, xhci_init_boot_script);
/* C0 steppings change iCLK/USB PLL VCO settings from 5 to 7 */
if (pattrs_get()->stepping == STEP_C0) {
uint32_t reg = iosf_ushphy_read(USHPHY_CDN_PLL_CONTROL);
reg |= 0x00700000;
iosf_ushphy_write(USHPHY_CDN_PLL_CONTROL, reg);
}
/* Finalize Initialization */
reg_script_run_on_dev(dev, xhci_hc_init);