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broadwell: pcie update from BWG/RC code

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According to BIOS spec 8.14
B0:D28:F0[5:4] should be set to 11

BRANCH=none
BUG=chrome-os-partner:28234
TEST=build ok, boot to Auron and Samus
     make sure register is set and PCIE is working

Change-Id: I7c37245053ceae460dac0f18363f585244db72f8
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/217414
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Kane Chen 2014-09-09 15:53:09 -07:00 • committed by chrome-internal-fetch
commit 82826e3c44
1 changed files with 1 additions and 0 deletions
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src/soc/intel/broadwell/pcie.c
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@ -113,6 +113,7 @@ static void root_port_init_config(device_t dev)
rpc.pin_ownership = pci_read_config32(dev, 0x410);
root_port_config_update_gbe_port();
pcie_update_cfg8(dev, 0xe2, ~(3 << 4), (3 << 4));
if (dev->chip_info != NULL) {
config_t *config = dev->chip_info;
rpc.coalesce = config->pcie_port_coalesce;