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samus: Update SPD with correct geometry and timings

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This memory is also x16 and needs slight tweak to tRFCmin
in order to be functional.

BUG=chrome-os-partner:31833
BRANCH=None
TEST=build and boot on EVT unit with this config

Change-Id: I01163ee7e70f08ccad84a3da39f1aac96e4c4771
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217190
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2014-09-08 20:47:52 -07:00 • committed by chrome-internal-fetch
commit 6c4bf71c8c
1 changed files with 6 additions and 6 deletions
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12
src/mainboard/google/samus/spd/hynix_16Gb.spd.hex
View file

@ -1,15 +1,15 @@
# Hynix H9CNNNNCLTMLAR-NTM LPDDR3
# banks 8, ranks 2, rows 15, columns 11, density 16384 Mb, x32
91 20 F1 03 06 1A 05 0B 03 11 01 08 0A 00 50 01
78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
# Hynix H9CCNNNCLTMLAR LPDDR3
# banks 8, ranks 2, rows 15, columns 11, density 8192 Mb, x16
91 20 F1 03 05 1A 05 0A 03 11 01 08 0A 00 50 01
78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00
48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E
54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
48 39 43 43 4E 4E 4E 43 4C 54 4D 4C 41 52 00 00
00 00 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00