WWAN_FCPO == GPP_D6
WWAN_RST == GPP_E17
spec reuqest: 0 < toff <10ms
LTE is controlled by bits 14 and 15 in fw_config, and P sensor
and LTE modules exist at the same time, so we use the same bit
to control whether to load the driver.
BUG=b:419325064,b:417105553
TEST=Confirm the measured WWAN power sequence
Change-Id: Ia978aef2cc721b65618ac78c13930447d1557797
Signed-off-by: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87841
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no powering-on control in the fingerprint kernel driver.
Follow Rauru to power-on FP MCU in the FW.
BUG=b:401396071
BRANCH=none
TEST=ectool --name=cros_fp version can get the FP FW version.
Signed-off-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
Change-Id: I20ff175ee4874c4188b7d07ee57330a9275dcb3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
These variants were missing VBTs necessary for display init, so add
them. VBT files taken from the stock firmware images:
coreboot-Google_Moonbuggy.13324.803.0.bin
coreboot-Google_Scout.13324.645.0.bin
Since all variants now have VBTs, move the selection of
INTEL_GMA_HAVE_VBT to the baseboard.
TEST=build/boot various puff variants, including scout.
Change-Id: I2bb06894fc4df358cc38a4627de9f95289c2c5e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Ocelot does not support GEN5 NVME Storage. However since ocelot code
was forked from fatcat, these configs exist in coreboot.
Furthermore, the GEN4 NVME GPIOs have changed for ocelot -
1. GPP_B10 to GPP_H18 - GEN4_SSD_PWREN renamed to EN_PP3300_SSD
2. GPP_B09 to GPP_A08 - M2_GEN4_SSD_RESET_N renamed to SSD_PERST_L
BUG=b:419731962
Change-Id: I005d1188138ac7b4bbffa1437bba9aea39aff117
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87804
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Update gpio configuration for GPP_A08, GPP_E17, and GPP_F18 to
match ocelot schematic.
Change GPP_H16 (WWAN_PWR_EN) to GPP_E01 (EN_WWAN_PWR) in fw_config.c.
Change GPP_V06 and GPP_V11 to "No Connect" as they are test points.
Change trace names from "SNDW3_" to "SDW3_" to match names on ocelot
schematic.
BUG=b:412736286
BRANCH=None
TEST=`emerge-ocelot coreboot` and verify it compiles without error.
Change-Id: I8996dc1b2b0f85490d55a86dc2ca6a90c1604638
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87750
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently Francka cannot boot up immediately by pressing power button
when its power state is S5.
This patch fixes the power on process for this scenario.
BUG=b:419406610
BRANCH=none
TEST=Francka boots up immediately by pressing power button in S5.
Change-Id: I52fba7f58faa890955cd07728a6790520df29321
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87807
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This modification sets the HDA GPIO pin to NC by default.
Different audio configurations can be enabled via fw_config.
BUG=b:417133565
TEST=emerge-fatcat coreboot, HDA sound cards can be detected.
Change-Id: I0090a68d86de1067697d7efbb64c4638476c64ca
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87810
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set open-drain GPIOs for ChromeOS as input and bias-disable mode. Also
set AP_HDMI_RST_ODL to low, which is the only open-drain output pin.
BUG=b:397102113
BRANCH=none
TEST=build pass
Change-Id: I4375c25768de8f1462c491b2c84b9cf31f118126
Signed-off-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87796
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase the CPU little core frequency from 1.6 GHz to 2.0 GHz to
speed up the boot process.
BUG=b:379008996
BRANCH=none
TEST=check little core cpu frequency is 2GHz in kernel by commands
clkdbg() { echo $@ > /proc/clkdbg ; cat /proc/clkdbg ; }
clkdbg fmeter
See the little core CPU frequency:
fm_armpll_ll_ck : 1999968
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I979f44e9340ea5bd733dc7f0fe47af47a4f403b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87795
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIO_AP_SUSPEND_L is supposed to be high in S0, and low in S3. EC uses
this pin to determine the AP power state. This pin should be set as
early as possible in bootblock.
BUG=b:396030112
BRANCH=none
TEST=reboot pass. `powerinfo` shows S0 in EC console.
Change-Id: Ib7e9eaa19d232a37b3793bcbe268ba021e456ac7
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
SMI handler previously did not evaluate input slp_typ parameter and
apparently always acted as S3 was requested.
With the change keyboard is no longer a wakeup source from S4/S5, it is assumed MAINBOARD_EC_S5_WAKE attribute defined in ec.h is correct.
Change-Id: I54c7d7455a6737f731c65e57c91b6457643c7cb2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Extracted from coreboot-Google_Teliks.15217.734.0.bin
Change-Id: I2c6b00ab0fc67b651256ec32d4d983b987435010
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87557
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Extracted from coreboot-Google_Yaviks.15217.552.0.bin
TEST=build/boot yaviks/yavilla variant with working display.
Change-Id: I775baf4216eef2a60bc1ac034cef3c5c7c38ea69
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87556
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Extracted from coreboot-Google_Pujjo.15217.460.0.bin.
TEST=build/boot pujjo1e variant with working display.
Change-Id: I82425bdbbba93197fb7b6f7a866412dc49066cdf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
To have the best usage case on 4GBx32 memory sku, the external display
resolution must not exceed 2560x1700. So use the GPP_E13 signal level
to determine x32 memory configuration and apply the corresponding VBT
accordingly.
BUG=b:415850768
TEST=Check the log for the string "Use vbt-uldrenite_x32mem.bin"
Cq-Depend: chrome-internal:8258325
Change-Id: I82a7415b4c99de9278e04f07a9efb0dfa0bf753d
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87654
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These variants were missing VBTs necessary for display init, so add
them. VBT files taken from the stock firmware images:
coreboot-Google_Dood.11297.368.0.bin
coreboot-Google_Foob.11297-169.0.bin
Since all variants other than the baseboard have VBTs, move the
selection of INTEL_GMA_HAVE_VBT to the baseboard and exclude the
octopus board.
TEST=build/boot various ocotpus variants, including dood/foob.
Change-Id: I67655b149de40e3e7f83971780f62cd7fce820c8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87774
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Needed for coolstar's IOM/TCSS drivers under Windows.
TEST=build/boot Win11 on google/screebo
Change-Id: Ib5a288d9b5d259c27f3b3b2b1b7b86e9c0e1f491
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Update VBTs for both sarien and arcada variants from v221 to v228.
The current public CFL FSP uses/expects v228, and the older v221
causes a 180* rotation of the display at boot. Updating the VBT
to v228 fixes the issue. Also disable the fixed mode at boot
setting, so that the native panel resolution can be used by
the payload.
Settings were exported from the v221 VBTs using the Intel BMP tool,
and imported/applied to the sample VBT provided in the FSP repo.
TEST=build/boot google sarien w/edk2 payload, verify screen orientation
correct and native panel resolution used.
Change-Id: Ib6669fc535a197f961abdfcd10616c97a0573df2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87619
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Resolve the issue that DP can only display on one side.
BUG=b:416842915
BRANCH=none
TEST=Build and boot to pujjocento. Verify typec works.
Change-Id: I55f2f28a0bdb052cafa05a98f51c8483fb343b8c
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87757
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Per discussion in CB:87660, this is another approach to fix duplicate
ACPI device GFX0.
The following GFX ACPI device is already declared in nissa/devicetree
by CB:83071, it declare a ACPI gfx device as below:
device ref igpu on
register "panel_cfg" = "{
.up_delay_ms = 200,
.down_delay_ms = 50,
.cycle_delay_ms = 500,
.backlight_on_delay_ms = 1,
.backlight_off_delay_ms = 200,
.backlight_pwm_hz = 200,
}"
register "gfx" = "GMA_DEFAULT_PANEL(0)"
end
It will generate an ACPI \_SB.PCI0.GFX0 device.
However, some Nissa projects re-select DRIVERS_GFX_GENERIC in their
overridetree, which results in the generation of a second
\_SB.PCI0.GFX0. This duplication causes iasl to fail when disassembling
the SSDT table.
Error message from iasl:
File appears to be binary: found 7485 non-ASCII characters, disassembling
Binary file appears to be a valid ACPI table, disassembling
Input file SSDT, Length 0x4A03 (18947) bytes
ACPI: SSDT 0x0000000000000000 004A03 (v02 COREv4 COREBOOT 00000000 CORE 20230628)
Pass 1 parse of [SSDT]
Firmware Error (ACPI): Failure creating named object [\_SB.PCI0.GFX0._DOD], AE_ALREADY_EXISTS (20200925/dswload-387)
ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20200925/psobject-264)
Could not parse ACPI tables, AE_ALREADY_EXISTS
BUG=none
TEST=disassembling SSDT on pujjoniru successfully
Change-Id: I16e9875c12b4e8e42214da5972bed6a02c5567f4
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87745
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit introduces support for LP5 and DDR5 memory configurations
on ocelot. It adds board IDs for ocelot and integrates new memory
settings within the variant parameters. The new memory configuration
includes settings related to early command training and LP5/DDR5
specific training parameters.
LP5 memory configuration includes detailed DQ and DQS mapping for
different DDR channels. This facilitates accurate routing of signals
and initialization of memory. Additionally, SPD information retrieval
is adapted to accommodate DDR5-specific settings, such as DIMM module
topology and SMBus addresses.
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I828b1944d5a0d7f58aa8f545d567b1bb1b0da5ae
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87684
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Fn key on pujjocento emits a scancode of 94 (0x5e).
BUG=b:417141058
TEST=Flash Pujjocento, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: If8ad29fccbd7c088ee793f3261df0b0999f25765
Signed-off-by: lizheng <lizheng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
RTL8111 was occasionally not detected after reboot. This change
moves the configuration of the ISOLATE_ODL pin to high earlier
in the sequence to ensure the device is properly visible during
PCIe bus enumeration.
BUG=b:407469351
TEST=Verified that the Ethernet NIC is enumerated after reboot.
before:
[DEBUG] PCI: 00:1c.0 scanning...
[SPEW ] do_pci_scan_bridge for PCI: 00:1c.0
[DEBUG] PCI: pci_scan_bus for bus 01
[INFO ] PCI: Static device PCI: 01:00.0 not found, disabling it.
[DEBUG] GENERIC: 0.0 enabled
[WARN ] PCI: Leftover static devices:
[WARN ] PCI: 01:00.0
[WARN ] PCI: Check your devicetree.cb.
[DEBUG] scan_bus: bus PCI: 00:1c.0 finished in 34 msecs
after:
[DEBUG] PCI: 00:1c.0 scanning...
[SPEW ] do_pci_scan_bridge for PCI: 00:1c.0
[DEBUG] PCI: pci_scan_bus for bus 01
[SPEW ] PCI: 01:00.0 [10ec/0000] ops
[DEBUG] PCI: 01:00.0 [10ec/8168] enabled
[DEBUG] GENERIC: 0.0 enabled
[INFO ] Enabling Common Clock Configuration
[INFO ] L1 Sub-State supported from root port 28
[INFO ] L1 Sub-State Support = 0xf
[INFO ] CommonModeRestoreTime = 0x96
[INFO ] Power On Value = 0xf, Power On Scale = 0x1
[INFO ] ASPM: Enabled L1
[INFO ] PCIe: Max_Payload_Size adjusted to 128
[INFO ] PCI: 01:00.0: Enabled LTR
[INFO ] PCI: 01:00.0: Programmed LTR max latencies
[DEBUG] scan_bus: bus PCI: 00:1c.0 finished in 68 msecs
Change-Id: Idc0eb453c342828e0e8886ca5cacea8d7efcc437
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87734
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
The FW_CONFIG feature is not used on mc_rpl. Delete the related source
file and the reference to it in Makefile.
Change-Id: Ifec1efc239801205f1aec2095082c8f744f84a55
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Since this board comes with a fixed SoC (Raptor Lake with ADL-P PCH),
there is no need to have multiple different gpio configuration files and
devicetree files. This patch deletes the unneeded files and adopts
Makefile.mk to not use them.
Change-Id: Iced9d695e3f21dec260795bb651109ff9b2beb59
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This mainboard neither uses Chrome OS nor has any embedded controller
available. This patch removes all references from the build in this
regard. This also requires some refactoring in board_id.c.
Change-Id: If834480fbdac4b4843c265a257d3a77678f56aab
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87666
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename chromeos.fmd to mc_rpl.fmd and adjust the flash layout settings
to match the needs of this board. There is e.g. no A/B scheme used and
CSME stitching is done externally, therefore no detailed CSME partitions
are required at all.
Change-Id: I6389960d816c5f1a4690a965961301d3797305ff
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This patch adds a new mainboard called 'mc_rpl' which is based on the
Intel Alder Lake RVP. Only the needed changes are made in this patch in
order to make it compile with proper names. Follow-up patches will
tailor it more towards the real mainboard hardware.
Change-Id: Ic0caa621350848d459def6044ca0a6dfd88f873f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87664
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
update GPP_R4/GPP_R5 setting based on pujjocento proto schematic.
BUG=b:409752486
TEST=emerge-nissa sys-boot/coreboot sys-boot/chromeos-bootimage
Change-Id: I5a2926a074e801162972d950c62002352fb5cf6e
Signed-off-by: Lei Cao <caolei6@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87756
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The E7240 actually has a 8MiB + 4MiB flash configuration, not 8MiB.
Change-Id: I14f0c8f6f0c0dfebf41294812b1f4e131eaa18d0
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit overrides the `logo_valignment` setting in the
`common_soc_config` for the Ocelot board variant, similar to
https://review.coreboot.org/c/coreboot/+/87453.
The vertical alignment for the firmware splash screen logo is now set to
`FW_SPLASH_VALIGNMENT_MIDDLE`, which places the top edge of the logo at
the vertical midpoint of the screen.
Change-Id: I29f08d31d325304f7532ed37f9cf3d5ef0bb88ff
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit removes the `device ref npk on end` from the
`overridetree.cb` files for ocelot, similar to -
commit 85c65b0c20 (mb/google/fatcat: Remove NPK device from fatcat and francka variants)
This effectively disables the NPK device for these configurations
(because `npk` is default set to disable).
Change-Id: Iee1509f44f6543c23f9633ccd8d35d4a7e37b89e
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87753
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
