Increase size of SMMSTORE FMAP region to 512KB to ensure a large
enough area is allocated to UEFI variable storage which allows for
variables (such as the UEFI revocation database) to be updated
via fwupd. Previously, such updates would fail with an error such as:
"efivar: No space left on device".
Change-Id: I1ef876de4ccb3a0ed2ff0a96b66c6b02bf274a3e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Increase size of SMMSTORE FMAP region to 512KB to ensure a large
enough area is allocated to UEFI variable storage which allows for
variables (such as the UEFI revocation database) to be updated
via fwupd. Previously, such updates would fail with an error such as:
"efivar: No space left on device".
Change-Id: Ia7566b31991b6891b4c194ad9b494da2e5ea8e01
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90290
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Increase size of SMMSTORE FMAP region to 512KB to ensure a large
enough area is allocated to UEFI variable storage which allows for
variables (such as the UEFI revocation database) to be updated
via fwupd. Previously, such updates would fail with an error such as:
"efivar: No space left on device".
Change-Id: I4073f7d1aed589544f072c2a64cada2cdddbe8bf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The previous default size of 256KB provided for only 64KB of actual
space for EFI variables, and after accounting for fragmentation, did
not provide enough free space for applying updates, such as for the
UEFI revocation database (DBX). Increasing it to 512KB allows for
192KB space for variables, and allows the UEFI DBX to be updated
properly via fwupd.
TEST=build/boot google/drobit, verify UEFI DBX able to be successfully
updated via fwupd.
Change-Id: I8d6a2051f3ad50117d41cec2bbbe3aaafa7e65c2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90287
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
sysinfo contains both CBMEM_ID_MEMINFO and CBMEM_ID_MEM_CHIP.
This new function allows to easily retrieve the amount of memory the
system has based on the mentioned CBMEM entries structures.
BUG=b:450374306
TEST=Checked on Google/Brya/Omnigul (x86) - MEMINFO
TEST=Checked on Google/Rauru/Navi (ARM64) - MEM_CHIP
Change-Id: Iaf69c54dfb3d2eaffbccacee8bee3be425b78a3f
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90430
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For FVM, the function should be enable and set VR Fast Vmode ICC Limit
in BIOS.
According to VRTT test result by PWM IC vendor tuning.
VCCCORE VR Fast Vmode ICC Limit can set as 74A.
VCCGT VR Fast Vmode ICC Limit can set as 38A.
VCCSA VR Fast Vmode ICC Limit can set as 38A.
BUG=b:464422702
TEST=Build and check the system could boot to OS
Change-Id: Ia9dffbfde8d57044392b742d68c62398d6f3dfa3
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Correct "APCI" to "ACPI" in the UI help text.
Change-Id: I56343c82b2ddc73e565501f723538fbe96877cd6
Signed-off-by: Integral <integral@member.fsf.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90431
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We've accumulated a number of endianness-handling and related macros
that are duplicated between coreboot and libpayload. This patch reduces
duplication by merging them into a commonlib header. This has the added
side-benefit of bringing the coreboot implementation of beXXenc/dec()
functions to libpayload, which lead to better code generation by
avoiding https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92716.
Keep the htobell()-style functions in libpayload only since they're not
needed in coreboot and not preferred. Keep the cpu_to_beXX()-style
functions in coreboot only -- maybe we should deprecate those
eventually.
This patch is explicitly copying and relicensing some of the code I
originally added as GPLv2 in commit e8e92d60c4 ("endian.h: Add
be32dec/be32enc family of functions") to BSD-3.
Change-Id: I5eb83d44a98b3aa59bba65b8e22df668874d2668
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90308
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot produces SMBIOS tables with version 3.0.0. The UEFI payload
may overwrite this value based on PCDs and cause a mismatch of the
SMBIOS tables version produced by coreboot and version visible to OS.
To ensure proper parsing of SMBIOS tables in OS, set the same version
of SMBIOS for UEFI payload using the PCDs.
TEST=Run dmidecode on Gigabyte MZ33-AR1 and see that the tool reports
SMBIOS 3.0.0 present.
Change-Id: Ie3cdcca65dbcdddc74cb352ef5c4d3e83bdc87f5
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
TF-A feature additions have increased BL31 memory requirements. Expand
BL31 reservation from 600KB to 800KB and adjust the TA region start
address to prevent overlap. The TA region change requires FDT memory
reservation updates, which are handled in Depthcharge.This update
ensures proper memory alignment for secure firmware execution.
TEST=Created image.serial.bin and verified successful boot on X1P42100.
Basic device boot functionality with the updated memory reservation has
been validated.
Change-Id: Ia0145c9e8d5925de4a7fee3399efc76059944c10
Signed-off-by: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
AMD systems have a TOM2WB bit in SYS_CFG MSR to forcefully cover the
address space between 4GB-TOM2 as WB. Any WB MTRR that falls into that
range may be skipped from programming. It can save a lot of MTRRs when
calculating the MTRR solution. It is especially needed when using a
temporary MTRR to cover the flash as WP, as the MTRR space gets more
fragmented.
Add checks for SYS_CFG TOM2WB in the MTRR driver and skip the WB MTRR
ranges when possible.
TEST=Successfully enable temporary MTRR range for flash on Gigabyte
MZ33-AR1.
Change-Id: Ie9af9b54a1037c843d8f019506af761a8d8769d0
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89199
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
clock enablement
Add register address and clock value definitions required to enable
the display clock. The register details are part of HRD-X1P42100-S1
document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST=Generated image.serial.bin and verified boot on X1P42100.
Validated only basic device boot functionality, as clock enablement API
and its invocation sequence from display driver are not yet implemented.
Change-Id: Id23dd12c9c1ee4968546c8b928f9360163446a9d
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
send_global_reset() now returns cse_tx_rx_status, and skips the
CF9 reset only when CSE reports CSE_TX_RX_SUCCESS.
Test=Disable and enable the Intel ME on labtop_kbl and verify the
system actually resets, rather than hanging.
Change-Id: I5003ea9486a383ee7a4cace20ce6a54b0f94a166
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90274
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
cse_request_global_reset() returns CSE_TX_RX_SUCCESS on success. Make
do_global_reset() explicatly check for that, and fall back CF9 for any
other value.
Test=Disable and enable the Intel ME on starbook_mtl and verify the
system actually resets, rather than hanging.
Change-Id: I4c3fb7995bca8e7fe3793b9aee021e4004ace933
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Currently, cse_request_reset() returns 0 if the reset type is
unsupported or CSE isn’t ready. This is the same as
CSE_TX_RX_SUCCESS, which makes failures impossible to detect.
Return CSE_TX_ERR_INPUT or CSE_TX_ERR_CSE_NOT_READY respectively,
so we can detect errors.
Change-Id: Idede7342157901946ba62ba6fcda6f304a4a3fd0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90272
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The MP Specification v1.4 says to program the spurious interrupt
in the following way:
"The APIC spurious interrupt must point to a vector whose lower
nibble is 0F, that is 0xF, where x is 0 - F. Here we use Int 00FH,
which handles spurious interrupts and supplies the necessary IRET.
This vector is assumed to have already been initialized in memory."
Follow the requirement and set the spurious interrupt vector
to 0x0F. This is what reference implementations, like EDK2, and also
BIOS vendors do.
Change-Id: I7bde413bbadca1de0079daf52b5501ba6638a4c3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Halfway through the review of CB:89493 (commit 6e45016610 ("intel
soc,southbridge: Add Kconfig to set TSBS in IFD during build")) the
option was renamed and lost "CONFIG_" prefix in the Makefile. Add the
missing prefix.
The omission was discovered and the fix tested while trying to use this
option on Protectli VP6670 where incorrect Top Swap size prevented a
boot.
Adding a missing space while at it.
Change-Id: Ie85fc0b81b2231760878306cf065598bec390e9f
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90432
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Unlike other skywalker boards, GPIO14 is EN_PP6000_MIPI_DISP instead of
TCHSCR_REPORT_DISABLE on Padme. Therefore, in bootblock that GPIO should
be initialized low to meet the MIPI panel's required power-on sequence.
More precisely, IOVCC (LCD_VDDI) must lead AVDD by >2ms [1].
Add alias GPIO_EN_PP6000_MIPI_DISP to skywalker/gpio.h, and use it
instead of GPIO_TCHSCR_REPORT_DISABLE in the MIPI initialization code.
Also remove the EN_PP6000_MIPI_DISP pull-low in mipi_panel_power_on(),
as it has been pulled low in setup_chromeos_gpios().
[1] Preliminary+specification+TL121BVMS07+-00+V01+20250721.pdf
BUG=b:451746079
TEST=Boot Padme and confirm panel power-on timing is correct.
BRANCH=skywalker
Change-Id: I748a998cde35e58eac9eb590171b79864fc58ea9
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This change introduces support for variant-specific firmware
configurations (fw_config) for the Rauru mainboard, specifically adding
initial support for the Sapphire variant.
The fw_config fields for Sapphire are defined in b:458266555.
All fw_config fields are now defined in variant-specific overridetree.cb
files (hylia, navi, rauru, sapphire). Consequently, access to these
fw_config values has been refactored to be encapsulated within
variant-specific fw_config.c files. This approach ensures that common
mainboard code does not need direct knowledge of variant-specific
fw_config definitions.
This is demonstrated by the audio amplifier initialization, which
now uses a variant-specific get_audio_amp_id() function to determine
the hardware present, rather than directly probing fw_config in the
common code.
BRANCH=None
BUG=b:458266555, b:448281461, b:461594346
TEST=emerge-tanjiro coreboot && emerge-rauru coreboot && test on navi
Change-Id: Iecca5820421f250e1a22cec110b36fb578edd9e7
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90330
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Unify the I2C pad termination on all mc_ehl boards for better code
readability and continuity in the devicetrees. This patch does not
change the actual I2C pad termination configuration.
All the mc_ehl boards use external resistors for I2C termination.
Therefore, there is no need for internal termination at all. If the FSP
parameter 'SerialIoI2cPadsTermination' is omitted from the device tree,
the generic GPIO settings can define termination. If
'SerialIoI2cPadsTermination' is specified for an inactive I2C
controller, those settings are ignored.
This patch consistently adds 'SerialIoI2cPadsTermination' to the device
tree for all active mc_ehl boards, and removes it for controllers that
are switched off.
This topic came up in review for commit 864e3ca661
("mb/siemens/mc_ehl6: Adjust I2C setup").
TEST=Build and boot to OS on mc_ehl1/2/4 and compare register contents
of PAD_CFG_DW0/1 registers for all 8 I2C controllers before and after
the patch to ensure no change in I2C pad termination.
Change-Id: Iba75778893e0b6a7acb68535d0407dc1fc43d2ca
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Generate RAM ID for MT62F512M32D1DS-023 WT:E
DRAM Part Name ID to assign
MT62F1G32D2DS-031RF WT:C 4 (0100)
BUG=b:466889567
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I6a6ed45cacc9a10bc7a2cfc3b41cee93c552a6cd
Signed-off-by: Wayby Zhai <wayby.zhai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90411
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the bit definition for RGS_AUX_LDO_EN_READY_MASK in the MT8189
dptx_reg.h file, changing it from BIT(2) to BIT(0). The MT8189 is only
polling BIT(0) status instead of BIT(2). This correction ensures proper
functionality of the AUX LDO readiness check.
BUG=b:461384417
TEST=Boot up can see develop mode.
BRANCH=skywalker
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Change-Id: Id4a85c619311fecde5bc84ad29c521b7d20ffdd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90362
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current code doesn't make much sense. The offset created by the
skipping of NOP tokens is just ignored.
Reorder the lines to skip the NOP tokens first.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I860a57e4a773b634149e84271b8322d78ac20e32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The option was introduced by
commit ae738acdc5 ("cpu/x86: Support CPUs without rdmsr/wrmsr")
for the intel quark SOC. However the SOC doesn't exist anymore in
coreboot. Nor does any other SOC use this option.
Therefore remove it.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I4f3f5e91c00784c159042271387c2e862f351881
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90421
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use is_dev_enabled() on devicetree device to enable/disable USB4 devices
by updating the corresponding FSP UPDs.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: If0ae88eaaf88954159b55fdf030eb96d74ee29f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Glinda and Faegan are closely related and there's only very minimal
difference from the coreboot viewpoint, so Feagan is added as Glianda
variant and not as a new SoC folder. Faegan has a different CPUID, so
it's added to the CPU table, and some GPIO muxes have a few more valid
settings to route the MDIO pins related to the 2 XGBE controllers to
GPIO pins.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I57699089a4a3ac7ddb037f254d42cb043b816c55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90417
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some specific Glinda SoCs support dual 10G PCI ethernet devices.
Add defines and chipset entries for XGBE0 and XGBE1.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7e3bb1819165a7c2f4284b76450f831bb99b1ad3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90416
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Glinda actually supports warm reset, so we don't need to toggle the
PwrGood for all resets.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I70e9a13b84219847795e65b39c52114592a2cb61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90415
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fill in the DIMM voltages as reported by FSP.
Change-Id: I22d6bac93d8e8b8130f89a440be661829c700fe9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There is ESPI1 fixed resource living 64K above the ESPI0 fixed
resource. Report it if the hardware has ESPI1 bus.
Change-Id: I7245850450cfa9de326f26c83c4f01c8d167f8be
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
On systems with AMD ROM armor enabled the SPI base address register
in LPC bridge PCI device space is not accessible (returns all FFs).
In such case the AML code will not be able to retrieve the SPI BAR
and report it properly. Use fixed bases instead to avoid running
into this problem in the future.
Change-Id: Ia01508e5ddf2da053f9bf4116c5e05b89500f772
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89488
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the dsc_config parameter to mtk_ddp_soc_mode_set to support DSC
configuration, and updated function calls to pass dsc_config from
panel_serializable_data. The MIPI_DSI_DUAL_CHANNEL flag is set when the
panel uses the dual MIPI path. This patch is prepared for upcoming MIPI
DSI and DSC changes.
BUG=b:424782827
TEST=Build pass.
Change-Id: Ia3ada4aca41a231adb2273c34deef636889c5c81
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90377
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Refactor the MIPI DPHY implementation to improve modularity and
maintainability:
- Extract the dphy timing calculation to mtk_mipi_dphy_v1.c.
- Update Makefiles for multiple chips to include the new file.
- Enhance board-specific tuning by isolating timing configuration logic.
BUG=b:424782827
TEST=Build pass, boot ok, display ok
Change-Id: Ie0daa6e7b384a172ed483eda926e5acd1e3c539a
Signed-off-by: Payne Lin <payne.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90358
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable Unified Firmware and Secondary Source Configuration (UFSC)
support for Matsu.
UFSC standardizes the bitfields and bitmap definitions for firmware
configuration. Update overridetree.cb with new UFSC definitions and
enable EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC.
BUG=b:454549696,b:444322626
TEST=Ensure the probed fw_config matches the written configuration.
BRANCH=none
Change-Id: I55e2b9fd17290731f365632d92f1b26923c8022a
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90299
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SSDT contains:
CreateByteField (PPOP, Local0, TPPF)
However, CreateByteField requires the source argument to be
(Buffer | String | Integer). PPOP is an OperationRegion, so
iasl correctly reports:
Error 6058 - Invalid type ([Region] found)
Per ACPI spec, OperationRegions must use CreateField rather than
CreateByteField. Replace the AML emission with:
CreateField (PPOP, Local0 * 8, 8, TPPF)
This reads one byte at an arbitrary offset inside the PPI
OpRegion and is fully standards-compliant. This isn't a
functional change, just "correct".
Test=boot starbook_mtl, verify iasl can decompile and recompile
SSDT and TPM is still operational.
Change-Id: If80bb5bf69562f8b904c1b315e95a0b5627efbc4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Based on the Unified Firmware and Second Source Configuration(UFSC)
Developer's Guide to generate the UFSC firmware config file
ruby_ap_fw_config.cb and copy the content to overridetree.cb.
https://chromium.googlesource.com/chromiumos/config/+/refs/heads/main/
util/ufsc/ufsc_developer_guide.md
BUG=b:460231264
TEST=util/abuild/abuild -x -t GOOGLE_RUBY -a
BRANCH=none
Change-Id: Ia9536ba9b11ca83e80e7e6b3042a04fc6cdbf526
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90375
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables Cirrus Audio codec and HDA in devicetree for ojal
and updates FW config for GPIO's according to schematics revision 0.9.
RDC kit no:840138
Scope (\_SB.PCI0.HDAS.SNDW)
{
Device (SW30)
{
Name (_ADR, 0x00033001FA424301) // _ADR: Address
Name (_DDN, "Headset Codec") // _DDN: DOS Device Name
Name (_SUB, "1337") // _SUB: Subsystem ID
...
BUG=b:437459757
TEST=Build ojal board and check SSDT tables for codec.
Change-Id: Id4110263750ef5ff2375199d073175b47dc4f909
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bhat D, Krishna P <krishna.p.bhat.d@intel.com>
Modify ocicat TPM_TIS_ACPI_INTERRUPT to fix TPM timeout
BUG=b:457879750
TEST=flash and boot to DUT, verify can boot to OS.
Change-Id: Ie6f35c8c68b8e5849a038124739f9ec4846f4aef
Signed-off-by: lai.kaiden <lai.kaiden@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90359
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds wake functionality to the CNVi Bluetooth device by
registering to "GPE0_PME_B0" using the common CNVi block.
BUG=454341255
TEST=Able to wake up the device from a low power state using a keyboard
Bluetooth device.
Change-Id: I5a0bbd0523611e8e38b62f8b3fdf77f736d3136f
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90379
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Upadhyay, Varun <varun.upadhyay@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Running FWTS detected a problem with FACS having non-zero
values in reserved fields:
FAILED [MEDIUM] FACSReservedNonZero: Test 1, FACS Reserved field must be zero,
got 0x00fe7bcd instead
FAILED [HIGH] FACSReservedBitsNonZero: Test 1, FACS OSPM Flags Bits [31..1] must
be zero, got 0xf23bcdd8 instead
FAILED [LOW] FACSInvalidReserved1: Test 1, FACS: 2nd Reserved field is non-zero
Clear whole FACS table and then start filling the non-zero values to
fix the issue.
TEST=Run FWTS V25.01.00 on Gigabyte MZ33-AR1 and see no error for FACS
test.
Change-Id: I2af4caea155e3707e3b7832824e81e6b69f836a5
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89923
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change below GPIO pins status to fix audio function.
GPP_D10 : Native function 2
GPP_D11 : Native function 2
GPP_D12 : Native function 2
GPP_D13 : Native function 2
BUG=b:466263099
TEST=Build and boot to OS, check soundcard shows using command
'cat /proc/asound/cards' and check audio jack and amp are work.
Change-Id: Ieac732ebf5149a13fe7aba36bf14627ded4783ad
Signed-off-by: luca.lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90394
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This update enhances the Intel touch driver by incorporating support for
newly added _DSD entries specific to I2C devices. The enhancements
include:
- Adding new entries in the I2C _DSD to enable configurations for
maximum frame size and interrupt delay settings.
- Introducing device-specific interrupt delay settings tailored for
Hynitron devices.
These changes ensure improved configurability and performance tuning for
supported devices. It is crucial to use this update with an operating
system that includes corresponding changes for this new support.
ATTENTION: This change requires a THC driver fix. If the OS does not
have the driver fix, please use LPSS I2C or disable the touchscreen
and touchpad. For instance, on the Google Fatcat board, use the
following CBI fw_config options:
TOUCHSCREEN field: TOUCHSCREEN_LPSS_I2C or TOUCHSCREEN_NONE
TOUCHPAD field: TOUCHPAD_LPSS_I2C or TOUCHPAD_NONE
BUG=none
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Iaab8329c97247161395d203a5efa92c053acb3a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89214
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kim, Kyoung Il <kyoung.il.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
