If these aren't set, the rom and ram stages will attempt to load at address
zero which doesn't work.
BUG=None
TEST=Built and booted into the bootblock on nyan. Verified that the rom and
ram stages had valid starting addresses.
BRANCH=None
Change-Id: I0b9b37d6363e6b208248d8a1af6ebee4db602486
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/173540
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
This adds a basic SPI driver for reading SPI flash content. It uses
the DMA engine, albeit in a sub-optimal manner for now with the
intention of future optimizations to shave a few dozen milliseconds
off boot time.
BUG=none
BRANCH=none
TEST=read SPI flash on Nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ic68348add093f014a6b3f08ace5719de035629be
Reviewed-on: https://chromium-review.googlesource.com/172952
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
This adds basic DMA support. The actual code in this patch does very
little since DMA transfers are pretty well intertwined with the
module's usage. Perhaps in the future we'll add some helper functions
so module code doesn't modify the DMA registers directly...
BUG=none
BRANCH=none
TEST=Successfully used DMA to transmit data over SPI
Change-Id: I3a76ec8350a71e24aac920beaf52b499fef271ec
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172951
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
The clock constants were not consistently named and not consistently
commented. There were also structures which didn't really fit the registers
they were overlaid on, or don't really go together. This change straightens
out these problems, and also consolidate writes to the reset and enable
registers.
BUG=None
TEST=Built and booted into the bootblock on nyan. Verified that we can still
start up the main CPU and run code on it.
BRANCH=None
Change-Id: I21961caebc0c556da9a939649093e23246dc98fe
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172954
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This updates the APB addresses for the SPI controller and gets rid of
the obsolete SLINK nomenclature.
BUG=none
BRANCH=none
TEST=tested in upcoming Tegra124 SPI driver patches
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I6e7507518eb0531af8bf7865d6e31a8c22283c3d
Reviewed-on: https://chromium-review.googlesource.com/173322
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
The currently used Bay Trail devices comply with eMMC 4.51
specification and as such require the appropriate GPIOs to be
configured for func3.
Note that the CMD line termination requires 2K, otherwise when driven
by the eMMC device the front slope of the pulse in unacceptably
gentle.
BUG=chrome-os-partner:22580
TEST=manual
. with u-boot SDHCI driver implemented, the eMMC device on the
Bayley Bay CRB can be initialized and mounted
Change-Id: Ib53b6e42d8558c9ca2dff4b6bbf3bcf6fd22e136
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173241
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
The ram_id[2:0] signals have stuffing options for pull up/down
with values of 10K. However, the default pulldown values for these
pads are 20K. Therefore, one can't read a high value because of
the high voltage threshold is 0.65 * Vref. Therefore the high
signals are marginal at best.
Fix this issue by disabling the internal pull for the pads connected
to ram_id[2:0].
BUG=chrome-os-partner:23350
BRANCH=None
TEST=Built and checked that ram_id[2:0] is properly read now.
Change-Id: Ib414d5798b472574337d1b71b87a4cf92f40c762
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173211
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
The original documentation was incorrect. Fix the pci
device for the MMC port to reflect reality.
MMC is at 00:17.0 with a device id of 0x0f50.
BUG=None
BRANCH=None
TEST=Built.
Change-Id: Ic18665b7dda5f386e72d1a5255e4e57d5b631eb0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172772
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Despite some references to a fixed bclk in some of the
docs the bclk is variable per sku. Therefore, perform
the calculation according to the BSEL_CR_OVERCLOCK_CONTROL
msr which provides the bclk for the cpu cores in Bay Trail.
BUG=chrome-os-partner:23166
BRANCH=None
TEST=Built and booted B3. correctly says: clocks_per_usec: 2133
Change-Id: I55da45d42e7672fdb3b821c8aed7340a6f73dd08
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172771
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
After running the MRC blob print out some information
on the training: MRC version, number channels, DDR3
type, and DRAM frequency.
Example output:
MRC v0.90
2 channels of DDR3 @ 1066MHz
Apparently there are two dunit IOSF ports -- 1 for each
channel. However, certain registers really on live in
channel 0. Thus, there was some changes to dunit support
in the iosf area.
BUG=chrome-os-partner:22875
BRANCH=None
TEST=Built and booted bayleybay in different configs.
Change-Id: Ib306432b55f9222b4eb3d14b2467bc0e7617e24f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172770
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
If a payload is compiled to use SSE instructions it will
fault with an undefined opcode because SSE instructions weren't
enabled. Therefore enable SSE instructions at runtime.
BUG=chrome-os-partner:22991
BRANCH=None
TEST=Built and booted with SSE enabled payload. No exceptions seen.
Change-Id: I919c1ad319c6ce8befec5b4b1fd8c6343d51ccc1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172642
Reviewed-by: Stefan Reinauer <reinauer@google.com>
These configs were previously living in the private
repo. There's no reason to live in there. Therefore,
bring in those configs to simplify config changes in
a single CL. Lastly, select CONFIG_VBOOT_VERIFY_FIRMWARE=y
for both bayleybay and rambi.
If wanting to bypass talking to a TPM build with
MOCK_TPM=1.
BUG=chrome-os-partner:23249
BRANCH=None
TEST=Built and booted on bayley bay.
CQ-DEPEND=CL:*146399
CQ-DEPEND=CL:*146436
Change-Id: Ic8bac07ec05541edf0c7b3f8f140cd7daae99a68
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172713
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Add suport for verifying the ramstage with vboot
during romstage execution. Along with this support
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to
cache the relocated ramstage 1MiB below the
top end of the TSEG region.
BUG=chrome-os-partner:23249
BRANCH=None
TEST=Built and booted with CONFIG_VBOOT_VERIFY_FIRMWARE=y
selected.
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I355f62469bdcca62b0a4468100effab0342dc8fc
Reviewed-on: https://chromium-review.googlesource.com/172712
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
In the case of CONFIG_VBOOT_VERIFY_FIRMWARE not being
selected allow for calling vboot_verify_firmware()
with an empty implementation. This allows for one not to
clutter the source with ifdefs.
BUG=chrome-os-partner:23249
BRANCH=None
TEST=Built with a !CONFIG_VBOOT_VERIFY_FIRMWARE and non-guarded
call to vboot_verify_firmware().
Change-Id: I72af717ede3c5d1db2a1f8e586fefcca82b191d5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172711
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Bay Trail has the following types of resets it supports:
- Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92
- Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9
- Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9
- Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9
- Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to
0xcf9 but with ETR[20] set.
While these are documented this support currently provides support
for 2nd soft reset as well as cold and warm reset.
BUG=chrome-os-partner:23249
BRANCH=None
TEST=Built and booted.
Change-Id: I9746e7c8aed0ffc29e7afa137798e38c5da9c888
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172710
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
While trying to make the The I2C constants unambiguous, I also made their
names very verbose. This CL reigns them in a bit and also consolidates _SHIFT
and _MASK constants for bit fields which have only one bit. A value with a one
in the right place can be used to test the field or set it to any of its legal
values.
BUG=None
TEST=Built and booted into the bootblock on nyan. Used test code to verify
that the main CPUs still start correctly.
BRANCH=None
Change-Id: Ia9a3da2d36e4f71ad8380c7d6efacb0c471eb522
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172953
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This will allow us to run the ROM stage on the main CPU0 instead of the AVP
coprocessor. In addition, this CL also fixes some problems in the clock init
function, and replaces the definition of the PMC register layout structure. I
originally implemented this new version by accident without realizing the
original existed, but since it's a bit more up to date we decided to use it
instead.
The procedure for bringing up the main CPUs happens in four broad phases.
1. Enable the external power for the CPU rail by talking to the PMIC over I2C.
2. Enable the internal power rail for the CPUs.
3. Un-gate power for the CPUs and associated bits and pieces.
4. Enable the CPU clocks and take CPU0 out of reset.
The reset address is stored in an memory location with the magical property
that the CPUs will use whatever address when they reset. No explanation is
given in the documentation why this location behaves that way, what other
values near it might do, etc., so we have to just follow the example of the
kernel and U-Boot and treat it the same way.
Some code still needs to be written which will call into the flow controller
and get it to shut down the AVP so that it isn't sitting there consuming power
while execution has moved on to the main CPU. In the mean time, the current
implementation is sufficient.
BUG=None
TEST=Built and booted into the bootblock on nyan. Wrote a small test function
which sets the stack pointer to an array allocated as a new stack and then
prints a hello world type message. Used that function and some code in earlier
parts of the bootblock to print the uP-Tag at address 0x60000000 from the CPU
and the AVP and verified that they were 0x55555555 and 0xaaaaaaaa, indicating
that the test function actually was running on the main CPU and not on the
AVP.
Change-Id: I9728f43155074ab6948853eb26879656feb6b8c0
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172917
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This patch changes the GPIO API once again, this time back to functions.
It introduces a new opaque type gpio_t that holds both the GPIO number
and the corresponding pinmux number and can be constructed with a macro
(e.g. 'gpio_output(GPIO(Q2), 1);' ). This makes the GPIO functions
convenient to use, but also allows passing GPIOs around in variables and
function parameters.
BUG=None
TEST=Made sure GPIOs still twiddle when commanded.
Change-Id: I519c32b872b0c912046a3aaa070ef4e9699856ee
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172916
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Pull-ups and pull-downs can be active on functional pins. Add configs
for these options so they can be specified on board GPIO maps.
TEST=Manual on bayleybay. Verify that platform boots to payload load.
BUG=chrome-os-partner:22863
Change-Id: I0905dc94e4fcce87fd97be0e87c83aa5f2ae78b9
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172766
Reviewed-by: <adurbin@chromium.org>
Now that CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM is
an option the haswell boards need to be kept in line
to maintain their previous behavior. This commit
is separated from the actual implementation for
easier rebasing.
BUG=None
BRANCH=None
TEST=Built for falco.
CQ-DEPEND=CL:172602
Change-Id: Ic8b1c7f37ab4ac7b7d453e924c30f18a528f6eb6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172643
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Haswell was the original chipset to store the cache
in another area besides CBMEM. However, it was specific
to the implementation. Instead, provide a generic way
to obtain the location of the ramstage cache. This option
is selected using the CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
Kconfig option.
BUG=chrome-os-partner:23249
BRANCH=None
TEST=Built and booted with baytrail support. Also built for
falco successfully.
CQ-DEPEND=CL:172643
CQ-DEPEND=CL:*146397
CQ-DEPEND=CL:*146398
CQ-DEPEND=CL:*146435
CQ-DEPEND=CL:*146445
Change-Id: I70d0940f7a8f73640c92a75fd22588c2c234241b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172602
Reviewed-by: Stefan Reinauer <reinauer@google.com>
The GPIO wrappers are already pretty nice, but you still end up writing
everything twice since you need to specify the pinmux register:
gpio_output(GPIO_Q2, PINMUX_GPIO_Q2, 1);
Calculating the pinmux index from the GPIO isn't easy, but luckily the
enums use a similar naming scheme. This patch changes the wrapper
functions to macros that generate the corresponding pinmux name
automatically.
BUG=None
TEST=Made sure code with GPIO macros compiles, twiddled some output
GPIOs to confirm that they work.
Change-Id: Id23855c5aec5f87b4201f22bac32503e72f83392
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172731
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
This patch changes the order of GPIO and pinmux register accesses when
setting GPIOs to make the operations as atomic as possible, and avoid
output-to-output as well as special-function-to-input glitches under
some circumstances. It also sets the TRISTATE pinmux for input GPIOs,
since according to my understanding of the pinmux circuit this is the
right thing to do.
Also changed all uintXX_t types to uXX, since I think we agreed on
preferring that for all new code.
BUG=None
TEST=Twiddled some Servo-connected GPIOs and make sure they work.
Change-Id: I2e0156fbaa85e46e460b4494765a06e19f50d4e4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172730
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This will make the PCIe slots and the onboard network interface
work.
BUG=none
BRANCH=none
TEST=Use onboard network interface
Change-Id: Ia65a5e2443883da75b6fff60748d25189c91aa64
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172275
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
For graphics we need a chip.h in tegra124. Add it.
Set it in the nyan mainboard as a test.
BUG=None
TEST=build it
BRANCH=None
Change-Id: I1c5ccd5574d2e6b49bb4947035ccd10e99729458
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172773
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Add code which initializes the AS3722 PMIC based on the initialization
sequence U-Boot uses. I wasn't able to find documentation which said what each
register in the PMIC does, so the next best solution was to imitate another
implementation which presumably sets things up correctly.
The code is set up significantly differently than the U-Boot code, first
because it uses the i2c driver through it's external interface instead of
poking values into the controller's registers directly. The driver uses the
packet mode of the controller while the U-Boot code does not. Second, it uses
an array of register indices and values, a pattern established with Exynos,
instead of having a sequence of calls to the i2c_write function.
This change is also a practical test of the i2c driver's write capability.
BUG=None
TEST=Built and booted into the bootblock on nyan. Used a multimeter to measure
the voltage on capacitors connected to the CPU's power rail. When booting
U-Boot, the voltage across the capacitors is 1V. When booting coreboot before
this change, that rail stayed off and the rail stayed at 0V. After this change
it went to 1V.
BRANCH=None
Change-Id: Iab1f8d3b735b0737ce93ee3c9c7fdb2a1dcbbf8a
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172585
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Set up the i2c controllers that are used on nyan.
BUG=None
TEST=Built and booted into the bootblock on nyan.
BRANCH=None
Change-Id: Ibdd5685e3effdd13ca560b8f18db25e9edadc07b
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172584
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
There's generic clock initialization that needs to be done for any mainboard
using that soc. Other initialization depends on what peripherals are going to
be used and what rate they should run at and should be done in the mainboard
source.
BUG=None
TEST=Built and booted into the mainboard on nyan.
BRANCH=None
Change-Id: Idf79faac523bb99f3c7c29bac6947d2149fc3651
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172583
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
We need somewhere to put mainboard specific bootblock initialization.
BUG=None
TEST=Built and booted into the bootblock on nyan.
BRANCH=None
Change-Id: Ief409baff5ae67871879291c7ff0533f19ea6e56
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172582
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
We should seperate out the mainboard specific parts of the bootblock so that
they can be customized as necessary.
BUG=None
TEST=Built and booted into the bootblock on nyan.
BRANCH=None
Change-Id: Ia633a68521725f6e88341608ccdbedc4f1ce8223
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172581
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
This uses the packet mode of the controller since that allows transfering more
data at a time.
BUG=None
TEST=Used the i2c driver to read registers in the PMIC. I wasn't able to find
documentation which said what values to expect, but the values I got were
consistent, seemed reasonable, and tracked which register I was reading.
BRANCH=None
Change-Id: I8329e5f915123cb55464fc28f7df9f9037b0446d
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172402
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
I cleaned up the clk_rst struct: no need to have an array for the
source select because each thing is an individual entity.
There is a bit of a trick in here. I'm using macros to index arrays in the
clk_rst struct. Simple reason: if people use the constants we get compile-time
checking for simple errors.
init_pllx is fixed. The vendor table in u-boot was wrong.
BUG=None
TEST=builds. Amazing. Prints. Amazing.
BRANCH=None
Change-Id: I4429b3e5c14c200db6b4dd129eff14261fe1f326
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172106
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
We had brought this code in from the kernel but found it best to
use mainboard- or chipset specific versions. Firmware should
strive to be as non-generic as possible.
BUG=None
TEST=Builds and this code was not used anywhere
BRANCH=None
Change-Id: Ic1ca746cc52c3f9ea4de6895f2b32946229beada
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172625
Tested-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Fix USB2 and USB3 port configuration for Beltino
BUG=none
BRANCH=none
TEST=Boot system, see front USB ports working.
Change-Id: I7b799e2a2d17a89bde7dd93b4e9149f19ae4e7ac
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172274
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
The bootblock and romstage UART consoles were being built in based only on
whether or not the bootblock and romstage consoles were selected, ignoring
whether serial console support was compiled in generally.
BUG=None
TEST=Built for nyan with and without serial.
BRANCH=None
Change-Id: I3866519c422a990c44ced66885108eff24894563
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172580
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
In order to enable a SuperIO in non ChromeEC systems we
need to make pch_enable_lpc() available to the mainboard
romstage.c
BUG=none
BRANCH=none
TEST=boot ChromeOS on Beltino
Change-Id: I34e7d23012e1852c69e82ba7cdc81a05751846de
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172180
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
The access to control registers were scattered about.
Provide a single header file to provide the correct
access function and definitions.
BUG=chrome-os-partner:22991
BRANCH=None
TEST=Built and booted using this infrastructure. Also objdump'd the
assembly to ensure consistency (objdump -d -r -S | grep xmm).
Change-Id: Iff7a043e4e5ba930a6a77f968f1fcc14784214e9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172641
Reviewed-by: Stefan Reinauer <reinauer@google.com>
When compiling coreboot for x86 on gcc the compiler is
free to pick whatever defaults it is using at the time of
gcc's compile/configuration when no -march is specified.
Not properly specifying -march then opens up the use of SSE
instructions for copmilation units it should not be used such
as the SMM module as this module doesn't save/restore SSE
registers.
BUG=chrome-os-partner:22991
BRANCH=None
TEST=Built and confirmed -march=i686 was used on command line. Also
noted not xmm registers were produced grep'ing through objdump
output.
Change-Id: I64d4a6c5fa9fadb4b35bc7097458e992a094dcba
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172640
Reviewed-by: Stefan Reinauer <reinauer@google.com>
This is a direct copy of the bayleybay configuration.
BUG=chrome-os-partner:23121
TEST=emerge-rambi libpayload
Change-Id: Ib90f5797b4656ac366d16da5f3243fea20357dc5
Reviewed-on: https://chromium-review.googlesource.com/172587
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
This patch represents a major overhaul of the USB enumeration code in
order to make it cleaner and much more robust to weird or malicious
devices. The main improvement is that it correctly parses the USB
descriptors even if there are unknown descriptors interspersed within,
which is perfectly legal and in particular present on all SuperSpeed
devices (due to the SuperSpeed Endpoint Companion Descriptor).
In addition, it gets rid of the really whacky and special cased
get_descriptor() function, which would read every descriptor twice
whether it made sense or not. The new code makes the callers allocate
descriptor memory and only read stuff twice when it's really necessary
(i.e. the device and configuration descriptors).
Finally, it also moves some more responsibilities into the
controller-specific set_address() function in order to make sure things
are initialized at the same stage for all controllers. In the new model
it initializes the device entry (which zeroes the endpoint array), sets
up endpoint 0 (including MPS), sets the device address and finally
returns the whole usbdev_t structure with that address correctly set.
Note that this should make SuperSpeed devices work, but SuperSpeed hubs
are a wholly different story and would require a custom hub driver
(since the hub descriptor and port status formats are different for USB
3.0 ports, and the whole issue about the same hub showing up as two
different devices on two different ports might present additional
challenges). The stack currently just issues a warning and refuses to
initialize this part of the hub, which means that 3.0 devices connected
through a 3.0 hub may not work correctly.
BUG=chrome-os-partner:22139
TEST=Manual
Change-Id: Ie0b82dca23b7a750658ccc1a85f9daae5fbc20e1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170666
Reviewed-by: Kees Cook <keescook@chromium.org>
The current XHCI code only sets IOC on the last TRB of a TD, and
doesn't set ISP anywhere. On my Synopsys DesignWare3 controller, this
won't generate an event at all when we have a short transfer that is not
on the last TRB of a TD, resulting in event ring desync and everyone
having a bad time. However, just setting ISP on other TRBs doesn't
really make for a nice solution: we then need to do ugly special casing
to fish out the spurious second transfer event you get for short
packets, and we still need a way to figure out how many bytes were
transferred. Since the Short Packet transfer event only reports
untransferred bytes for the current TRB, we would have to manually walk
the rest of the unprocessed TRB chain and add up the bytes. Check out
U-Boot and the Linux kernel to see how complicated this looks in
practice.
Now what if we had a way to just tell the HC "I want an event at exactly
*this* point in the TD, I want it to have the right completion code for
the whole TD, and to contain the exact number of bytes written"? Enter
the Event Data TRB: this little gizmo really does pretty much exactly
what any sane XHCI driver would want, and I have no idea why it isn't
used more often. It solves both the short packet event generation and
counting the transferred bytes without requiring any special magic in
software.
BUG=chrome-os-partner:21969
TEST=Manual
Change-Id: Idab412d61edf30655ec69c80066bfffd80290403
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170980
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Kees Cook <keescook@chromium.org>
We had a hardcoded version of the set_avp_clock_to_clkm function in the
bootblock, and we had to use it until now because the real version uses
udelay, and until now that hadn't been implemented. Also, replace the delay
loop in the hacky_hardcoded_uart_setup_function with a call to the real thing.
BUG=None
TEST=Built and booted into the bootblock on nyan. Verified that there was
still serial output.
BRANCH=None
Change-Id: I6df9421bcad484e0855c67649683d474d78e4883
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172045
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
It turns out there's a register in tegra which automatically counts at 1us
increments. It's primarily intended for hardware to use (I think to drive
other timers) but we can read it ourselves since a 1us timer is exactly what
we need to support the monotonic timer API.
BUG=None
TEST=Built and booted into the bootblock on nyan with test code in the
bootblock. Used that code to print two serial messages, 1 minute apart. The
messages happened 1 minute and 2 seconds apart. That's pretty close, although
it might be worthwhile to figure out where those extra two seconds are coming
from (measurement error?).
BRANCH=None
Change-Id: I68e947944acec7b460e61f42dbb325643a9739e8
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172044
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The pins for the UART had been configured manually using hardcoded offsets and
values. Now that we have pinmux functions for that sort of thing, we should
use that instead. This also provides a very simple test for the pinmux code.
Ultimately this code should be wrapped in a function which handles setting up
any of the UARTs which is appropriately parameterized and which would be
called from the bootblock main instead of being in it, but for now this is
sufficient.
BUG=None
TEST=Built and booted into the bootblock on nyan. Saw console output.
BRANCH=None
Change-Id: I69e36fa5fc9b6f3f5ef7f1be3e9f18cdbfdd7fe9
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171807
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The pins on tegra are controlled by three different units, the pinmux, the
pin group controls, and the GPIO banks. Each of these units controls some
aspect of the pins, and they layer together and interact in interesting ways.
By default, the GPIOs are configured to pass through the special purpose IO
that the pinmux is configured to and so can be ignored unless a GPIO is needed.
The pinmux controls which special purpose signal passes through, along with
pull ups, downs, and whether the output is tristated. The pingroup controls
change the parameters of a group of pins which all have to do with a related
function unit.
The enum which holds constants related to the pinmux is relatively involved
and may not be entirely complete or correct due to slightly inconsistent,
incomplete, or missing docuemtnation related to the pinmux. Considerable
effort has been made to make it as accurate as possible. It includes a
constant which is the index into the pinmux control registers for that pin,
what each of the functions supported by that pin are, and which GPIO it
corresponds to. The GPIO constant is named after the GPIO and is the pinmux
register index for the pin for that GPIO. That way, when you need to turn on
a GPIO, you can use that constant along with the pinmux manipulating functions
to enable its tristate and pull up/down mode in addition to setting up the
GPIO controls.
Also, while in general I prefer not to use macros or the preprocessor when
writing C code, in this case the set of constants in the enums was too large
and cumbersome to manage without them. Since they're being used to construct
a table in a straightforward way, hopefully their negative aspects will be
minimized.
In addition to the low level functions in each driver, the GPIO code also
includes some high level functions to set up input or output GPIOs since that
will probably be a very common thing to want to do.
BUG=None
TEST=Replaced the hardcoded pinmux configuration code for the UART pins and
saw that the UART still worked correctly. Added an infinite loop to the
bootblock that read and print the value of the lid switch over and over. Ran
it and toggled the lid switch on servo and saw that the output changed as
expected. Repeated that with the dev switch GPIO.
BRANCH=None
Change-Id: I48efa58d1b5520c0367043cef76b6d3a7a18530d
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171806
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The exynos directories had been moved from src/cpu to src/soc, but the name
of the chip_operations structure wasn't updated properly. That meant that the
SOCs never installed their memory resources and the ram stage would fail to
load the payload.
BUG=None
TEST=Built and booted on pit. Before this change, the payload would fail to
load because no bounce buffer could be found. After this change, ChromeOS
booted successfully.
BRANCH=None
Change-Id: Ib60489b6d3434e3ebd13827a804452f762747f1b
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172400
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The flags used to compile libgcc may make it incompatible with the code it's
linked against, and/or the hardware it's going to run on. Rather than try to
tease the right libgcc from the compiler, lets just leave it out and use our
own implementations of the necessary functions.
Most of these implementations were taken from the Linux kernel, except for
uldivmod.S which was taken from a CL originally written for U-Boot by
Che-Liang Chiou in December of 2010. It was modified to not use the CLZ
instruction on machines that don't have it, anything earlier than ARMv5. The
top block was taken from an earlier version of the same CL which didn't use
CLZ in that spot. The later block was written from scratch.
BUG=None
TEST=Built and booted into the bootblock on nyan. Ran a series of tests which
divided and modded a 64 bit value by various 32 bit values which were powers
of 2. Confirmed that this function was used and that the returned value was
correct. Printed decimal and hex versions of some values and verified that
they equaled each other. Built and booted on pit with serial enabled.
BRANCH=None
Change-Id: I7527e28af411b7aa7f94579be95a6b352a91a224
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172401
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
