Read-only mirror of https://review.coreboot.org/coreboot.git. Synced every hour. We don't handle Pull Requests.
https://coreboot.org
- C 93.8%
- ASL 2.2%
- Makefile 1.1%
- C++ 0.5%
- Pawn 0.5%
- Other 1.8%
7c5169a197
This will allow us to run the ROM stage on the main CPU0 instead of the AVP coprocessor. In addition, this CL also fixes some problems in the clock init function, and replaces the definition of the PMC register layout structure. I originally implemented this new version by accident without realizing the original existed, but since it's a bit more up to date we decided to use it instead. The procedure for bringing up the main CPUs happens in four broad phases. 1. Enable the external power for the CPU rail by talking to the PMIC over I2C. 2. Enable the internal power rail for the CPUs. 3. Un-gate power for the CPUs and associated bits and pieces. 4. Enable the CPU clocks and take CPU0 out of reset. The reset address is stored in an memory location with the magical property that the CPUs will use whatever address when they reset. No explanation is given in the documentation why this location behaves that way, what other values near it might do, etc., so we have to just follow the example of the kernel and U-Boot and treat it the same way. Some code still needs to be written which will call into the flow controller and get it to shut down the AVP so that it isn't sitting there consuming power while execution has moved on to the main CPU. In the mean time, the current implementation is sufficient. BUG=None TEST=Built and booted into the bootblock on nyan. Wrote a small test function which sets the stack pointer to an array allocated as a new stack and then prints a hello world type message. Used that function and some code in earlier parts of the bootblock to print the uP-Tag at address 0x60000000 from the CPU and the AVP and verified that they were 0x55555555 and 0xaaaaaaaa, indicating that the test function actually was running on the main CPU and not on the AVP. Change-Id: I9728f43155074ab6948853eb26879656feb6b8c0 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172917 Reviewed-by: Julius Werner <jwerner@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> |
||
|---|---|---|
| 3rdparty@ba8caa30bd | ||
| configs | ||
| documentation | ||
| payloads | ||
| src | ||
| util | ||
| .gitignore | ||
| COPYING | ||
| Makefile | ||
| Makefile.inc | ||
| PRESUBMIT.cfg | ||
| README | ||
------------------------------------------------------------------------------- coreboot README ------------------------------------------------------------------------------- coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload. With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required. coreboot was formerly known as LinuxBIOS. Payloads -------- After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot. See http://www.coreboot.org/Payloads for a list of supported payloads. Supported Hardware ------------------ coreboot supports a wide range of chipsets, devices, and mainboards. For details please consult: * http://www.coreboot.org/Supported_Motherboards * http://www.coreboot.org/Supported_Chipsets_and_Devices Build Requirements ------------------ * gcc / g++ * make Optional: * doxygen (for generating/viewing documentation) * iasl (for targets with ACPI support) * gdb (for better debugging facilities on some targets) * ncurses (for 'make menuconfig') * flex and bison (for regenerating parsers) Building coreboot ----------------- Please consult http://www.coreboot.org/Build_HOWTO for details. Testing coreboot Without Modifying Your Hardware ------------------------------------------------ If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU. Please see http://www.coreboot.org/QEMU for details. Website and Mailing List ------------------------ Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website: http://www.coreboot.org You can contact us directly on the coreboot mailing list: http://www.coreboot.org/Mailinglist Copyright and License --------------------- The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details. coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details. This makes the resulting coreboot images licensed under the GPL, version 2.