- The SATA CAP register setup was moved outside the refcode blob we run
so it needs to be set up by coreboot again...
- Slight tweak to fast ramp voltage for broadwell CPU
BUG=chrome-os-partner:25491
BRANCH=None
TEST=Build and boot on samus
Change-Id: I7bdc0811ad8f28ab0912972036dca59d229b0173
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214024
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This can be shared between mainboards, they are still free
to override if needed.
BUG=chrome-os-partner:28234
BRANCH=none
TEST=build and boot on samus
Change-Id: I85fae6e254adcbda1c52410d5ba046f3f05b54c0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213792
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to more easily bring up the 2nd core refactor
the cpu startup logic. A common 32bit_entry.S is compiled
both for romstage and ramstage to provide the common 32-bit
entry point.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted ryu to the kernel. Also, can get the 2nd
core up out of reset.
Change-Id: Id810df95c53d3dc8b36d8bd21851d3b0006a8bc2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213850
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The original code won't set power gating for disabled port correctly,
due to it must be set before Lock
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
verify bit 24, 26 is set in RCBA(0x3a84) for samus
Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: Id78d391ac657665a972cb4fd1810df6304a5a6ab
Reviewed-on: https://chromium-review.googlesource.com/213561
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Kane Chen <kane.chen@intel.com>
Commit-Queue: Kane Chen <kane.chen@intel.com>
Instead of requiring the mainboards to know the magic
literals for the bus numbers provide an easier name to
number to handle all the weird ordering.
BUG=chrome-os-partner:31106
BRANCH=None
TEST=Built and booted on ryu.
Change-Id: Id4d773d3049a43b186711900c61935ba7f3562ce
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213491
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The existing cpu_reset does board-wide reset, thus, should be renamed.
BUG=none
BRANCH=none
TEST=Built firmware for Nyans. Ran faft on Blaze.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I5dc4fa9bae328001a897a371d4f23632701f1dd9
Reviewed-on: https://chromium-review.googlesource.com/212982
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
fixed a coding error and sync sata configuration with ref code
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
verify registers between samus and crb
Change-Id: I09dd80a9772ac82b841363a540c9b7a8689e04a9
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/213137
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This provides are barebones initialization for tegra132 GIC
on CPU0. It routes all interrupts to CPU0, moves them all
into group 1, and attempts to allow non-secure access for
all registers (doesn't appear to be implemented, though).
BUG=chrome-os-partner:31449
BRANCH=None
TEST=Built and booted past smp init in the kernel. Timers
appear to be flowing now since jiffies are updated.
Change-Id: I69dd9ae53f259e876a9bc4b9d7f65330150d2990
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212795
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
In order to access secure device register space the cpu
needs to have the page tables marked as secure memory. In
addition the page tables need to live within secure memory
otherwise the accesses default to non-secure.
Therefore move the page tables to the trustzone region. Remove
the TTB_* config options as well as removing the TTB reservations
from coreboot's resource list.
BUG=chrome-os-partner:31355
BUG=chrome-os-partner:31356
BRANCH=None
CQ-DEPEND=CL:213140
TEST=Built and booted into kernel.
Change-Id: Ia4b9d07ef35500726ec5b289e059208b9f46d025
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213141
I2C6 has a special mux in the SOR/DC domain, so there's a ton
of devices that need to be clocked, SOR unpowergated, and then
the I2C6 muxing done in the DPAUX_HYBRID_PADCTL register.
BUG=none
BRANCH=none
TEST=none, built rush/ryu AOK
Change-Id: I4aaa74ef1b3009da621d1a2ef6f79de8ebf545e2
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/212887
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Added distinct functions for clock_enable and clock_clear_reset,
and rewrote clock_enable_clear_reset() to use them. Useful when
unpowergating SOR partition, for instance, where we need to
enable a bunch of periph clocks, unclamp SOR, then take all of
those periphs out of reset.
BUG=none
BRANCH=none
TEST=none, built rush/ryu OK.
Change-Id: I6fef5a72421cb4e3d7edb33a66f62b6e14865a32
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/212916
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
BUG=None
BRANCH=None
TEST=Built rush and ryu, ran on rush into recovery mode.
I2C6 is in the SOR domain, so a lot of further init is
needed before it can be used. A follow-on patch will do this.
Change-Id: I1160a182ee6e2b2b56479384efc6a9063590448f
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/212671
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This was a merge error when I was pulling in some of the
code into this file I put it after the read of CAP2 but
before it is modified and written back. In the end the
DEVSLP bits are getting set/cleared that need to but the
other bits in the register may be wrong. Also when enabling
devslp set the devslp-present bit in each enabled port.
Also remove much of the 0:1f.2@0x98 setup and the attempt
to write (the write once) CAP register that is already
being written in the reference code.
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
Change-Id: I467f3c15b9f4d4c814ba0ef8baf95739b4bc6662
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212308
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Continuing down the path of easing mainboard maintenance
provide a way to bring up the USB 2.0 ports through funit.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=With ryu patch was able to get same sporadic USB communication.
Change-Id: Iee5ca30b3c8b876a9cae7b91db096fef933a8412
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212332
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With non-cacheable memory region and dma range addition, booting from usb
reaches the same point as mmc.
Change-Id: I1083f8de2bfbe9a233d317b29b8fc56f47c7061d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/211039
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
The clk_rst.h file wasn't including files that had
functionality it was using resulting in broken builds
if just this file was included.
BUG=None
BRANCH=None
TEST=Built with just this file included -> no more errors.
Change-Id: I8dc0fcab363e1089587e6dc8ff04c2a76c5e364c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212331
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Make sure the array size matches the number of supported
FUNITs. Also remove the FUNIT_NONE enumeration so that
there isn't an empty slot in the array at index 0.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built when array wasn't large enough. Compiler threw an error.
Change-Id: I0bb37c51311d202729b7fb9731d6eec0a28dc040
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212330
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
To provide easier access to the base addresses of the controllers
by funit identifier add the base addresses to the data structure.
BUG=chrome-os-partner:31251
BUG=chrome-os-partner:31106
BRANCH=None
TEST=Built.
Change-Id: Iff5564b250dcf2038252d54a4caec3df5f7f3de7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212169
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Provide consistently named base address enumerations as well
as provide some that were missing.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built.
Change-Id: I75030598f7da7dacf8e8eff1d7427c5bf202814f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212168
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
In order to prepare for USB initialization move the clock
configuration into a separate routine in the funit library.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built and booted into recovery mode.
Change-Id: Iea6cd2fbe8369a91c06b15d94b63c409ae83124f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212167
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Just use direct pointers to the registers in the pre-filled
data structures. In 64-bit the sizes increase, but it's small.
The fields now directly point to the correct register so no
need to do any arithmetic to identify the correct register.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built and booted on ryu into recovery.
Change-Id: I186bf5d145437472126067960e62d7ed6a25f295
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212166
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Built and ran on ryu through depthcharge into recovery mode.
Change-Id: I76fa8f1c3469b049df7f5bf943701ce18deeb927
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212151
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Pull out the common usb setup utmip functions from t124 into tegra usb.h. These
can be reused for t132 as well.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=Compiles successfuily for nyan, big and blaze
Change-Id: I83f83bafad0f52ad651fe5989430f41142803f2b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/211200
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Depending on the needs of the mainboard certain regions of the address
map may need to be adjusted. Allow for that.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With ryu patches able to insert a non-cacheable memory region.
Change-Id: Iaa657bba98d36a60f2c1a5dfbb8ded4e3a53476f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212161
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
The high address field was being shifted in the wrong direction
resulting in the lower 12 bits of the upper address being dropped.
BUG=chrome-os-partner:30572
BRANCH=None
TEST=Was able to run on ryu and not hang while wiping memory.
Change-Id: I7bf173bb0373d2d25ce9014c80236fb55cc8e17e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211941
Reviewed-by: Tom Warren <twarren@nvidia.com>
This api provides a common interface to initialize various clock sources,
dividers as well as enabling the clock for various functional units.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Compiles successfully for rush and boots till last known good point.
Change-Id: I7abb193d6a9cfa448df1c48c346b4edbad802329
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/211765
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
In order to prevent possible TPM lockout due to PLTRST assertion
shortly after powering up add a small delay before the reset.
This will affect cold power up only, reboot/resume/warmboot will
all have the flex ratio locked already so this reset is unneeded.
BUG=chrome-os-partner:29859
BRANCH=None
TEST=build and boot on samus. I tried unsuccessfully to trigger the
TPM lockout, but I was not able to do that consistently without this
patch so it is unknown yet whether this is 100% effective.
Change-Id: Ief8c9261c0268b0f90a3022213ebd2b06633b481
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change also depends on mrc due to changes in pei_data.h
Report smbios type 17 for each memory
CQ-DEPEND=CL:210005
BUG=None
BRANCH=None
TEST=Compiles successfully
See smbios type17 in OS by dmidecode
Change-Id: If83c99364726cd17c719a59ed8ac993736c63b9a
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/210399
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
TCO registers are 16bit not 32bit. Also do not log the
TCO reset event in S3 resume path to avoid it being logged
when TCO is not actually tripping.
BUG=chrome-os-partner:28234
BRANCH=None
TEST=manual:
1) build and boot on samus
2) modify kernel command line with nmi_watchdog=0
3) while sleep 1 ; do echo -n V ; done > /dev/watchdog &
4) fg 1
5) ctrl-Z
6) wait for reboot
7) check event log for TCO event
8) check suspend/resume path to ensure no TCO event logged
Change-Id: I9cd8627de8498b280deb088f3a8e1e20546e2f96
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211840
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tegra132 has 2 different paths for booting and resuming from
sleep. The boot path uses the typical bootblock, romstage,
and ramstage. However, the resume path is completely orthogonal.
cbmem_initialize() attempts to recover the cbmem area, but
that functionality should not be used from romstage because
tegra132 is by definition in a fresh boot if it is executing
romstage. Therefore, use cbmem_initialize_empty() so that cbmem
is always initialized from scratch on each boot.
BUG=chrome-os-partner:31239
BRANCH=None
TEST=Built and ran on ryu. Was able to enter recovery and stay in
recovery without entering a reboot loop.
Change-Id: I2016146fdc3aea493a78bab31ea8c8cbd78935c5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211424
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
- ADSP IRQ should be exclusive
- HDA should write reg 0x43 even if disabled
- A few clock gating tweaks based on ref code changes
- Move SATA clock gating to sata.c where SIR changes are done
- Add support for enabling Deep SX in AC/DC modes
- CLKREQ VR Idle for enabled PCIE ports
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
Change-Id: Icece58e32b7a5d2b359debd5516a230cae3fd48c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211611
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The current 2 boards were setting up clocks and enabling
peripherals that apply to the SoC generically. Therefore,
move the common pieces into the SoC code.
BUG=chrome-os-partner:31105
BRANCH=None
TEST=Built and booted through depthcharge on ryu.
Change-Id: I6df1813f88362b8beaf1a716f4f92e42e4b73406
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211191
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
The original intent was to set the equivalent flags by default
for the PAD_CFG_* macros so as not to make the usage too chatty.
The GPIO_INPUT variant didn't have the PINMUX_INPUT_ENABLE field
set. Therefore, automaticaly set it for PAD_CFG_GPIO_INPUT().
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran on ryu.
Change-Id: Ifb630601cf04d2984542933382aace16540863ad
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211133
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The tegra132 SoC provides the monotonic timer API. Therefore,
ensure the reset of the coreboot infrastructure is aware.
BUG=None
BRANCH=None
TEST=Built and ran on Ryu. Noted that ramsgage is showing timings
for each bootstate.
Change-Id: I9b8fcf38cba9bdaaf0455701df1d6328bf1927c1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211132
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
coreboot already has a reset API. Utilize it by selecting
HAVE_HARD_RESET. The tegra132 boards have to provide the
hard_reset() implementation as that involves board-specific
bits. The tegra132 code then provides a cpu_reset() routine
that just promotes that call to a hard_reset().
For the existing tegra132 boards remove the unnecessary files
from the build.
BUG=chrome-os-partner:30784
BRANCH=None
TEST=Ensured hard_reset() does something on Ryu.
Change-Id: I1e1b014062dafb5d81fb9da40006c5405073a95d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211131
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
There was an empty udelay() implementation result in 0 waits.
Provide an actual implementation.
BUG=None
BRANCH=None
TEST=Built and ran through to depthcharge on rush.
Change-Id: I201f2fdc4e4f5c88d48e4002839b03e808a5a1bc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210827
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The gpio_index_to_port() incorrectly was dividing by
GPIO_PORTS_PER_BANK on a value including the bit number. After
masking off the BANK offset just divide by the number of gpios
in a port to get the port offset.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran through to depthcharge. Printed bank, port, and
bit numbers for validation.
Change-Id: I8bb50e922c9fd7c0a1c247ba95394f6deb9f1533
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210909
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
I erroneously added GPIO_NONE_INDEX at the beginning of the
enum block effectively putting every GPIO index off by 1.
Instead, move it to the end.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran through to depthcharge on rush. Also
printed out banks, port, and bit offsets to validate.
Change-Id: I0471480e8658de9e534beb859a1f5027a961d73e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210908
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
It's helpful to be able to track this information. Therefore
dump it in to the console log.
BRANCH=None
BUG=chrome-os-partner:31126
TEST=Built and ran on rush. Revision information is put out on the
console.
Change-Id: Ic95382126a6b8929d0998d1c9adfcbd10e90663f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210903
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Instead of calling out with function names all the possible
combinations of interface and device provide one call to the
mainboard to configure all the necessary bits.
BUG=chrome-os-partner:31104
BUG=chrome-os-partner:31105
BRANCH=None
TEST=Built and ran on rush.
Change-Id: Id27d9c2da4dccdff38c48dc5cdeb1a68cf23cbfc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210838
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Instead of hard coding certain pieces of a board in the common
chipset code provide a way to initialize things early in the
bootblock path. Add a bootblock_mainboard_early_init() function
before console init to performany necessary mainboard initialization
early in the bootblock.
BUG=chrome-os-partner:31104
BUG=chrome-os-partner:31105
BUG=chrome-os-partner:29981
BRANCH=None
TEST=built both on rush and ryu. rush still behaves the same.
Change-Id: I7d93641dff3a961f120e8f0ec2d959182477ef87
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210835
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Start using the soc_configure_pads() API. This allows for
bulk processing of pads.
BUG=chrome-os-partner:31105
BUG=chrome-os-partner:31104
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and can get console messages on rush.
Change-Id: Iaa6a6ff4d559aedb98b078e87b0ecddefd3402d6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210834
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Instead of sprinkling the pad configuration and pinmux
selection throughout the code allow for a data-driven
initialization sequence. Most of the calls in the
original pinmux functions require 12 bytes per pad
plus the support code. This implementation allows for
4 bytes per pad in addition to the support code.
BUG=chrome-os-partner:29981
TEST=Built and booted into depthcharge on rush.
Change-Id: I3a119b4068e880b74a0a1597f143d7c4e108a6c1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210833
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Workaround for auto shutdown issue on broadwell SKU.
Now we can see C7 transition, and MRC fastboot
BUG=chrome-os-partner:29787,chrome-os-partner:29117
BRANCH=None
TEST=build ok and boot on samus
Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: Id1f174b67fa3e6f248dd8b21aee25e6e01abf33e
Reviewed-on: https://chromium-review.googlesource.com/210870
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Kane Chen <kane.chen@intel.com>
Commit-Queue: Kane Chen <kane.chen@intel.com>
Rush has its EC on SPI, and Ryu has it on I2C, so need both
mainboard_init_ec_spi and mainboard_init_ec_i2c in both builds,
due to romstage.c being in the common tegra132 subdir.
BUG=none
BRANCH=rush_ryu
TEST=Built both rush and rush_ryu images OK. Will try to
boot on Ryu later.
Change-Id: I48d9530697d5669177ecd9ba3c34360197002003
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/210595
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
