tegra132: introduce romstage_mainboard_init()

Instead of calling out with function names all the possible
combinations of interface and device provide one call to the
mainboard to configure all the necessary bits.

BUG=chrome-os-partner:31104
BUG=chrome-os-partner:31105
BRANCH=None
TEST=Built and ran on rush.

Change-Id: Id27d9c2da4dccdff38c48dc5cdeb1a68cf23cbfc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210838
Reviewed-by: Furquan Shaikh <furquan@chromium.org>

src/mainboard/google/rush/romstage.c

@@ -34,7 +34,7 @@ static void configure_tpm_i2c_bus(void)
 	i2c_init(2);
 }
 
-void mainboard_init_tpm_i2c(void)
+static void mainboard_init_tpm_i2c(void)
 {
 	clock_enable_clear_reset(0, 0, CLK_U_I2C3, 0, 0, 0);
 
@@ -51,7 +51,7 @@ void mainboard_init_tpm_i2c(void)
 	configure_tpm_i2c_bus();
 }
 
-void mainboard_init_ec_spi(void)
+static void mainboard_init_ec_spi(void)
 {
 	clock_enable_clear_reset(0, CLK_H_SBC1, 0, 0, 0, 0);
 
@@ -75,9 +75,10 @@ void mainboard_init_ec_spi(void)
 	clock_configure_source(sbc1, CLK_M, 500);
 }
 
-void mainboard_init_ec_i2c(void)
+void romstage_mainboard_init(void)
 {
-	/* Empty - Rush uses SPI to communicate with the EC */
+	mainboard_init_tpm_i2c();
+	mainboard_init_ec_spi();
 }
 
 void mainboard_configure_pmc(void)

src/mainboard/google/rush_ryu/romstage.c

@@ -39,7 +39,7 @@ static void configure_ec_i2c_bus(void)
 	i2c_init(1);
 }
 
-void mainboard_init_tpm_i2c(void)
+static void mainboard_init_tpm_i2c(void)
 {
 	clock_enable_clear_reset(0, 0, CLK_U_I2C3, 0, 0, 0);
 
@@ -55,12 +55,7 @@ void mainboard_init_tpm_i2c(void)
 	configure_tpm_i2c_bus();
 }
 
-void mainboard_init_ec_spi(void)
-{
-	/* Empty - Ryu uses I2C to communicate with the EC */
-}
-
-void mainboard_init_ec_i2c(void)
+static void mainboard_init_ec_i2c(void)
 {
 	clock_enable_clear_reset(0, CLK_H_I2C2, 0, 0, 0, 0);
 
@@ -74,6 +69,12 @@ void mainboard_init_ec_i2c(void)
 	configure_ec_i2c_bus();
 }
 
+void romstage_mainboard_init(void)
+{
+	mainboard_init_tpm_i2c();
+	mainboard_init_ec_i2c();
+}
+
 void mainboard_configure_pmc(void)
 {
 }

src/soc/nvidia/tegra132/include/soc/romstage.h

@@ -20,10 +20,10 @@
 #ifndef __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__
 #define __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__
 
+void romstage(void);
+void romstage_mainboard_init(void);
+
 void mainboard_configure_pmc(void);
 void mainboard_enable_vdd_cpu(void);
-void mainboard_init_tpm_i2c(void);
-void mainboard_init_ec_spi(void);
-void mainboard_init_ec_i2c(void);
 
 #endif /* __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ */

src/soc/nvidia/tegra132/romstage.c

@@ -32,7 +32,10 @@
 #include <soc/clock.h>
 #include <soc/romstage.h>
 
-void romstage(void);
+void __attribute__((weak)) romstage_mainboard_init(void)
+{
+	/* Default empty implementation. */
+}
 
 static void *load_ramstage(void)
 {
@@ -86,9 +89,7 @@ void romstage(void)
 	ccplex_load_mts();
 	printk(BIOS_INFO, "T132 romstage: MTS loading done\n");
 
-	mainboard_init_tpm_i2c();
-	mainboard_init_ec_spi();
-	mainboard_init_ec_i2c();
+	romstage_mainboard_init();
 
 	entry = load_ramstage();