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broadwell: Tweak GFXPAUSE settings based on revision

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Changes from 2.1.0 reference code release.

BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus

Change-Id: I6110a9bdb2973f1a134d8105c37659bf43f61d34
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210607
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2014-07-31 10:46:57 -07:00 • committed by chrome-internal-fetch
commit ef660ddc6c
3 changed files with 20 additions and 2 deletions
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3
src/soc/intel/broadwell/broadwell/systemagent.h
View file

@ -122,4 +122,7 @@
/* Data is passed through bits 31:0 of the data register. */
#define BIOS_MAILBOX_DATA 0x5da0
/* System Agent identification */
u8 systemagent_revision(void);
#endif

14
src/soc/intel/broadwell/igd.c
View file

@ -147,8 +147,7 @@ static const struct reg_script broadwell_early_init_script[] = {
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa250, 0x000000ff),
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa25c, 0x00000010),
/* GFXPAUSE settings */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00030020),
/* GFXPAUSE settings (set based on stepping) */
/* ECO Settings */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x45200000),
@ -166,6 +165,9 @@ static const struct reg_script broadwell_early_init_script[] = {
/* Video Frequency Request */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000),
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138158, 0x00000009),
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x13815c, 0x0000000d),
/*
* RC6 Settings
*/
@ -489,6 +491,14 @@ static void igd_init(struct device *dev)
/* Early init steps */
if (is_broadwell) {
reg_script_run_on_dev(dev, broadwell_early_init_script);
/* Set GFXPAUSE based on stepping */
if (cpu_stepping() <= (CPUID_BROADWELL_E0 & 0xf) &&
systemagent_revision() <= 9) {
gtt_write(0xa000, 0x300ff);
} else {
gtt_write(0xa000, 0x30020);
}
} else {
reg_script_run_on_dev(dev, haswell_early_init_script);
}

5
src/soc/intel/broadwell/systemagent.c
View file

@ -37,6 +37,11 @@
#include <broadwell/ramstage.h>
#include <broadwell/systemagent.h>
u8 systemagent_revision(void)
{
return pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID);
}
static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
{
u32 pciexbar_reg;