Mark GPIO42 as unused according to Samus schematics
BUG=None
TEST=Make the chnage; Pass the build process; Need someone having
the board perform the verification.
Change-Id: Ifd6a0d2de8af0fe3af4a14f44ce572b41b77509c
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/217344
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
For now storm bootblock runs with DRAM fully initialized, this patch
puts the early console between bootblock and rom phase.
BUG=chrome-os-partner:31734
TEST=verified that preram_cbmem_console is set:
$ grep preram_cbmem_console cbfs/fallback/bootblock.map
40618000 A preram_cbmem_console
Change-Id: I132a0cbcc82e713c36fc5031706d9afbf3e9b879
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217291
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of relying on config variables to determine the current el, use
{read/write}_current macros for accessing registers.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully and boots to kernel login prompt
Change-Id: If4a5d1e9aa50ab180c8012862e2a6c37384f7f91
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/217148
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Allow read/write to registers at a given el. Also, make read/write registers at
current el call this newly added function.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully
Change-Id: I17de4c4f3bc1ee804422efe5f4703b4dd65b51f2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/216904
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Required for arm64 platforms: rmodules used for arm64 require module_params and
rodata to be placed at 8-byte boundary in order to avoid unaligned access.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully and address verified during boot
Change-Id: I4820efad2b408ebd3930943f7771805a7bbb62e9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/216374
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
In order to ease the process of reading and writing any register at current EL,
provide read_current and write_current assembly macros. These are included in
arch/lib_helpers.h under the __ASSEMBLY__ macro condition. This is done to allow
the same header file to be included by .c and .S files.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully
Change-Id: I1258850438624abfe3b1ed7240df0db0e7905be6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/216373
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
According to BIOS spec 8.14
B0:D28:F0[5:4] should be set to 11
BRANCH=none
BUG=chrome-os-partner:28234
TEST=build ok, boot to Auron and Samus
make sure register is set and PCIE is working
Change-Id: I7c37245053ceae460dac0f18363f585244db72f8
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/217414
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit 27d5d6a3 (t132: Fix clock apis) broke the Rush build.
Rush needs SBC1 (for EC) and SDMMC3 (for SD-card) added to the
table/enum in clock.h. To make future T132 board ports easier,
all periphs should have an entry in this table/enum - I just
added the 2 needed to fix the Rush build in this change.
BUG=None
BRANCH=None
TEST=Built and booted all Tegra132 boards (Rush and Ryu)
Change-Id: I6659858c24e925aec9495bf64344c0000ad19b4c
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/217342
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The proto0.2 hardware connects gpio26 (sw reset) to the ethernet
switch reset pit. The output stays low (or high-z) after power up,
which holds the switch in reset. Deassert the signal at startup on
hardware rev 1 and later.
BUG=chrome-os-partner:31780
TEST=with this patch applied, when proto0.2 boots, the ethernet
switch's LED blink once, as was the case with proto0.
Change-Id: I81b3dccb1d1d43c5c1e6dcb5400af8eed6dee870
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217087
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This memory is also x16 and needs slight tweak to tRFCmin
in order to be functional.
BUG=chrome-os-partner:31833
BRANCH=None
TEST=build and boot on EVT unit with this config
Change-Id: I01163ee7e70f08ccad84a3da39f1aac96e4c4771
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217190
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Nvidia tracks their MTS versions using decimals. Update
the format so there isn't an extra step in communicating
versions while debugging things.
BUG=chrome-os-partner:31864
BRANCH=None
TEST=Booted and confirmed decimal print out.
Change-Id: Ia7d0bc49318a4b4c969ee37e762e084ec65de543
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217260
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Figuring out board_id on storm requires reading tertiary gpios, which
takes time. Let's calculate it once and reuse it when necessary.
BUG=none
TEST=verified board ID reported as 0 and 1 on proto0 and proto0.2
respectively.
Change-Id: I4e237077d1d9a96daebba462cd00f3f40be14518
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217086
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Now that there is cpu devicetree support retire the
bring_up_secondary_cpu option as the devicetree is the
way going forward to do other CPU bring up.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and booted with 2nd core.
Change-Id: Ic213fbf56a1846e73462886f876a0a70e48b3158
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216929
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Now that arm64 and tegra132 has cpu devicetree support stop
using the bring_up_secondary_cpu option.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and brought up 2nd core.
Change-Id: I210bea73f8249de15f99d0c062600e789184eefd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216928
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The original purpose of soc_secondary_cpu_init() was to provide
a way for the SoC to run code on the secondary processors as
they come up. Now that devicetree based bringup is supported
there's no need to have this functionality.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Booted SMP into linux.
Change-Id: Ie5c38ef33efadb2d6fdb2f892b4d08f33eee5c42
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216927
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Use the formal devicetree way for bringing up each of
the cpus. This includes providing a cpu_driver as well
as calling arch_initialize_cpus() with the proper
operations to start the cores.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Booted SMP on ryu.
Change-Id: I13d8bfd645abf66f270d56d48eff4331c4ea1200
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216926
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This adds SMP bring up support for arm64 cpus. It's
reliant on DEVICE_PATH_CPU devices in the devicetree.
Then for each enabled device it attempts to start then
initialize each CPU. Additionally, there is a cpu_action
construct which allows for running actions on an individual
cpu.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Booted both cores on ryu into linux.
Change-Id: I407eabd0b6985fc4e86de57a9e034548ec8f3d81
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216925
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Add a cpu-internal.h for internal prototypes to the
architecture specific code.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and booted.
Change-Id: I8ab520478954a3b43e8e0831d1883f9a791850aa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216924
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Provide a simple spinlock implentation for arm64. A value
of 0 is unlocked and a value of 1 is locked.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and ran SMP bringup on ryu.
Change-Id: I3bf2d80b91112d04442455ff0fa3f16900b7327f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216923
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The spinlock header file was not residing in the correct place.
It needs to live under 'arch/smp'.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built with SMP. spinlock.h found.
Change-Id: I0e594cacfafcd6f30802c9563785ca09a2f7a2af
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216922
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The load-acquire/store-release operations (including exclusive
variants) form a basis for atomic operations. Also remove
the dmb, dsb, and isb functions from lib_helpers as barrier.h
already included these. Lastly, utilize barrier.h.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and ran SMP bringup using barriers.
Change-Id: I77ff160c635297a2c7cab71cb0d3f49f2536f6ff
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216921
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
printk() shouldn't be called until the consoles have been
initialized. This just so happened to work by luck. Once
CONFIG_SMP is enabled that breaks because of spinlock
usage in uncached memory.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built with CONFIG_SMP and ramstage doesn't hang early.
Change-Id: I6091b1e949e648b3435231946e5924260bf1807f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216920
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
printk() shouldn't be called until the consoles have been
initialized. This just so happened to work by luck. Once
CONFIG_SMP is enabled that breaks because of spinlock
usage in uncached memory.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built with CONFIG_SMP and ramstage doesn't hang early.
Change-Id: I247caac410894fb896dfb25a27c3a3213ef7f020
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216429
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Add all the CPUs to the device tree.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Brought up 2nd core on ryu in kernel.
Change-Id: I682f23a9b68f49206aa99d55e800540d8d0f8900
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216426
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
BUG=chrome-os-partner:31812
TEST=check if TS is found by the kernel
Change-Id: I22e6a9b65253bd17b639ce4d0742d1e7d3109e0c
Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216527
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Instead of directly using the clk_src_id based on enum for clock source, every
device needs to have its own set of clk source ids defined. This prevents from
accidentally selecting a wrong clk source if the ids are changed as for host1x.
Also, clk_src_id is separated from clk_src_freq_id. clk_src_id is the clk src id
represented in CLK_SOURCE_<dev> registers, whereas clk_src_freq_id is used for
handling the common clock sources based on id to get the proper frequency in
software.
BUG=chrome-os-partner:31821
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt
Change-Id: I5c88bed62841ebd81665cf8ffd82b0d88255f927
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/216761
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Provide access to the MIDR_EL1 register to obtain the
main id for determining CPU implementer and part/revision
information.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and printed the output of this function on ryu.
Change-Id: I8b8506ebff8e6f9d7c4f96d7ff7e21803972961e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216423
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The host1x clock selection register has a different encoding
than the major of other clock source registers. This results
in PLLM_OUT0 being selected when PLLP_OUT0 was requested.
Use the clock_configure_irregular_source() method to correct
this situation.
BUG=chrome-os-partner:31820
BRANCH=None
TEST=Noted proper clock selection was achieved.
Change-Id: Idc1ea88e2e1f2abc0c13e7aa1e8bdfa981da388e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216422
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
This function is breaking display bring up in the kernel. While
this functionality may be needed it's not until there is a
necessity to beep and/or bring up the display in firmware.
BUG=chrome-os-partner:31820
BRANCH=None
TEST=Sean ran with this patch and the display indeed did come up.
Change-Id: I833d66a0e63e04118b130b6803a7a3b68c802148
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216421
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: I805d93e94f73418099f47d235ca920a91b4b2bfb
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/209469
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Julius Werner <jwerner@chromium.org>
There is no proto function for mainboard_suspend_resume
In this case mainboard_suspend_resume is not NULL,
and cause if statment true.
Bios will jump to an empty weak function,
if mainboard_suspend_resume is not defined in mainboard.c
Then system becomes panic during s3 resume
BUG=chrome-os-partner:31286
TEST=compile ok and make sure system can resume from s3
BRANCH=None
Change-Id: I76bdea1d96166e683c6284024e1befbfc0d64645
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/215865
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
These are used by the LPDDR3 code in sdram.c.
Based on the schematic and email, I've filled in 4 slots
in sdram_configs.c. My A44 returns RAMCODE 0 (using only bits
1:0) for Samsung SDRAM. I haven't tested the other 2 types of
RAM (Hynix and Micron). The 4th slot is a fallback slow Micron
config.
BUG=chrome-os-partner:29921
BUG=chrome-os-partner:31031
BRANCH=None
TEST=Built for rush and rush_ryu.
Change-Id: Ib7e8b814eb6dadb9b366536721876a3eeba0d2c0
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/216000
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These are not needed/were never really used. SDRAM init will now
be done in sdram.c, not the BootROM.
BUG=chrome-os-partner:29921
BUG=chrome-os-partner:31031
BRANCH=None
TEST=Built rush_ryu AOK.
Change-Id: I7d25de3e888bb24e4c6e6dea2726510c97fe1730
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/215863
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Expanded sdram.c to add support for LPDDR3 init. This code can
be used with matching BCT .inc files to have LPDDR3 SDRAM
initialized by coreboot instead of the T132 BootROM.
BUG=chrome-os-partner:29921
BUG=chrome-os-partner:31031
BRANCH=None
TEST=Built for rush and rush_ryu.
Change-Id: I6bcffcd22d2e4f8da6d729b6757714657f3f6735
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/214753
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Not much is happening yet, when the board is enabled (in the next
patch), all three components build successfully, the map files show
them placed where expected and the bopotblock is wrappeed in a BIMG
header.
BUG=chrome-os-partner:31438
TEST=when config is enabled, emerge-urara coreboot succeeds. more
extensive testing to come later
Change-Id: I573cfb70f5c1e612dfa0a55d3d22d92f00584c66
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214600
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Romstage initialization code does not need to be board specific, keep
it in the SOC directory. Should there be a need for the board specific
code, it can be added later.
BUG=chrome-os-partner:31438
TEST=with upcoming patches, the urara board coreboot builds fine
Change-Id: I27e2d225bd36c42ccd29128d0ea9a970566c02af
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215992
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With the proper configuration flags enabled, do_printk is available
from src/console, no need to define it elsewhere.
BUG=chrome-os-partner:31438
TEST=with upcoming patches, the urara board coreboot builds fine
Change-Id: Ib1e3e5750cdc1adc509b4580a4f24d3ff3b105ee
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215862
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When doing an EC requested reboot to RO mode clear the
saved post code in order to prevent confusing events in
the log where the system is rebooted intentionally.
BUG=chrome-os-partner:28234
BRANCH=none
TEST=build and boot on samus, run FAFT, check for odd
eventlog entries about last post code 0x31 when it is
rebooted during samus romstage entry point.
Change-Id: I8bedc611712424bf1044cdca1972e34ffdd51abd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215681
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These modules are necessary to resolve external names when building
the board image. These are just skeletons for now which will be filled
later.
BUG=chrome-os-partner:31438
TEST=when config is enabled, emerge-urara coreboot succeeds. more
extensive testing to come later
Change-Id: I69cc178976a910ebf8031ed9ac9ad67b4cc0878a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215678
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add basic board support for the ImgTec Danube Virtual Platform, which
emulates a system built around the Danube SoC.
Run this by loading coreboot.bimg into a flash device connected to SPFI1
chip select 0 & then executing the Danube boot ROM.
BUG=chrome-os-partner:31438
TEST=none yet
Change-Id: I7a2b52f304bcb4b614440ec38975e05f38b0e590
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/207976
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add build infrastructure and basic support code for the ImgTec Danube
SoC. This support is sufficient to run on a simulator.
BUG=chrome-os-partner:31438
TEST=none yet
Change-Id: Ia7ed7288b13085db7ff37b5ad75d978b6137f958
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/207974
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In addition to ARM based systems, allow MIPS based systems to select
bootblock console support.
BUG=chrome-os-partner:31438
TEST=none yet
Change-Id: I41f03ea8c8104ba2dd9f532b084696385d29636c
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-on: https://chromium-review.googlesource.com/207973
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
The power button signal is driven from the silego part.
It's active high when the button is pressed.
BUG=None
BRANCH=None
TEST=Booted with power button pressed. vboot saw the press and
requested a shut down.
Change-Id: If25ebce28c1ab5a363f3b4b5ab9fc24baebad56a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214847
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Instead of calling out the gpio index and port numbers use
real names. It's semantically clearer and there's only one
place to adjust the hardware values.
BUG=chrome-os-partner:31106
BRANCH=None
TEST=Built and booted.
Change-Id: I68c138b428abbd0c9bc60be0cfc70681528d7728
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215542
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
