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tegra132: fix host1x clock selection

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The host1x clock selection register has a different encoding
than the major of other clock source registers. This results
in PLLM_OUT0 being selected when PLLP_OUT0 was requested.
Use the clock_configure_irregular_source() method to correct
this situation.

BUG=chrome-os-partner:31820
BRANCH=None
TEST=Noted proper clock selection was achieved.

Change-Id: Idc1ea88e2e1f2abc0c13e7aa1e8bdfa981da388e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216422
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Aaron Durbin 2014-09-05 09:06:55 -05:00 • committed by chrome-internal-fetch
commit 14b51ea737
1 changed files with 5 additions and 3 deletions
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8
src/soc/nvidia/tegra132/i2c6.c
View file

@ -26,7 +26,6 @@
#include <soc/nvidia/tegra132/clk_rst.h>
#include "delay.h"
#define I2C6_BUS 5
#define I2C6_PADCTL 0xC001
#define DPAUX_HYBRID_PADCTL 0x545C0124
@ -90,8 +89,11 @@ void soc_configure_i2c6pad(void)
remove_clamps(POWER_PARTID_SOR);
unreset_sor_periphs();
/* Host1X needs a valid clock source so DPAUX can be accessed */
clock_configure_source(host1x, PLLP, 204000);
/*
* Host1X needs a valid clock source so DPAUX can be accessed. Note that
* 4 is the PLLP_OUT0 source for this register.
*/
clock_configure_irregular_source(host1x, PLLP, 204000, 4);
/* Now we can write the I2C6 mux in DPAUX */
write32(I2C6_PADCTL, (void *)DPAUX_HYBRID_PADCTL);