Update the API used to configure Soundwire GPIOs to the LPASS GPIO
configure API, as these GPIOs are controlled by the LPASS subsystem.
Applies to the Soundwire amplifier GPIOs:
- GPIO_SNDW_AMP_0_ENABLE (GPIO 204)
- GPIO_SNDW_AMP_1_ENABLE (GPIO 205)
- GPIO_SNDW_0_SCL (GPIO 202)
- GPIO_SNDW_0_SDA (GPIO 203)
Test=1. Create an image.serial.bin and verify it boots successfully on
X1P42100.
2. Dump the corresponding TLMM GPIO CFG register and verify if the
eGPIO bit is disabled. The register details are part of HRD-X1P42100-S1
document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
Change-Id: I9cc16b659fc5302ef81951ffbad8e62ce90e2890
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Introduce a new API to handle configuration of LPASS GPIOs. The TLMM
GPIOs include an eGPIO enable bit that determines which subsystem
controls the GPIO. When set, the APPS processor controls the GPIO.
When cleared, the GPIO is controlled by the LPASS subsystem.
For GPIOs intended for LPASS, this API avoids enabling the eGPIO bit,
ensuring the GPIO remains controlled by the LPASS subsystem.
Test=Create an image.serial.bin and verify it boots successfully on
X1P42100.
Change-Id: Iccb51d3f5e6be4c1fadfdc7b9778805ae3e66af7
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
In dt_copy_subtree(), the device_tree_node copying
*dst_node = *src_node;
doesn't work correctly for circular linked lists [1], because the 'next'
pointer of the last element isn't modified to point to the dst head.
As the only public caller of dt_copy_subtree() is dt_apply_overlay(),
and the dt_apply_overlay() function comment already explicitly disallows
'overlay' accesses after the call, fix the problem by utilizing
list_move() for copying device tree node properties and children.
Also add a new test case test_dt_apply_overlay.
[1] commit 23c41622a9 ("commonlib/list: Change to circular list")
BUG=b:434080284
TEST=emerge-rauru coreboot libpayload
BRANCH=none
Change-Id: I166ab74c9de67330d52f94e92b5d7ce5ddefa82b
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91558
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
This function transfers all elements from one list head to another. The
The destination list head takes ownership of all nodes from the source
list head. The source list head is reinitialized to an empty list.
This is useful for efficiently moving list contents without element-wise
relinking, particularly in contexts like device tree overlay application
where node structures are incorporated from a temporary tree.
BUG=b:434080284
TEST=emerge-rauru coreboot libpayload
BRANCH=none
Change-Id: I143394e381fa72bcba692b7727f57dfc09fda70e
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Rename the devtree_update() bootstate hook added in commit f8494fbeae
("lib: Add devtree_update bootstate hook") to mb_devtree_update()
for clarity, since it is a mainboard-provided hook.
Update all declarations, definitions, and call sites accordingly.
TEST=build Starlabs Starfighter MTL
Change-Id: Id7fd9811433a668905d8439b90a8ee34a472d117
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Remove the explicit devtree_update() call from mainboard configuration.
The devtree_update hook is provided by src/lib/devtree_update.c and runs
at BS_PRE_DEVICE. Drop the variant declarations from variants.h and add
the devtree_update header in each variant devtree.c so their overrides
are used via the common mechanism.
TEST=build/boot Starlabs Starfighter MTL
Change-Id: Ia7ceaaefe717566c6411f86d81d3a76bdfb2b2ea
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91573
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Samsung K3KL8L80EM-MGCU and K3KL9L90EM-MGCU to the supported
memory parts list for the moonstone variant.
BUG=None
BRANCH=None
TEST=Regenerate SPD ID for moonstone via spd_tools
Change-Id: Iefde607ef703b7355b4516bf8f4fbe0129f7150d
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91559
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Decode LPDDR5/LPDDR5X .spd.hex dumps into spd_tools-compatible JSON.
The default output is a single-part memory_parts.json-style document
without the bits that spd_gen adds automatically.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I49874bcd42cf3981277abbfa997ec185088f0715
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89785
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Run some steps a bit earlier for consistency with Lynx Point.
Change-Id: I819f95275b23867c83d0991f1eaab3d2e8947abc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91473
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This write is already done later on, in `pcie_enable_clock_gating()`.
Change-Id: Id152e1358f581e2a3ef6871a909be366f309c1dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91472
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For consistency with Lynx Point, ensure OBFF is disabled in DCTL2.
Change-Id: Id726ade900adfce513ad58c77027de8862bd271b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Prepare to unify both southbridges by deduplicating the ASL files. This
change is meant to be reproducible, so there is some preprocessor usage
to achieve this. It will be tidied up in follow-up changes.
Tested with BUILD_TIMELESS=1, Purism Librem 15 v2 remains identical.
Change-Id: Ibbb2d76448d87fad7f9d765cd659d60f54c54703
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91470
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The chipset platform.asl only provided empty _PTS/_WAK stubs and _SWS
methods, which mainboards needing custom sleep/wake behavior (e.g. EC
methods) cannot use. Only 2 of 5 Wildcat Point boards used it. Move the
content to mainboard code and inline the device_nvs and common platform
includes in dsdt.asl to align with other Wildcat Point and Lynx Point
boards. Keeping device NVS in mainboard code also simplifies future
Lynx/Wildcat unification.
Tested with BUILD_TIMELESS=1, Purism Librem 15 v2 remains identical.
Change-Id: I753302a13567efb3b7903364be8cef486d2b76e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91469
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
In the charger applet, it is possible for the PMIC to take some time
to negotiate and enable the charging current. Previously, the code
proceeded immediately, which could lead to false-positive power-off
triggers if current hadn't started flowing yet.
This change:
1. Implements a 3000ms stopwatch-based timeout.
2. Polls get_battery_icurr_ma() until a non-zero current is detected.
3. Aborts the applet if current fails to stabilize within the window.
4. Adds logging to track the actual duration of the power-up sequence.
BUG=none
BRANCH=none
TEST=Verified that the system enters off-mode charging more reliably
without powering off.
```
[INFO ] Inside launch_charger_applet. Initiating charging
...
...
[INFO ] Issuing power-off due to change in charging state.
...
...
```
Change-Id: Ie3501dff06aadf81d527658c4042de7c92de24b5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add H58G56DK9BX068 in the memory_parts.json and re-generate the SPD.
BUG=none
TEST= Booted successfully on nvlrvp board using H58G56DK9BX068.
util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I7f8e13c2dac50b108f3ded1528a48b641eafbeec
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90856
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This aligns with the corrected indexing scheme used in the SoC VR
configuration code.
Ref=:830097_WCL_PDG_SchChk_Rev1p5
BUG=b:None
TEST=Build ocelot and verify that the system boots
Change-Id: I948c9233f4a5518992891b90fb9bb6a3793baa5f
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Set IA voltage regulator to use IRMS mode with 28 second time window
for more accurate thermal design current measurement.
Ref=:830097_WCL_PDG_SchChk_Rev1p5
BUG=b:None
TEST=Build ocelot and verify that the system boots with the following
VR parameter
[SPEW ] TdcMode[0]:0x1
[SPEW ] TdcMode[1]:0x0
[SPEW ] TdcMode[2]:0x0
[SPEW ] TdcMode[3]:0x0
[SPEW ] TdcTimeWindow[0]:0x6D60
[SPEW ] TdcTimeWindow[1]:0x0
[SPEW ] TdcTimeWindow[2]:0x0
[SPEW ] TdcTimeWindow[3]:0x0
Change-Id: I4b7b9484d47cf9d98548cfc8b53e47be4e21c4d1
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91455
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When ramstage is not LZ4 compressed then don't include the LZ4
decompressor into postcar stage.
TEST=Reduces postcar size on Lenovo x220 by 1224 bytes.
Change-Id: I51e25d94213b42474c8cedd9e7bae9e81568566d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91385
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This board no longer uses option table, so the config is invalid.
Change-Id: I62268472e9a2020e81c352933aa9bac8bb2fcddd
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91541
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The LCD MIPI panel requires proper power-off commands before reset.
Skipping them may cause overpotential conditions, leading to image
stickiness or flicker.
On MTK platforms, CR50 reset is the only reboot path in coreboot.
Add mainboard_prepare_cr50_reset() implementation on skywalker to
power off the MIPI panel before issuing CR50 reset.
BUG=b:474187570
TEST=emerge-jedi coreboot chromeos-bootimage
BRANCH=skywalker
Change-Id: I46a654e03ca2e7374cdaf05729f12b182669a64f
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91507
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Zhengqiao Xia <xiazhengqiao@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce mtk_mipi_panel_poweroff() in common display layer and
mtk_dsi_panel_poweroff() in DSI driver. The DSI mode flags are
saved during init and reused for the power-off command path.
BUG=b:474187570
TEST=emerge-jedi coreboot chromeos-bootimage
BRANCH=skywalker
Change-Id: Ic684822bc5f20d3e2f5ce3d44035c902a2b44184
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91432
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhengqiao Xia <xiazhengqiao@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The commit 7072f42c08f7 ("soc/mediatek/mt8196: Move WATCHDOG_TOMBSTONE
from SRAM to SRAM_L2C") move WATCHDOG_TOMBSTONE from SRAM to SRAM_L2C
causes elog_handle_watchdog_tombstone (BS_POST_DEVICE, BS_ON_ENTRY) to
be invoked after mtk_mmu_disable_l2c_sram. As a result, the watchdog
event magic value in WATCHDOG_TOMBSTONE is cleared before it can be
processed, which is incorrect behavior.
So we refactor the mtk_mmu_disable_l2c_sram to be called as a boot state
entry (BS_POST_DEVICE, BS_ON_EXIT) instead of directly from soc_init.
This ensures that mtk_mmu_disable_l2c_sram will be executed after
elog_handle_watchdog_tombstone.
BUG=b:481854714
TEST=watchdog event added to eventlog on WDT timeout (triggered via echo > /dev/watchdog)
TEST=cbmem logs preserved on WDT timeout
Change-Id: I69ef567ab73f2f7006bb249cb577f377d4720909
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The purpose of the WATCHDOG_TOMBSTONE section is to temporarily record
the watchdog timeout event, before triggering the reboot. Then, in the
next boot, if WATCHDOG_TOMBSTONE contains the watchdog event magic, then
a watchdog event will be added to the event log.
The flow relies on the fact that the WATCHDOG_TOMBSTONE section can be
preserved across AP resets. However, for MT8196, the whole SRAM region
will be powered down during AP reset via GPIO AP_SYSRST_ODL (SYSRSTB).
On MT8196, L3C (used as SRAM_L2C) is powered on by default. Also, per
MT8196 PMIC configuration, a SYSRSTB reset will retain the L3C power.
Therefore, region data in SRAM_L2C can be preserved across AP resets.
Fix the WATCHDOG_TOMBSTONE preservation by moving it to SRAM_L2C.
Reduce PRERAM_CBMEM_CONSOLE by 1K for WATCHDOG_TOMBSTONE.
BUG=b:481854714
TEST=watchdog event added to eventlog on WDT timeout:
17 | 2026-03-04 08:57:17+0000 | Hardware watchdog reset
TEST=cbmem logs preserved on WDT timeout
Change-Id: I630d1749e1a743069f2d814efe0a4994889a2a3f
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91540
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Communication with GSC and EC is abnormal because Mica is
missing the following configurations: DRIVER_TPM_I2C_BUS,
EC_GOOGLE_CHROMEEC_SPI_BUS,and MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT.
BUG=b:489062509,b:489264026
TEST=build mica board, flash to Quenbi to verify the GSC and
EC communication functionality.
Check if there are any further abnormalities in the bootup log:
For GSC:
Probing TPM I2C: Cr50 TPM IRQ timeout!
For EC:
crosec_spi_io: Timeout waiting for framing byte.
Change-Id: I2ff158968f946eb780d593c8b1d1e8b07f95ce8a
Signed-off-by: KangMin Wang <kangmin.wang@luxshare.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91517
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Replace platform-specific finalize.c with the common finalize
implementation.
Changes:
- Remove src/soc/intel/pantherlake/finalize.c
- Enable SOC_INTEL_COMMON_FEATURE_FINALIZE in Kconfig
- Update Makefile.mk to remove finalize.c from build
The finalize implementation was identical to Meteor Lake, making
it an ideal candidate for consolidation.
Change-Id: I749eea246fdc7ab89848ed4160c61666e8944095
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Replace platform-specific finalize.c with the common finalize
implementation.
Changes:
- Remove src/soc/intel/meteorlake/finalize.c
- Enable SOC_INTEL_COMMON_FEATURE_FINALIZE in Kconfig
- Update Makefile.mk to remove finalize.c from build
The finalize implementation was identical to Panther Lake, making
it an ideal candidate for consolidation.
Change-Id: Id0c3bde3b721b7a3e497711cfc6dd21efbfda4c5
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
This introduces a common finalize implementation for Intel SoCs that
consolidates the nearly identical finalize.c files across Meteor Lake
and Panther Lake platforms.
The implementation includes:
- pch_finalize(): TCO lockdown and PMC status clearing
- tbt_finalize(): Disable Thunderbolt PCIe root ports bus master
- sa_finalize(): Lock system agent PAM regions when coreboot handles
chipset lockdown
- heci_finalize(): Set HECI to D0i3 and optionally disable HECI1
- soc_finalize(): Main finalization sequence coordinating all the above
This consolidation eliminates duplicate code and ensures consistent
finalization behavior across platforms. Alder Lake is intentionally
excluded as it has additional platform-specific camera clock (ISCLK)
configuration that would complicate the common implementation.
The common driver is enabled via the SOC_INTEL_COMMON_FEATURE_FINALIZE
Kconfig option.
Platforms that will use this common implementation:
- Meteor Lake
- Panther Lake
Change-Id: I4dd9ccf7e14fecdded92da6bf366e6ff56d866a4
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91227
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.
Changes:
- Remove src/soc/intel/elkhartlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build
The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.
Change-Id: I635347f15e35ec8e69c24edcec8c45c55a496ffd
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.
Changes:
- Remove src/soc/intel/jasperlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build
The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.
Change-Id: Ia039b25b21b4af5912dd5e8af9ef06a66c00a7bd
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.
Changes:
- Remove src/soc/intel/cannonlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build
The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.
Change-Id: If5a70a0e05c50ab893ba8861e200b078982dfad9
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91213
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.
Changes:
- Remove src/soc/intel/tigerlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build
The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.
Change-Id: I1bf9d4eeab0fecbb33d122a32ecdeef85af059fa
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.
Changes:
- Remove src/soc/intel/pantherlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build
The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.
Change-Id: I9bd0dae5bbfc0ec2e9101e848de2037760314456
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.
Changes:
- Remove src/soc/intel/meteorlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build
The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.
Change-Id: I0ad75bbeb1fad7352b2b898487a5b54eff496d0b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific reset.c with the common global reset
implementation using CSE with PMC fallback.
Changes:
- Remove src/soc/intel/alderlake/reset.c
- Enable SOC_INTEL_COMMON_FEATURE_GLOBAL_RESET_CSE_PMC in Kconfig
- Update Makefile.mk to remove reset.c from build
The global reset implementation was identical to 6 other platforms,
making it an ideal candidate for consolidation.
Change-Id: Iebaf5bafd5a97dde37ffc435b2ad8b6a8dcfecd0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
This introduces a common implementation of do_global_reset() that
uses CSE (Converged Security Engine) with PMC (Power Management
Controller) fallback. This implementation is identical across 7
Intel client platforms.
The function attempts to request a global reset from the CSE first,
which is the preferred method. If CSE is unavailable or the request
fails, it falls back to enabling PMC-based global reset and
triggering a full reset.
This consolidates the global reset handling and eliminates duplicate
code across multiple platforms. The common implementation is enabled
via the SOC_INTEL_COMMON_RESET_GLOBAL_RESET_CSE_PMC Kconfig option.
Platforms that will use this common implementation:
- Alder Lake
- Meteor Lake
- Panther Lake
- Tiger Lake
- Cannon Lake
- Jasper Lake
- Elkhart Lake
Change-Id: Ida59bc2df483db5397ee043f66fdee56508bd0df
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91208
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific lockdown.c with the common PMC lockdown
driver.
Changes:
- Remove src/soc/intel/pantherlake/lockdown.c
- Add PMC_FDIS_LOCK_REG define pointing to GEN_PMCON_B in soc/pmc.h
- Enable SOC_INTEL_COMMON_FEATURE_PMC_LOCKDOWN in Kconfig
- Update Makefile.mk to remove lockdown.c from build
Panther Lake uses GEN_PMCON_B for ST_FDIS_LOCK (bit 21), the same
approach as Meteor Lake.
Change-Id: I9becbedbb1bcbc19f60d3ebb024dd5e43c7cee29
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91207
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific lockdown.c with the common PMC lockdown
driver.
Changes:
- Remove src/soc/intel/meteorlake/lockdown.c
- Add PMC_FDIS_LOCK_REG define pointing to GEN_PMCON_B in soc/pmc.h
- Enable SOC_INTEL_COMMON_FEATURE_LOCKDOWN in Kconfig
- Update Makefile.mk to remove lockdown.c from build
Meteor Lake uses GEN_PMCON_B for ST_FDIS_LOCK (bit 21), the same
approach as Panther Lake.
Change-Id: Iecccc482f04d85cfec738dd57dc1473eaf82cfcc
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Replace platform-specific lockdown.c with the common PMC lockdown
driver introduced in the previous commit.
Changes:
- Remove src/soc/intel/alderlake/lockdown.c
- Add PMC_FDIS_LOCK_REG define pointing to ST_PG_FDIS1 in soc/pmc.h
- Enable SOC_INTEL_COMMON_FEATURE_PMC_LOCKDOWN in Kconfig
- Update Makefile.mk to remove lockdown.c from build
Alder Lake uses the ST_PG_FDIS1 register (0x1e20) for ST_FDIS_LOCK,
which differs from newer platforms that use GEN_PMCON_B. This
difference is handled through the PMC_FDIS_LOCK_REG define.
Change-Id: Ic80aca618dcbe5a4fef54f4802e6f4ce6f4ebd44
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91205
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Wildcat Point's GPIOs work the same as Lynx Point LP's GPIOs.
Change-Id: I64963937a5b40bcab605acb826567d63af512427
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91468
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The idea is to use Haswell's acpi.c file in the next commit, and this
little difference affects reproducibility.
Change-Id: Ib2641586fbb9e8ed175eeca0bd665057f5049c0e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Device NVS is only used in southbridge code. This change is
non-reproducible.
Change-Id: I60ce9a80d6e3e0ce0c13037d4caae473d3d092a9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91402
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Device NVS is only used in southbridge code. Also move the platform.asl
file since it is mostly about southbridge stuff.
Tested with BUILD_TIMELESS=1, Purism Librem 15 v2 remains identical.
Change-Id: Ia0d301f6b77f7084a6d1dfe1238693c76c62ef7a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91401
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
