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sb/intel/wildcatpoint/pcie.c: Reorder some steps

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Run some steps a bit earlier for consistency with Lynx Point.

Change-Id: I819f95275b23867c83d0991f1eaab3d2e8947abc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91473
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2026-02-27 23:56:38 +01:00 • committed by Matt DeVillier
commit 2ac2df0eda
1 changed files with 6 additions and 6 deletions
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12
src/southbridge/intel/wildcatpoint/pcie.c
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@ -538,6 +538,12 @@ static void pch_pcie_early(struct device *dev)
pci_and_config8(dev, 0xf5, 0x0f);
if (rp == 1 || rp == 5 || rp == 6)
pci_and_config8(dev, 0xf7, ~0x0c);
/* Set EOI forwarding disable. */
pci_or_config32(dev, 0xd4, 1 << 1);
/* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */
if (CONFIG(PCIEXP_AER))
pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29) | 0x10001);
@ -555,12 +561,6 @@ static void pch_pcie_early(struct device *dev)
/* Enable Relaxed Order from Root Port. */
pci_or_config32(dev, 0x320, 3 << 23);
if (rp == 1 || rp == 5 || rp == 6)
pci_update_config8(dev, 0xf7, ~0xc, 0);
/* Set EOI forwarding disable. */
pci_update_config32(dev, 0xd4, ~0, (1 << 1));
/* Read and write back write-once capability registers. */
pci_update_config32(dev, 0x34, ~0, 0);
pci_update_config32(dev, 0x40, ~0, 0);