We have a hard alignment to LB_ENTRY_ALIGN (4). We check for an
alignment of 4 bytes at the beginning of each lb_record. But since it
was 8 byte aligned, it was also automatically 4 byte aligned.
It therefore wasn't detected by coreboot.
This will break payload implementations that rely on the 8 byte
alignment for this specific struct. But since lb_smmstorev2 has only
been recently updated in commit 5bf88a44e9 ("drivers/smmstore:
Support 64-bit MMIO addresses"), one can only hope that no payloads
were updated to this yet.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ib6171b7d4bd08b8a1559833ddb048644ff082b73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
PcdFirstTimeWakeUpAPsBySipi controls the sequence of IPIs sent to APs
during AP wakeup in UefiCpuPkg. Since coreboot leaves APs parked in
halt loop, SIPI is not enough to wake them up. They need to go through
regular INIT-SIPI-SIPI sequence. Set PcdFirstTimeWakeUpAPsBySipi to
FALSE to cause the MP code in UEFI Payload to send INIT-SIPI-SIPI
sequence, otherwise the APs are not detected in UEFI Payload.
Additionally, after rebasing to the latest UefiCpuPkg, CpuDxe now calls
MpInitLibStartupAllCPUs() while setting up per-CPU exception stacks.
If we leave `PcdFirstTimeWakeUpAPsBySipi` at its default (TRUE), only a
SIPI is issued on the first wake attempt. The APs that coreboot parks in
an HLT loop never acknowledge that SIPI, the DXE driver trips
`ASSERT_EFI_ERROR()` and the UEFI payload reboots straight back into
coreboot. Explicitly set the PCD to FALSE so the INIT-SIPI-SIPI flow is
used and all cores report in.
before:
MpInitLib: Find 1 processors in system.
after:
MpInitLib: Find 4 processors in system.
TEST=edk2 boots cleanly on Star Labs Lite ADL (Intel N200) and
Gigabyte MZ33-AR1; DXE log shows all processors detected.
Change-Id: I299b74892a56894c3e15507b507a50bdf7e59860
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89210
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This change adds support for the TAS2563 codec in the device tree
and enables it based on the fw_config.
BUG=b:451935496
TEST=Build and boot to Android16 with Linux 6.12.52 and check tas2563 audio driver was probed successful.
Change-Id: I924518aab5463ed49bd2341cab0104e6ed3ed14b
Signed-off-by: David Lin <david.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Chiang, Mac <mac.chiang@intel.com>
Enables correct identification of boards using tas2563 speaker amplifier
by SOF Windows drivers.
BUG=b:451935496
TEST=Build and boot to Android16 with Linux 6.12.52 and check tas2563 audio driver was probed successful.
Change-Id: I7dd0276a44ebb9b0712589c28ac017bff1ed5b1a
Signed-off-by: David Lin <david.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89878
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This driver uses the ACPI Device Property interface to generate
the required parameters into the _DSD table format expected by
the kernel.
This was tested on the fatcat/variants/ruby mainboard to ensure
that the SSDT contained the equivalent parameters that are provided
by the current DSDT object.
BUG=b:451935496
TEST=Build and boot to Android16 with Linux 6.12.52 and check tas2563 audio driver was probed successful.
Change-Id: I801ef13937078ca9cfcd3610b1aa8aaedbaf1cf1
Signed-off-by: David Lin <david.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Chiang, Mac <mac.chiang@intel.com>
This patch implements passing a "SerialIoUartDmaEnable" pointer to
FSP-S by parsing the devicetree.
Default (0) means PIO, while 1 means DMA.
Change-Id: Id0acfe0b30899a3019ea7e54067fc06cbc56bab6
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Extract PCIe RP clock configuration logic to a separate function,
following the same refactoring done for Meteor Lake in CB:89790.
Change-Id: I0abc48c066697199acfc7b77ee553e4e8c7b5119
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Extract the logic to configure PCIe RPs' clock source and clock request
signals to a separate function, so that the loop in `pcie_rp_init()` is
easier to reuse to program other PCIe-related settings.
While we're at it, make a few small improvements such as printing which
RP index is missing the clock structure definition as well as using the
`BIT()` macro (which is already used in `pcie_rp_init()`. Also retype a
few variables for the RP index, as it is never bigger than a `uint8_t`,
the type of the return value of the `get_max_pcie_port()` function.
Change-Id: I5583ef863630790cedd901e7bd30f4606f887a04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
The slow battery charging control was split across two locations:
1. Unconditionally enabled in `romstage.c`.
2. Conditionally disabled later in `mainboard.c` for normal boot mode.
This split logic is unnecessary and can be simplified. Battery charging
should only be enabled when the system determines it needs to enter a
low-battery boot mode (`LB_BOOT_MODE_LOW_BATTERY`).
This commit refactors the control flow by:
1. Removing the unconditional `enable_slow_battery_charging()` call from
`romstage.c`.
2. Enabling `slow_battery_charging()` only within `lb_add_boot_mode()`
when the determined boot mode is low-battery.
This ensures charging is managed solely based on the determined boot
mode, confining the control logic to a single location.
BUG=b:457566143
TEST=Able to build and boot google/quenbi. Ensure charging is only
enabled in AP firmware if booted in low-battery mode.
Change-Id: I906d555b9fa4ad2581f598621ea96bda891ff47e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The USB port configuration macros (covering USB 2.0, 3.0, and TCSS) are
currently duplicated across multiple Intel SoC headers.
This patch refactors the definitions into a new, central IA common
header file. Moving these macros to a shared location eliminates
redundant code, simplifies maintenance, and ensures consistency across
platforms.
Specifically, this refactoring allows Intel Meteor Lake (MTL) and
Panther Lake (PTL) to immediately adopt the common definitions.
TEST=Able to build and boot google/kinmen.
Change-Id: I7fb1e4d100c6d72eba0e31f37aa58e6d741ceea6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89984
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add ruby project new supported memory parts in mem_parts_used.txt.
Generate SPD id for this part.
Micron MT62F1G32D2DS-020 WT:D
Samsung K3KL8L80EM-MGCV
BUG=b:446771934
TEST=Use part_id_gen to generate related settings
Change-Id: Ic2710e9a5e59ffecb3fd696c15b944eb58e23f0b
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89886
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Xeons implementation and the common intel implementation are identical
functionality wise so just use the common function.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I0ed42a93444e7cc0d339cf63cec4c4411b5b4f73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Update SX9324 register settings based on tuning values from SEMTECH to
adjust the proximity sensor sensing range to support 5G LTE module.
BUG=b:445338278
TEST=Confirm P sensor function can work and check i2c register settings
on Guren by command # i2cwatch -f -y 14 0x28
Signed-off-by: Joyce Ciou <joyce_ciou@pegatron.corp-partner.google.com>
Change-Id: Ic5e8fe1c67dcdfcfc9a4657b9d859a3b71239858
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89930
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Retrieve SVID/SSID via devicetree and program to HDA device
BUG=b/458444964, b/454824561
TEST="lspci -s 00:1f.3 -x and check value in offset 0x2c-0x2f"
Change-Id: I6bf4b5f2cbce69429daabce83ab11c13272194f4
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89983
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
The code was indexing an array of clock sources using an RP index which
is not correct. As the intent of compliance mode seems to be to set all
clock sources to be free-running, do the same from a different place in
order to avoid potential out-of-bounds accesses.
To preserve original behaviour, exit early from `pcie_rp_init()`. While
this is rather crude, subsequent commits will refactor said function.
Change-Id: I89e6e9f85b7b86b0a74ece88641a378f2c0b599f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89788
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
`cfg[i].clk_req` is a `uint8_t` so use `%u` instead of `%d`.
Change-Id: I6c7a6ecbd2f5b917d44923d0ad6cb331d9bb054c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89789
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Add a mechanism for mainboards to override default values of CFR
objects defined in SoC or common code without duplicating object
metadata.
Mainboards can now declare a simple override table mapping option
names to new default values:
const struct cfr_default_override mb_cfr_overrides[] = {
CFR_OVERRIDE_BOOL("s0ix_enable", false),
CFR_OVERRIDE_ENUM("pciexp_aspm", ASPM_DISABLE),
CFR_OVERRIDE_END
};
The CFR backend checks this table when writing options and uses the
override value if one exists. All other metadata (name, help text,
enum values, flags) comes from the original object.
Change-Id: Ifb3da90d605f2799bf0207ff58d69bee3415ccc2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89933
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some SKUs of pujjoquince have a Bayhub LV2 card reader chip,
therefore enable the corresponding driver for the mainboard.
BUG=b:454252968
TEST=Build FW and checking SD card reader register is correct like
printk(BIOS_INFO, "Luca_0x%x: %x\n", ltr_cap + PCI_LTR_MAX_NOSNOOP,
pci_read_config16(dev, 0x236));.
Change-Id: Ib04a419b86213b6ffef25d7f6f64668abaf36801
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89890
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
In the arm64 exception handler in libpayload, we use the banked
exception stack pointer (SP_EL2, as opposed to the normal SP_EL0) not as
a normal stack pointer, but simply as a pointer to the exception_state
struct. This makes it easy to dump all registers into that struct on
context switch. We then immediately switch back to SP_EL0.
Yet, even though it is not really a stack for us, the aarch64
architecture still requires that SP_EL2 is 16 byte aligned at function
boundaries. If the exception_state struct is not thus aligned,
exceptions are broken. (I don't know why nobody ever hit this before,
but I hit it now while trying to pull in zstd code. I guess we just
don't have unaligned BSS entries that often and simply got lucky for a
while. 3 hours wasted on debugging. :( )
Change-Id: Id19184656fb9da68fe4bfdbc240c0c25b9d24cd6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This chang adds the necessary configuration for ILITEK touchscreen
(ILIT2901) device. The relevant parameters are from the manufacturer's
email dated October 13th. Furthermore, adding fw_config THC_ILITEK
ensures that the touch functionality of both touchscreens is normal.
BUG=b:455442712
TEST=emerge-fatcat coreboot and chromeos-bootimage,
flash to DUT, ilitek touchscreen can be found by `getevent`,
and no wake-up functionality when the DUT is in sleep mode.
Change-Id: I7611c7b1e1364e48ae87a0d91ad3106130ccc586
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add FW_CONFIG probe based on lapis boxster of below devices:
touchpad, audio and touchscreen.
BUG=b:456579786
TEST=Boot to OS and verify the touch and audio device are set
based on fw_config
Change-Id: I6943a0cd6304a6d92481d2904bfa5082944ffd70
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89939
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to ACPI spec, OSPM will not check _STA first and may run the
_ON method repeatedly, even if the resource is already on.
GPIO CNV_BTEN, CNV_BT_IF_SELECT and BT_RESRT_GPIO are already enabled
before entering OS, but OS still try to run method _ON during boot up
process.
Therefore, try to check the GPIO state first to avoid unnecessary
operation and interfere touch enabling sequence.
BUG=b:454848201
TEST="rebuild and dump dsdt to check asl code generate as expected"
Change-Id: I8bd517c3a5ca46c7c8b8ad436af5e4be2295b631
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89849
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To resolve the issue of probabilistic inability to enter s0ix, We need to
1.Add reset_gpio for SSD RTD3 configuration
2.Disable card reader in coreboot
BUG=b:431653999
TEST=dut can successfully enter S0IX during stress test.
Change-Id: I7f8b117f23ca5639a17f2bace634ee84fce08247
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
To resolve the issue of probabilistic inability to enter s0ix, We need to
1.Add reset_gpio for SSD RTD3 configuration
2.Disable card reader in coreboot
Regarding adding reset_gpio for SSD RTD3 configuration
The PCIE SSD PERST part is added in the schematic diagram of the V4 version,
So GPP_F20 needs to be configured on felino, and keeps NC on felino4es.
BUG=b:431653999
TEST=dut can successfully enter S0IX during stress test.
Change-Id: I7dbb8b167fd7d519cd8c148ff7ead328c8c11d81
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Adjust the touchpad I2C frequency to greater than 380 kHz
and less than 400 kHz.
Before:
THC0-I2C - 368KHz
After:
THC0-T2C - 388KHz
BUG=b:456906446
TEST=Rate of the actual measured machine is pass.
Change-Id: I389a1b0f56494694f1d96aa036fd41dff476c074
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Modify camera enable gpio pin from C05 to C06 to enable function.
schematics: RUBY_EVT_0902_2112.pdf
BUG=b:457650397
TEST=Build and boot to OS and check camera function works.
Change-Id: Id4ef314d039298e9cadd69e2faa53e6b9bcf6143
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
LZMA checks at util/cbfstool/lzma/lzma.c:Write() for the output
buffer/stream size and does not write beyond it.
LZ4 checks at src/commonlib/bsd/lz4.c.inc:LZ4_decompress_generic() for
the buffer/stream size and does not write beyond it.
Change-Id: I41298b509b3f5e775bb4000c82c539eefa80c885
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Add the battery design capacity and voltage offsets to the EC
definitons; these will be used by coreboot to calculate the
wattage which it'll use to set PL4.
Change-Id: Id0600ddd8ffaecab6004549ab51b7c06305d3c09
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89925
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This isn't a function change, it just reduces the number of
overrides.
Change-Id: I9178028b40c04fe52f4f549365828005cfe5f8be
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89911
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The featureset of Merlin is common, so adjust the Kconfig options
to avoid having the boards select all of them.
This is not a functional change.
Change-Id: Ie8d7afed750055274cdfde3f2f4f9b70fa47a8b1
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
MAX_CHARGE and FAN aren't available for the Nuvoton EC, so
remove the dependency.
Change-Id: Ie087b1c4503a397621b8fd714564cc082150d7a6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89909
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ASPM option for CPU root ports was guarded against the
SOC supporting CPU root ports. This meant that the option
was visible for boards that didn't utilise the CPU root
ports.
Adjust this to guard against BOARD_STARLABS_STARBOOK_RPL,
which is the only board to actually use the CPU root ports.
Change-Id: Id632a8279e8c1cb07536b4198c3752d57eee657a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89908
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the code that disables the DMIC based on the option table
to the common directory, as it's pretty much the same for all
boards.
Drop the check for the codec ID, as it's pointless.
Change-Id: I55dd8f5f65908f5c4605001893003209f85cb139
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Split the "wireless" option into "WiFi" and "Bluetooth" in CFR
to allow more granular control.
Test=Disable WiFi and Bluetooth in turn and make sure the devices
are disabled independently.
Change-Id: I3f617486c78a89a60a1e8c7c8ab7d157dc20bf2e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89797
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the wireless CFR object to allow users to disable or
enable the built-in wireless.
Change-Id: I8f48bf30429d64980d15d33f9e26164e806c520c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89810
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move all of the CFR object definitons to the common directory
to reduce duplicated code.
Change-Id: I02d486563a01738335a9f1a20b5fcad2b96d6498
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89809
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adjust how the common headers are included, in a more "coreboot"
fashion.
Change-Id: Iaeb8e12272235a51c620656387838be8b0a0a098
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89917
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for the new memory CXMT CXDB5CBAM-MA-B.
BUG=b:451917928
BRANCH=firmware-dedede-13606.B
TEST=Run command
"go run ./util/spd_tools/src/part_id_gen/part_id_gen.go \
JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ \
src/mainboard/google/dedede/variants/pirika/memory/\
mem_parts_used.txt"
And confirm the mainboard boot normally with CXMT
CXDB5CBAM-MA-B memory.
Change-Id: I8e1600ac191fd76b2226605e7a72497823a48105
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Add the ability to set the keyboard backlight level at boot, controlled
by a setup option variable and restricted to devices which actually
have a backlit keyboard.
TEST=tested hooked up to a CFR option 'ec_kb_backlight' (added later in
the patch series) to set the keyboard backlight at boot, with
visibility controlled by backlight presence, on a range of Chromebooks
with and without keyboard backlight support.
Change-Id: I92eed62935d0333f548599860b7bbe22f6b9f2b4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89828
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reduce maximum timeout from 100ms to 20ms for OTG Enablement polling
for USB Type-C.
Avoid OTG enablement polling when in sink mode
BUG=b:455551151
TEST: Verify USB3.0 (SS) works for C0/C1 on Google/Bluey.
Background:
During USB Type-C port initialization, the OTG (On-The-Go) status must
be verified when the port operates in source mode to ensure proper VBUS
power delivery. The previous implementation polled the OTG status
register with a 100ms timeout on all ports regardless of their role.
Previous Implementation Issues:
1. Overly conservative timeout: The 100ms maximum wait significantly
exceeded actual requirements, as OTG enablement consistently
completes in approximately 14ms under normal conditions
2. Inefficient polling logic: OTG status was polled even when ports
operated in sink mode, where OTG functionality is irrelevant since
the port receives rather than provides power
Improvements:
1. Timeout reduction: Decreased maximum polling duration from 100ms to
20ms, maintaining adequate margin (>40% headroom) while reducing boot
time by up to 80ms per sink-mode port
2. Mode-aware polling: Added logic to detect port role and skip OTG
status polling entirely for sink-mode ports, as demonstrated by the
"Primary in SNK mode - skipping OTG status read" log entry
The changes maintain full USB3.0 SuperSpeed functionality while
improving initialization efficiency. The 20ms timeout remains
sufficiently conservative to accommodate normal timing variations.
Debug logs:
[DEBUG] QMP PHY SS0 initialized and locked in 1671us,
phy_status: 0x86868686
[INFO ] Enabling Primary VBUS SuperSpeed
[INFO ] Primary in SNK mode - skipping OTG status read
[INFO ] Primary Type-C Status:
[INFO ] Misc Status (0x2B0B): 0x1a
[INFO ] Src Status (0x2B08): 0x00
[INFO ] Mode Config (0x2B44): 0x00
[INFO ] Interrupt En Cfg 1 (0x2B5E): 0xff
[INFO ] State Machine Status (0x2B09): 0x02
[DEBUG] USB HS PHY initialized for index 3
[DEBUG] QMP-1x16 USB4 DP PHY SS1 init
[DEBUG] QMP PHY SS1 initialized and locked in 1671us,
phy_status: 0x86868686
[INFO ] Enabling Secondary VBUS SuperSpeed
[INFO ] Secondary in SRC mode - OTG Status: 0x02, State: 0x02
(OTG Enabled) - Time: 14 ms
[INFO ] Secondary Type-C Status:
[INFO ] Misc Status (0x2B0B): 0x4b
[INFO ] Src Status (0x2B08): 0x08
[INFO ] Mode Config (0x2B44): 0x00
[INFO ] Interrupt En Cfg 1 (0x2B5E): 0xff
[INFO ] State Machine Status (0x2B09): 0xa6
confirmed that there are no otg polling for sink mode and
polling timeout is reduced to max of 20ms.
Change-Id: I7467248185c9d0526816ac62e1e1a1496440fddc
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This reverts commit 668ea97075.
Let's just keep using --param=min-pagesize=1024 in xcompile to sweep
the -Warray-bounds warnings under the rug in the coreboot tree.
Change-Id: I0f76c27bcbaac9d0927160fcab9cbf9aaefa9095
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89915
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit cfdaff3f70.
Let's just keep using --param=min-pagesize=1024 in xcompile to sweep
the -Warray-bounds warnings under the rug in the coreboot tree.
Change-Id: I875cb140aacd44f1aaddd410de0f154af585b1c1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
