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mb/google/fatcat/var/felino: Disable card reader in coreboot

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To resolve the issue of probabilistic inability to enter s0ix, We need to
1.Add reset_gpio for SSD RTD3 configuration
2.Disable card reader in coreboot

BUG=b:431653999
TEST=dut can successfully enter S0IX during stress test.

Change-Id: I7f8b117f23ca5639a17f2bace634ee84fce08247
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit is contained in:
Tongtong Pan 2025-11-06 11:54:11 +08:00 • committed by Matt DeVillier
commit 0f7c54d7d1
2 changed files with 1 additions and 11 deletions
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2
src/mainboard/google/fatcat/variants/felino/gpio.c
View file

@ -187,7 +187,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_D17: PCH_DMIC_DATA1 */
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
/* GPP_D18: PCIE_CLKREQ_SD_N */
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
PAD_NC(GPP_D18, NONE),
/* GPP_D19: NC */
PAD_NC(GPP_D19, NONE),
/* GPP_D20: NC */

10
src/mainboard/google/fatcat/variants/felino/overridetree.cb
View file

@ -204,16 +204,6 @@ device ref tbt_pcie_rp0 on end
end
end
device ref pcie_rp2 on
# Enable PCH PCIE x1 slot using CLK 6
register "pcie_rp[PCIE_RP(2)]" = "{
.clk_src = 6,
.clk_req = 6,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L1,
}"
end # SD Card
device ref pcie_rp4 on
probe WIFI WIFI_PCIE_6
probe WIFI WIFI_PCIE_7