Generate RAM ID for Kingston B3221XM3BDGVI
DRAM Part Name ID to assign
B3221XM3BDGVI 2 (0010)
BUG=b:420797833
BRANCH=firmware-brya-14505.B
TEST=emerge-constitution coreboot
Change-Id: Ic4f92cb7d597a877b693906dee23e1b277fcf122
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Vbt extracted from coreboot-Google_Pujjoga.15217.834.0.bin.
Pujjoga/Pujjogatwin both use same variant dir/same VBT.
TEST=build/boot pujjoga
Change-Id: Ie2054f53563372e9ce7e6692513340a53c35b565
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88094
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because the pujjolo motherboard p-sensor could not recognize, so
I modify the below changes.
1. Update P-sensor I2C bus from 2 to 3.
2. Copy P-sensor parameters from pujjocento.
BUG=b:395763555
BRANCH=none
TEST=Build and verify on pujjolo
Device list:
cat /sys/bus/iio/devices/iio\:device0/name
sx9324
The value of register 01 when away:
i2cget -f -y 13 0x28 01
0x00
The value of register 01 when approaching:
i2cget -f -y 13 0x28 01
0x01
Change-Id: Ia5685ad790949001da7ba793759eb286b8cce1e8
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88104
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable USB3 related functions like usb-a, wwan, wlan.
BUG=b:395763555
BRANCH=none
TEST=Boot to OS and verify output of lsusb contains:
us 004 Device 002: ID 8564:4100 Transcend Information, Inc. USB3.1 Hub
Bus 004 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 003 Device 003: ID 33f8:01a2 Rolling Wireless S.a.r.l. Rolling RW101R-GL Module
Bus 003 Device 005: ID 093a:2516 Pixart Imaging, Inc. USB OPTICAL MOUSE
Bus 003 Device 004: ID 258a:002a SINO WEALTH Thunderobot KG3089
Bus 003 Device 002: ID 8564:4100 Transcend Information, Inc. USB2.1 Hub
Bus 003 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Change-Id: Ia9cb6a394169530eb660023998dd92d8691a1607
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88062
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add Ax211 wifi card setting to let wifi function work.
BUG=b:395763555
BRANCH=none
TEST=Insert Ax211 wifi card to MB and boot to OS to connect wifi
successfully.
Change-Id: I061ca0ad54bef23861ad8c937cece72902afff47
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88092
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Pujjolo project is going to have single RAM devices,so add single
ram configuration.
BUG=b:395763555
BRANCH=none
TEST=Build and boot to OS. Verify functions work.
Change-Id: I92b0bd1e05276c170d35ce20508cc6f439104442
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88027
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
In some panels, the power supply for the display and the I2C touch
screen comes from the same source. As a result, if the display is not
powered on, the I2C bus will also be unpowered. This leads to a problem
: if the Intel DRM driver has not yet reached the stage where it powers
on the display, the I2C touch screen device integrated into the panel
will remain unpowered as well. A similar issue can also occur after
resuming from s0ix.
In Linux-like systems, the Intel DRM driver and the generic I2C driver
operate independently, so their execution order in the kernel cannot be
guaranteed.
Kernel patchsets link:
https://lore.kernel.org/all/cover.1749199013.git.jani.nikula@intel.com/
Due to the required kernel changes mentioned above, an ACPI device LCD0
needs to be declared under GFX0, and a _DSD declaration must be added
to the I2C touch screen device.
An example that clearly illustrates the required ACPI change:
Scope (\_SB.PCI0.GFX0)
{
...
Device (LCD0)
{
Name (_STA, 0x0F) // _STA: Status
...
}
}
Scope (\_SB.PCI0.I2C1)
{
....
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x02)
{
...
Package (0x02)
{
"panel",
\_SB.PCI0.GFX0.LCD0
}
}
})
}
BUG=b:398703068
TEST=Extracted SSDT contains a required _DSD entry within the I2C1
touchscreen device scope
Cq-Depend: chromium:6626797
Change-Id: I73058851c35a7190d70a51a554cccf21253fc59b
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch creates a new variant `felino4es`.
The new variant will support PTL ES1 samples. This existing `felino`
variant will support ES2 and QS samples.
BUG=b:424355826
TEST=Able to build google/felino4es
Change-Id: I9da7ad9fcdd4467d5b7ab5c31ffba6f3c8b3a943
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88096
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch creates a felino model Kconfig `BOARD_GOOGLE_MODEL_FELINO`
so that different variants can easily select the configs without any
duplication.
This change is made to support `felino` and `felino4es` variants.
BUG=b:424355826
TEST=Able to build google/felino
Change-Id: I38d72eada28734ed26427dbd85ab603cddab258c
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88095
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now we face the suspend could not enter s0ix issue.
So according to the schematics 627075_TWL PCH GPIO_Pujjolo_1th version
_20250527.xlsx to change gpio setting and hook up the SD card reader
via fwconfig to fix the issue.
Change :
1. gpio GPP_D8(SD_CLKREQ_ODL) to native function 1
2. add probe sd card.
BUG=b:422600523
BRANCH=none
TEST=Build and boot to OS. Verify powerd_dbus_suspend could enter S0ix
Change-Id: Iaa5a653608316ca8cb1e34429d30a2ebfdf7a1e9
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88050
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These boards only have 2 DMIC physically connected, and attempting to
record from 4 channels vs 2 results in a large amount of background
noise which drowns out the recording. Selecting the 2 channel DMIC
shows audio on both channels and no noise.
TEST=build/boot octopus variants, test built-in mic under Windows
and Linux.
Change-Id: I70c4b3a8f1ece16cb1c134c6b4c786eb4a685bc5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
These boards only have 2 DMIC physically connected, and attempting to
record from 4 channels vs 2 results in a large amount of background
noise which drowns out the recording. Selecting the 2 channel DMIC
shows audio on both channels and no noise.
TEST=build/boot poppy variants, test built-in mic under Windows
and Linux.
Change-Id: I30d97fa1a25e8cefe05cedac5176bb74dad7f318
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This board only has 2 DMIC physically connected, and attempting to
record from 4 channels vs 2 results in a large amount of background
noise which drowns out the recording. Selecting the 2 channel DMIC
shows audio on both channels and no noise.
TEST=build/boot fizz/karma, test built-in mic under Windows and Linux.
Change-Id: I48162ff25d8c7f413e651c07a7f8e9604bee224c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
These boards only have 2 DMIC physically connected, and attempting to
record from 4 channels vs 2 results in a large amount of background
noise which drowns out the recording. Selecting the 2 channel DMIC
shows audio on both channels and no noise.
TEST=build/boot reef variants, test built-in mic under Windows
and Linux.
Change-Id: Ie7c422f4bd205b0388ee8efea7cf4f3cfa83ef05
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88080
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These boards only have 2 DMIC physically connected, and attempting to
record from 4 channels vs 2 results in a large amount of background
noise which drowns out the recording. Selecting the 2 channel DMIC
shows audio on both channels and no noise.
TEST=build/boot glados variants, test built-in mic under Windows
and Linux.
Change-Id: I68b7d1425c18d070dd75bc42d40ee30701f9704a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Update device tree to support PIXART touchpad.
BUG=b:414734334
TEST=emerge-fatcat coreboot and PIXART touchpad can work well.
Change-Id: I0eaab274e870f45f3cad16805580a968fc4b4aae
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Update device tree to support Synaptics touchpad.
BUG=b:414734334
TEST=emerge-fatcat coreboot and Synaptics touchpad can work well.
Change-Id: I5decb88cc37923e80a619899df66d47ec1579914
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88074
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ocelotmchp is the same as the ocelot variant except that it uses the
Microchip EC.
BUG=b:419857124
BRANCH=none
TEST=`emerge-ocelot coreboot` and verify it builds without error.
Change-Id: I9088a57289d9ef489a7773a8d828d5f945440757
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88060
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ocelotite is the same as the ocelot veriant except that it uses the
ITE EC.
BUG=b:419856369
BRANCH=None
TEST=`emerge-ocelot coreboot` and verify it builds without error.
Change-Id: I1871d5772ea1a73d55d49bdac5b00a17f524eeeb
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88059
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace RSMRST with PLTRST, for the PCH Strap GPIOs. RSMRST introduced
programming errors in cbmem (gpio_pad_reset_config_override: logical
to chipset mapping not found) and broke tablet mode rotation.
Change-Id: Ia2b655450558a9de98ce1a92c93820ab3da57ca0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88053
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ME region is 0x1000 smaller for Twin Lake, so adjust it
accordingly.
Change-Id: I8d4a279597b31f05c6181218c4a07acdfc676920
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Provide a valid GPIO configuration based on the mainboard wiring.
BUG=none
TEST=Checked output of verbose GPIO debug messages.
Change-Id: I75570acf2bb11a99b99fe70b9d639837daee125c
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87913
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DRAM Part Name ID to assign
H58G56CK8BX146 7 (0111)
BUG=b:424334614
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I35aa833372eced9b7906b4c46b9e3389fcb364f5
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88067
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DRAM Part Name ID to assign
H58G56CK8BX146 7 (0111)
BUG=b:424334614
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I9ca77d07908502649f3bc5380071ca1edceba997
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88066
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Alter dram from H9JCNNNCP3MLYR-N6E to H9JCNNNBK3MLYR-N6E
BUG=b:395763555
BRANCH=none
TEST=Could boot to OS.
Change-Id: Id2b024286b3699015be3a25341389db353d1ab8f
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88061
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
GPP_D07 was modified in CB:87806, which resulted in the dut having no camera function. Now we need to restore the configuration of GPP_D07.
BUG=NONE
TEST=emerge-fatcat coreboot and find that the camera function is good.
CB:87806: mb/google/fatcat/var/felino: Modify GPIOs config: I075efda3044ffe45d7db3d225b10e96e084483aa
Change-Id: I085c98753614a0b72f191a863b68990775832c98
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88025
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Create an ocelot model for the various ocelot variants to use.
BUG=b:419857124, b:419856369
BRANCH=none
TEST=`emerge-ocelot coreboot` and verify it compiles without error.
Change-Id: I61e636beb74c3b1ef36e1b9737aefe0b0ef104c5
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Add NANYA NT6AP512T32BL-J1 as id 2, and add NANYA NT6AP1024T32BL-J1
as id 3, resulting in the list below:
DRAM Part Name ID to assign
K4U6E3S4AB-MGCL 0 (0000)
K4UBE3D4AB-MGCL 1 (0001)
MT53E1G32D2NP-046 WT:B 1 (0001)
NT6AP512T32BL-J1 2 (0010)
NT6AP1024F32BL-J1 3 (0011)
BUG=422906387
TEST=Use part_id_gen to generate related settings
Change-Id: Ifd60e629eb606c7ce06f478cf7cc8b8b3ec77f74
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88005
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Update override devicetree based on schematic_1433518.
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I88a3729ff2a61a383a4715a335062310cba01f24
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add the default configuration for fans as seen in the OS with
superiotool.
Change-Id: Iba142c2ad683962ee2c007f387e87adc77352dad
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add early EC space configuration as done in the vendor BIOS.
Change-Id: I058560733e3f5bb8c6df7d5401efad87911d3f4a
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
The R520G6SB server represents the next generation of the M50FCP2UR
Intel Server System, delivering cutting-edge performance and
versatility tailored for demanding data center and enterprise
workloads. Designed as a 2U dual-socket (2S) Birch Stream SP server
system, it integrates advanced features to meet demanding computing,
networking, and AI-driven application requirements.
Tested:
- USB: Front Panel 2 USB ports and 1 USB port on DCSCM
- PCIe: J1_MXIO_SLOT1 ~ J1_MXIO_SLOT5 (with PCIe SATA controller)
- M.2: M2_CN1, M2_CN2
- Mini Display Port
- Flash firmware from BMC's redfish interface (Out-of-band)
Build with Linux payload and Intel proprietary FSP.
Installed with dual Intel® Xeon® 6756E, one Micron 64GB DDR5
RDIMM 4800 and boots to Ubuntu 22.04.5 LTS (6.8.0-57-generic).
Change-Id: I0590c82c9763bd07348bd86b134007ea4ed71d7a
Signed-off-by: Schumi Chu <schumi.chu@mitaccomputing.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87574
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SC513G6 is a high-performance single-socket server motherboard
designed for AI, HPC, cloud, and data center applications.
Featuring Intel® Xeon® 6 Processors(LGA4710) support with up to
350W TDP, it delivers exceptional compute power, high-speed
networking, and versatile storage options in a compact SSI CEB
form factor.
Tested:
- USB: 4 USB ports
- PCIe: PCIE#1, PCIE#2, PCIE#3, PCIE#5 (with PCIe SATA controller,
and PCIE#4 is only available on CPU R1S SKU)
- M.2: M.2#1 and M.2#2
- LAN: 2 RJ45 GbE ports
- Graphic VGA Port
- - Flash firmware from BMC's redfish interface (Out-of-band)
Installed with Intel® Xeon® 6756E and boots to
Ubuntu 22.04.5 LTS (6.8.0-57-generic).
Change-Id: I7b85e8548cfbdf9e52dc1956bd33e829020c052c
Signed-off-by: Schumi Chu <schumi.chu@mitaccomputing.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Update TPM related default values for DRIVER_TPM_I2C_BUS and
TPM_TIS_ACPI_INTERRUPT based on schematic_1433518.
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: Ifbd99265a36602b7d820cc088317579496144c9d
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I29070d871666f42615ba7afae9b9adb07e089fdc
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.
Enable and reset GPIOs are configured as per pin mapping in gpio.c.
BUG=b:391612392 b:421064225
TEST=Run suspend_stress_test on moxie and verify that the device
suspends to S0ix.
Change-Id: I6b2c264fd7244ab84e82919354afb2b49a22177a
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88000
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
FMAP_SECTION_SI_BIOS_START is used to pass host address for UPD
BiosRegionBase. It changes to flash address after:
commit 2efe4df522 ("treewide: Assume FMAP_SECTION_FLASH_START = 0")
Convert FMAP_SECTION_SI_BIOS_START to host address to set
BiosRegionBase.
TESTED=Build and boot on intel/beechnutcity CRB, check boot log with:
[INFO ] BiosRegionBase is set to ff000000
[INFO ] BiosRegionSize is set to 1000000
Change-Id: Ie115bd8e9044455185f82885a306849c509157bb
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87690
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FMAP_SECTION_SI_BIOS_START is used to pass host address for UPD
BiosRegionBase. It changes to flash address after:
commit 2efe4df522 ("treewide: Assume FMAP_SECTION_FLASH_START = 0")
Convert FMAP_SECTION_SI_BIOS_START to host address to set
BiosRegionBase.
TESTED=Build and boot on intel/avenuecity CRB, check boot log with:
[INFO ] BiosRegionBase is set to ff000000
[INFO ] BiosRegionSize is set to 1000000
Change-Id: I92589253915ad88bbb73736e10e7524b6be82499
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87689
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add usb-a port3 setting to let funtion work fine.
BUG=b:395763555
BRANCH=none
TEST=Build and boot to pujjolo. Verify functions work.
Change-Id: I132f34a5c341f64d829bb78be9d400a77889f291
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87998
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add Elan touchscreen setting to let funtion work fine.
BUG=b:395763555
BRANCH=none
TEST=Build and boot to pujjolo. Verify functions work.
Change-Id: I7a6f56d46347f680f80feb691fc5104f8acf3f29
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88021
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Early init is only required for I2C2 since the DDI1 connector type
must be probed in romstage. The other I2C busses aren't used at the
moment and there's no need for early init.
TEST=Display init on amd/birman_plus still works. I2C0, I2C1 and I2C3
are initialized in ramstage after FSPS.
Change-Id: I0491d03464b675d18e42324580c91642aae4e727
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
In the factory setting, when a type-C charger is connected and the
battery is disconnected, it guarantees that the power limits are reduced
to avoid any unexpected shutdown or reset.
Change-Id: Ibe37c303149bbc253c5734664e8f17ee7005aca1
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87959
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
This variant of coreboot pairs with the brtk EC target.
This target enables development of the RTK EC on a Brox device.
BUG=b:421434445
TEST=cros build-packages --board brox coreboot
BRANCH=none
Change-Id: Ieaa3de6c30d0a0978506f23d927a4e96de71b16d
Signed-off-by: Bob Moragues <moragues@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87957
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
