BUG=b:348678529
TEST=on Google Fatcat board. Set the proper CBI fw_config bit(s) and
check that the corresponding GPIO PADs are configured as expected
value accordingly.
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d54
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamirbohra@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch updates the flash map layout to guarantee that the
RW_SECTION_B section starts at a 16MB boundary.
TEST=Successfully builds google/fatcat.
Change-Id: I74ea21a8a4107d438bc03a0da182ea7e991e74bc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Erying is a Chinese manufacturer selling desktop motherboards with
laptop SoCs and custom shim to mount desktop coolers.
Working:
- Serial port (IT8613E 0x3f8)
- All rear USB ports (3.0, 2.0)
- Both HDMI ports
- Realtek GbE NIC
- Internal audio (ALC897/ TGL-H HDMI)
- Environment Controller (SuperIO fan control)
- All SATA ports
- All PCI-E/M.2 ports
- M.2 NGFF WiFi
- PCI-E Resizable BAR (ReBAR)
- VT-x
WIP/Broken:
- PCI-E ASPM (also broken on vendor's FW, clocks are messed up)
- S3/s0ix (also broken on stock, setting 3VSB register didn't help -
system goes to sleep, but RAM loses power)
- DisplayPort on I/O panel (seemingly a simple fix)
- One of USB2 FP connectors, as well as NGFF USB isn't mapped (yet)
- Automatic fan control (IT8613E can't read CPU_TIN at the moment)
Can be flashed using `flashrom -p internal -w build/coreboot.rom`, as
vendor hasn't enabled any protections on SPI chip.
TEST=Flash coreboot build onto the motherboard, install following PCI-E
cards: Radeon RX 7800XT, Kingston KC3000, Optane 900P, Audigy X-Fi.
Power the system up and boot into Windows 10 to check ACPI sanity, then
reboot into Fedora Linux (kernel 6.10.9) and launch 3D application, disk
benchmark, compilation at the same time to check system's stability.
Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e
Signed-off-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add and use a new helper function to determine if a device is
1) a PCIe device
2) it's mark hot-plug capable
Change-Id: I61cc013844024b43808cd2f054310cb6676ba69e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Intel platform boot policy setting blob is linked into FIT table
as an FIT4 entry. It is required for server executing CBnT and/or
PFR without a PCH.
Please refer to chapter 4.6 of the document in below link:
https://www.intel.com/content/dam/www/public/us/en/documents/
guides/fit-bios-specification.pdf
Tool usage:
./util/cbfstool/ifittool -f <binary> -a -n <cbfs name> -t 4 \
-r COREBOOT -s <max table size>
Change-Id: I0f9fc61341430b1a35a44d50b108dcfaf31cd11c
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Li, Jincheng <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84305
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Xeon-SP simics doesn't provide simulation of writable PAM-F
(Programmable Attribute Map) segment and hence coreboot needs to
enable SHADOW_ROM_TABLE_TO_EBDA to write system table pointers to
EBDA (Extended BIOS Data Area).
Change-Id: I216204987ad646a5d1655323d2725cfd3415a2d7
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Use dev_find_all_devices_on_stack() to find the PCI device on a given stack.
That way open coded duplicated code can be dropped and there's no need to call
socket0_get_ubox_busno(), which allows to drop socket0_get_ubox_busno().
In addition it adds PCI multi segment support.
Change-Id: Ib0ed177ae22112a9f2ed32199409d91cb5851ede
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84790
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The newly added enums and struct members will be used by MT8196.
BUG=none
TEST=emerge-corsola coreboot; emerge-geralt coreboot
Change-Id: I32e758cc4244114073606c418a69e0467cdf1039
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84773
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MT8196 has different pmif_spmi_arb and pmif_spi_arb configurations. Move
the common pmif data to a separate file in order to reuse common/pmif.c
as much as possible.
BUG=none
TEST=emerge-corsola coreboot; emerge-geralt coreboot
Change-Id: I24643ce58a57b9cc3c5220bc06a85b141b366eee
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
MT8196 has differenet configurations from other platforms. Make
CAL_TOL_RATE and CAL_MAX_VAL as per SoC configuration in order to reuse
common/pmif_clk.c
BUG=none
TEST=emerge-corsola coreboot; emerge-geralt coreboot
Change-Id: Iefc8180e1719d9796df7457b619a8792ceb762b2
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84771
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This enables SOC_INTEL_DEBUG_CONSENT to set PlatformDebugOption
to Trace Ready to have the safe configurations for Panther Lake
ES SoC.
This safe configuration will be removed once the feature is fully
verified and safe to be set to the default value.
BUG=b:373915085
TEST=Build fatcat and check the platform boots without an issue.
Change-Id: I1eaabcb2e2aaff16ee4e64d1c7709b229de18459
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84823
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Fix the following error when including device/pciexp.h
src/include/device/pciexp.h: In function 'pciexp_is_downstream_port':
src/include/device/pciexp.h:42:24: error: 'PCI_EXP_TYPE_ROOT_PORT' undeclared (first use in this function)
42 | return type == PCI_EXP_TYPE_ROOT_PORT ||
by including pci_def.h.
Change-Id: Idfd36301a5e766bbe97c93afef88c97507a4c4dc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84791
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adjust the DSM to return 0x00 (unsupported) when no reset gpio
is passed to the driver. Leave the _RST method to comply with
the ACPI specification but omit the BTRT method as it won't do
anything.
Change-Id: I9f8e98fb4f5a22b2f7617b131a3d71cf90f5bc80
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
If project set configure_ext_fivr = 0 will cause
PchFivrVccstIccMaxControl do not set correctly.
BUG=b:361831628
TEST=Verified on Teliks360 that affected DUTs.
Change-Id: I816de9c0c507aad3b73ab29e9f72048704f4662d
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84812
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Alder Lake, Meteor Lake and Panther Lake use the effective way size
when setting up the Enhanced No-Eviction Mode (cf.
`INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE').
BUG=b:360332771
TEST=Verified on PTL Intel reference platform
Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83947
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
On Alder Lake, Meteor Lake and Panther Lake platforms the way size to
consider for NEM+ computation is the effective way size.
On Alder Lake, the External Design Specification #627270 "3.5.2
No-Eviction Mode (NEM) Sizes" provides a way to compute the effective
way size by reading the number of CBO. Unfortunately, reading the
number of CBO is not possible on Meteor Lake and Panther
Lake. Therefore, we instead compute the effective way size as the
biggest of power of two of the way size which works across all three
platforms.
The Kconfig `INTEL_CAR_ENEM_USE_EFFECTIVE_WAY_SIZE' is introduced to
control this behavior.
The issue addressed by this commit can be observed with the following
experiment: using a 18 MB LLC SKU, set `DCACHE_RAM_SIZE` to
0x400000 (4 MB).
The number of ways that used to be computed is round(0x400000 /
0x180000) = round(2.66) = 3. 3 ways were mapped to cover the 0x400000
NEM+ region. When the bootblock code accesses memory between 3 MB and
4 MB, the core would raise a page fault exception.
The right computation is: 0x400000 / eff_way_size(0x180000) = 4. 4
ways needs to be mapped to cover the entire 0x400000 NEM+ region.
BUG=b:360332771
TEST=Verified on PTL Intel reference platform
Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This disables C1 state auto-demotion to run the coreboot with
Panther Lake ES SoC without an issue.
This configuration will be remove later once the related features
are fully verified.
BUG=b:373915085
TEST=Build fatcat and check the platform boots without an issue.
Change-Id: I384dba2918cfd04deb90284513c204fa8c21094b
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84767
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
There is no ACPI power resource for LTE module Rolling RW101R-GL,
therefore implement the power sequence of power-on, power-off, and
reset timing from GPIO init, bootstate init callbacks, and smihandler
function.
BUG=b:368450447
BRANCH=None
TEST= Build firmware and verify on jubilant with LTE:RW101R-GL.
Measure the power on, power off, and reset timing.
Run warm boot, cold boot and suspend/resume to make sure
WWAN devcie is workable.
Change-Id: I4a205e3db777c7c225d31b6cc802883fd7167089
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Update jubilant CPU PL4 from 9 watt to 14 watt for critical battery
boot. The maximum peak power is set at 14 watt which is 45W multiplied
by 32% efficiency.
Overriding power limits for AC power without battery:
PL1 (15000, 18000)
PL2 (41000, 41000)
PL4 (14)
BUG=b:364441688
BRANCH=None
TEST=Able to successfully boot on jubilant SKU1 and SKU2 with AC only.
Test on AC 65W and 45W w/o battery, and check PL4 values from log.
Change-Id: Id1e58797206a61d241f48b057b304e05c9c323d9
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84784
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
NAU8318 supports beep function via GPIO control. Configure the
GPIO pins and pass them to the payload.
BUG=b:343143718
TEST=Verify beep function through CLI in depthcharge successfully.
We can test with:
firmware-shell: badusbbeep
firmware-shell: devbeep
Change-Id: I79277bc1947dab517dea5aba583c5b4e0ac81bc4
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84693
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no powering-on control in the fingerprint kernel driver. The
fingerprint team of ChromeOS suggests powering-on FP MCU in the FW.
Follow trogdor to pull down FP_RST_1V8_S3_L, AP_FP_FW_UP_STRAP,
EN_PWR_FP and pull up EN_PWR_FP in ramstage for power rail to be stable.
BUG=b:340401582
TEST=measure waveform and the fingerprint works on ChromeOS
Change-Id: I05600d90fdf922faeb778a36d8a08f68c1bb4125
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84692
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Configure GPIO EINT28 (XHCI_INIT_DONE) as output, so that payloads
(for example depthcharge) can assert it to notify EC to enable USB VBUS.
BUG=b:317009620
TEST=emerge-rauru coreboot
Change-Id: I5950974435b56997626886b16d371cd8e6472e3c
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84691
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
N-1 IBL (Integrated Boot Logic) codes are initially forked from
EBG (Emmitsburg PCH) codes (src/soc/intel/xeon_sp/ebg). N-1 IBL
codes are a set of stub codes to fulfill build sanity check for GNR
SoC and CRB codes before the formal codes are published.
Change-Id: I6bd5a2ed973ff91750c5ed1f9a57d30e41d8b97e
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Create the francka variant of the fatcat reference board.
BUG=b:370666276
TEST=util/abuild/abuild -p none -t google/fatcat -x -a
make sure the build includes GOOGLE_FRANCKA
Change-Id: I372f445f7007d0d33020545a8febbce27c260e41
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84769
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the GPIO pad configuration to be performed before memory is set up
along with the relevant devices definition.
This patch includes:
- FW config for pre-mem GPIO PAD configuration
- Add overridetree changes used by pre-mem FW config
BUG=b:348678529
TEST=Boot on Google Fatcat board. Note this cannot be tested by itself
directly. Test with CL:84408, set the proper CBI fw_config bit(s) and
check that the corresponding GPIO PADs are configured as expected value
accordingly.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Iac1f637c21a9818512b224dc4cbe4a75dbc516ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84718
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Create the telith variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0)
BUG=372506691
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_TELITH
Change-Id: I4971b9691d3dd293ca640795967c36472afef9c9
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84759
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
The document was moved. The current URL gives a 404.
Change-Id: If6ca74a8bf47382100da048667976958961b9320
Signed-off-by: Daniel Maslowski <info@orangecms.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Add support for Arm Neoverse N2 Reference design.
Based on Arm Neoverse N2 reference design
Revision: Release D
TEST=Build Arm Neoverse N2 & make sure there is no error.
Change-Id: I17908d3ce773d4a88924bafb1d0e9e2a043c7fbc
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add the BMC and all PCIe slots that the board implements.
There are 32 RSSDs and 2 M.2 slots.
Change-Id: Id7d72990d6997d1e8b9ce75477ce3dc571c99839
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The current panel brightness is only 360 nits. Adjust the power and
gamma to optimize the panel brightness. The brightness after adjustment
is 390 nits.
BUG=b:320892589
TEST=boot ciri with IVO_T109NW41 panel and see firmware screen
BRANCH=geralt
Change-Id: I760c37bf915bb40ad2efa7c947034cb168938f2a
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84758
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The spec tells us to clear the busy bit manually after a timeout. Do
that and wait immediately, to detect further issues early. Also fix
some related comments and prints: Failures shouldn't be debug messa-
ges. And we are talking to the PIO interface of the controller, not
the codec. So this was never about the codec being ready.
Change-Id: I4b737f8259157c01bfcd9e6631cc15d39c653d06
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83592
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
