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soc/intel/alderlake_n: Fix display flicker issue when using internal FIVR

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If project set configure_ext_fivr = 0 will cause
PchFivrVccstIccMaxControl do not set correctly.

BUG=b:361831628
TEST=Verified on Teliks360 that affected DUTs.

Change-Id: I816de9c0c507aad3b73ab29e9f72048704f4662d
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84812
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
This commit is contained in:
Simon Yang 2024-10-20 17:54:02 +08:00 • committed by Subrata Banik
commit 5775ed215e
1 changed files with 9 additions and 9 deletions
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18
src/soc/intel/alderlake/fsp_params.c
View file

@ -1200,6 +1200,15 @@ static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,
static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_alderlake_config *config)
{
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
/* Enable the FIVR VCCST ICCMax Control for ADL-N.
* TODO:Right now the UPD is update in partial headers for only ADL-N and when its
* updated for ADL-P then we will remove the config since this needs to be enabled for
* all the Alderlake platforms.
*/
s_cfg->PchFivrVccstIccMaxControl = 1;
#endif
/* PCH FIVR settings override */
if (!config->ext_fivr_settings.configure_ext_fivr)
return;
@ -1234,15 +1243,6 @@ static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg,
s_cfg->PchFivrExtVnnRailIccMaximum =
config->ext_fivr_settings.vnn_icc_max_ma;
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
/* Enable the FIVR VCCST ICCMax Control for ADL-N.
* TODO:Right now the UPD is update in partial headers for only ADL-N and when its
* updated for ADL-P then we will remove the config since this needs to be enabled for
* all the Alderlake platforms.
*/
s_cfg->PchFivrVccstIccMaxControl = 1;
#endif
}
static void fill_fsps_fivr_rfi_params(FSP_S_CONFIG *s_cfg,