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soc/intel/xeon_sp: Allow Memory POR independent of RMT

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TEST=Build & boot in IBM SBP1 system. Verified the settings are effective in FSP logs.

Change-Id: I4341ead89a2683f64c834a6981ba316fcfef4f9a
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84741
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Naresh Solanki 2024-10-11 22:51:38 +05:30 • committed by Martin L Roth
commit 1d18513ad5
2 changed files with 3 additions and 4 deletions
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3
src/soc/intel/xeon_sp/spr/Kconfig
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@ -174,10 +174,9 @@ config ENABLE_RMT
Enable Rank Margining Tool. This option is intended for debugging and
validation and should normally be disabled.
config RMT_MEM_POR_FREQ
config MEM_POR_FREQ
bool "Enforce Plan Of Record restrictions for DDR5 frequency and voltage"
default n
depends on ENABLE_RMT
help
When RMT is enabled. Select this option to enforce Intel Plan Of Record(POR)
restriction on DDR5 frequency & voltage settings.

4
src/soc/intel/xeon_sp/spr/romstage.c
View file

@ -241,9 +241,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
mupd->FspmConfig.serialDebugMsgLvl = 0x3;
mupd->FspmConfig.AllowedSocketsInParallel = 0x1;
mupd->FspmConfig.EnforcePopulationPor = 0x1;
if (CONFIG(RMT_MEM_POR_FREQ))
mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0;
}
if (CONFIG(MEM_POR_FREQ))
mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0;
/* SPR-FSP has no UPD to disable HDA, so do it manually here... */
if (!is_devfn_enabled(PCH_DEVFN_HDA))