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mb/erying: Add Erying Polestar G613 Pro (TGL-H)

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Erying is a Chinese manufacturer selling desktop motherboards with
laptop SoCs and custom shim to mount desktop coolers.

Working:
- Serial port (IT8613E 0x3f8)
- All rear USB ports (3.0, 2.0)
- Both HDMI ports
- Realtek GbE NIC
- Internal audio (ALC897/ TGL-H HDMI)
- Environment Controller (SuperIO fan control)
- All SATA ports
- All PCI-E/M.2 ports
- M.2 NGFF WiFi
- PCI-E Resizable BAR (ReBAR)
- VT-x

WIP/Broken:
- PCI-E ASPM (also broken on vendor's FW, clocks are messed up)
- S3/s0ix (also broken on stock, setting 3VSB register didn't help -
  system goes to sleep, but RAM loses power)
- DisplayPort on I/O panel (seemingly a simple fix)
- One of USB2 FP connectors, as well as NGFF USB isn't mapped (yet)
- Automatic fan control (IT8613E can't read CPU_TIN at the moment)

Can be flashed using `flashrom -p internal -w build/coreboot.rom`, as
vendor hasn't enabled any protections on SPI chip.

TEST=Flash coreboot build onto the motherboard, install following PCI-E
cards: Radeon RX 7800XT, Kingston KC3000, Optane 900P, Audigy X-Fi.
Power the system up and boot into Windows 10 to check ACPI sanity, then
reboot into Fedora Linux (kernel 6.10.9) and launch 3D application, disk
benchmark, compilation at the same time to check system's stability.

Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e
Signed-off-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Alicja Michalska 2024-03-01 15:09:27 +01:00 • committed by Angel Pons
commit a890da52ef
15 changed files with 837 additions and 0 deletions
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17
src/mainboard/erying/Kconfig Normal file
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## SPDX-License-Identifier: GPL-2.0-only
if VENDOR_ERYING
choice
prompt "Mainboard model"
source "src/mainboard/erying/*/Kconfig.name"
endchoice
source "src/mainboard/erying/*/Kconfig"
config MAINBOARD_VENDOR
default "Erying"
endif # VENDOR_ERYING

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src/mainboard/erying/Kconfig.name Normal file
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## SPDX-License-Identifier: GPL-2.0-only
config VENDOR_ERYING
bool "Erying"

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src/mainboard/erying/tgl/Kconfig Normal file
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## SPDX-License-Identifier: GPL-2.0-only
if BOARD_ERYING_POLESTAR_G613_PRO
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
select SOC_INTEL_TIGERLAKE
select SOC_INTEL_TIGERLAKE_PCH_H
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SOC_INTEL_COMMON_BLOCK_MEMINIT
select INTEL_GMA_HAVE_VBT
select HAVE_ACPI_TABLES
select SUPERIO_ITE_IT8613E
select DRIVERS_UART_8250IO
select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE
select HAVE_INTEL_PTT
select CRB_TPM
config MAINBOARD_SMBIOS_PRODUCT_NAME
default "POLESTAR G613 Pro"
config MAINBOARD_DIR
default "erying/tgl"
config MAINBOARD_PART_NUMBER
default "TigerLake (mATX)"
config CBFS_SIZE
default 0xA00000
config USE_PM_ACPI_TIMER
default n
config USE_LEGACY_8254_TIMER
default y
config PCIEXP_ASPM
default n
config PCIEXP_CLK_PM
default n
config PCIEXP_L1_SUB_STATE
default n
endif

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src/mainboard/erying/tgl/Kconfig.name Normal file
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## SPDX-License-Identifier: GPL-2.0-only
config BOARD_ERYING_POLESTAR_G613_PRO
bool "Polestar G613 Pro (TGL-H)"

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src/mainboard/erying/tgl/Makefile.mk Normal file
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## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += bootblock.c
romstage-y += romstage_fsp_params.c
ramstage-y += ramstage.c

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src/mainboard/erying/tgl/board_info.txt Normal file
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Board name: Erying Polestar G613 Pro
Release year: 2022
Category: desktop
ROM IC: W25Q128FV
ROM package: SOIC-8
ROM socketed: no
Flashrom support: yes

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src/mainboard/erying/tgl/bootblock.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8613e/it8613e.h>
#include <gpio.h>
#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO)
#define UART_DEV PNP_DEV(0x2e, IT8613E_SP1)
void bootblock_mainboard_early_init(void)
{
ite_reg_write(GPIO_DEV, 0x29, 0xc1); /* 3VSB - RAM loses power in S3 anyway */
ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* disable k8 power seq */
ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE);
}

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src/mainboard/erying/tgl/cmos.layout Normal file
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# SPDX-License-Identifier: GPL-2.0-only
entries
0 384 r 0 reserved_memory
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# RTC_CLK_ALTCENTURY
400 8 r 0 century
412 4 e 6 debug_level
416 1 e 2 me_state
417 3 h 0 me_state_counter
984 16 h 0 check_sum
enumerations
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
checksums
checksum 408 983 984

BIN
src/mainboard/erying/tgl/data.vbt Normal file
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src/mainboard/erying/tgl/devicetree.cb Normal file
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chip soc/intel/tigerlake
# Power limits/thermals - adjust according to your needs, but beware of VRM cooling!
# H_6_CORE means Core i5, H_8_CORE means Core i7 or i9. Stock PL1/PL2: 45/109W.
register "power_limits_config[POWER_LIMITS_H_6_CORE]" = "{
.tdp_pl1_override = 45,
.tdp_pl2_override = 109,
}"
register "power_limits_config[POWER_LIMITS_H_8_CORE]" = "{
.tdp_pl1_override = 45,
.tdp_pl2_override = 109,
}"
register "tcc_offset" = "8"
# FSP configuration
register "eist_enable" = "1"
register "enable_c6dram" = "1"
register "deep_s3_enable_ac" = "1"
register "deep_s3_enable_dc" = "1"
register "deep_s5_enable_ac" = "1"
register "deep_s5_enable_dc" = "1"
# PME routing
register "pmc_gpe0_dw0" = "PMC_GPP_R"
register "pmc_gpe0_dw1" = "PMC_GPP_B"
register "pmc_gpe0_dw2" = "PMC_GPP_D"
# FiVR External Rails
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
.v1p05_enable_bitmap = 0,
.vnn_enable_bitmap = 0,
.v1p05_supported_voltage_bitmap = 0,
.vnn_supported_voltage_bitmap = 0,
.v1p05_icc_max_ma = 500,
.vnn_sx_voltage_mv = 1050,
}"
device cpu_cluster 0 on end
device domain 0 on
device ref igpu on
register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP" # DP
register "DdiPortBHpd" = "1"
register "DdiPortBDdc" = "1"
register "DdiPortCHpd" = "1" # HDMI
register "DdiPortCDdc" = "1"
register "DdiPort1Hpd" = "1" # HDMI
register "DdiPort1Ddc" = "1"
end
device ref peg0 on # SoC M.2 (Gen4)
register "PcieClkSrcUsage[2]" = "0x40"
register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED"
end
device ref peg1 on # SoC x16 (Gen4)
register "PcieClkSrcUsage[0]" = "0x41"
register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
end
device ref north_xhci on
register "TcssXhciEn" = "1"
end
device ref south_xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC_SKIP), /* Rear, bottom right */
[1] = USB2_PORT_MID(OC_SKIP), /* Rear, bottom left */
[2] = USB2_PORT_MID(OC_SKIP), /* NIC left */
[3] = USB2_PORT_MID(OC_SKIP), /* NIC right */
[4] = USB2_PORT_MID(OC_SKIP), /* Front Panel 1 */
[5] = USB2_PORT_MID(OC_SKIP), /* Front Panel 2 */
[8] = USB2_PORT_MID(OC_SKIP), /* Front Panel 1 (USB3) */
[9] = USB2_PORT_MID(OC_SKIP), /* Front Panel 2 (USB3) */
[10] = USB2_PORT_MID(OC_SKIP), /* Rear, top left */
[11] = USB2_PORT_MID(OC_SKIP), /* Rear, top right */
}"
register "usb3_ports" = "{
[0] = USB3_PORT_DEFAULT(OC_SKIP), /* Rear, bottom right */
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* Rear, bottom left */
[2] = USB3_PORT_DEFAULT(OC_SKIP), /* Front Panel 1 */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* Front Panel 2 */
[4] = USB3_PORT_DEFAULT(OC_SKIP), /* Rear, top left */
[5] = USB3_PORT_DEFAULT(OC_SKIP), /* Rear, top right */
}"
end
device ref shared_ram on end
device ref sata on
register "SataPortsEnable" = "{
[0] = 1,
[1] = 1,
[2] = 1,
[3] = 1,
}"
register "SataPortsDevSlp" = "{
[0] = 1,
[1] = 1,
[2] = 1,
[3] = 1,
}"
register "SataSalpSupport" = "1"
end
device ref pcie_rp5 on # PCH M.2 (Gen3)
register "PcieRpSlotImplemented[4]" = "1"
register "PcieClkSrcUsage[4]" = "4"
register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED"
end
device ref pcie_rp9 on # PCH NGFF (WiFi)
register "PcieRpSlotImplemented[8]" = "1"
register "PcieClkSrcUsage[5]" = "8"
register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
end
device ref pcie_rp11 on # RTL8111 GbE
register "PcieClkSrcUsage[3]" = "10"
register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED"
end
device ref pcie_rp12 on # PCH x1 (Gen3)
register "PcieRpSlotImplemented[11]" = "1"
register "PcieClkSrcUsage[1]" = "11"
register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"
end
device ref pch_espi on
chip superio/ite/it8613e
device pnp 2e.0 off end
device pnp 2e.1 on # COM 1
io 0x60 = 0x3f8
irq 0x70 = 4
irq 0xf0 = 1
end
device pnp 2e.4 on # Environment Controller
io 0x60 = 0xa30
io 0x62 = 0xa20
irq 0x70 = 0x00
irq 0xf4 = 0xe0
irq 0xf5 = 0x00
irq 0xf6 = 0xf0
register "TMPIN1.mode" = "THERMAL_DIODE"
register "TMPIN2.mode" = "THERMAL_DIODE"
register "FAN2.mode" = "FAN_SMART_AUTOMATIC" # CPU_FAN
register "FAN3.mode" = "FAN_SMART_AUTOMATIC" # SYS_FAN
register "FAN2.smart.tmpin" = "1"
register "FAN2.smart.tmp_off" = "35"
register "FAN2.smart.tmp_start" = "42"
register "FAN2.smart.tmp_full" = "72"
register "FAN2.smart.tmp_delta" = "2"
register "FAN2.smart.pwm_start" = "26"
register "FAN2.smart.slope" = "24"
register "FAN3.smart.tmpin" = "1"
register "FAN3.smart.tmp_off" = "35"
register "FAN3.smart.tmp_start" = "42"
register "FAN3.smart.tmp_full" = "72"
register "FAN3.smart.tmp_delta" = "2"
register "FAN3.smart.pwm_start" = "26"
register "FAN3.smart.slope" = "24"
end
device pnp 2e.5 off end
device pnp 2e.6 off end
device pnp 2e.7 on # GPIO
irq 0x2d = 0x02
io 0x60 = 0xa10
io 0x62 = 0xa00
irq 0x70 = 0x00
irq 0x71 = 0x01
irq 0xbc = 0xc0
irq 0xbd = 0x03
irq 0xc1 = 0x02
irq 0xc8 = 0x00
irq 0xc9 = 0x02
irq 0xda = 0xb0
irq 0xdb = 0x44
end
device pnp 2e.a off end # CIR
end
end
device ref p2sb hidden end
device ref hda on
subsystemid 0x10ec 0x3000
register "PchHdaAudioLinkHdaEnable" = "1"
end
device ref smbus on end
end
chip drivers/crb
device mmio 0xfed40000 on end
end
end

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src/mainboard/erying/tgl/dsdt.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725
)
{
#include <acpi/dsdt_top.asl>
#include <soc/intel/common/block/acpi/acpi/platform.asl>
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Device (\_SB.PCI0)
{
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/tigerlake/acpi/southbridge.asl>
#include <soc/intel/tigerlake/acpi/tcss.asl>
}
#include <southbridge/intel/common/acpi/sleepstates.asl>
}

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/gpio.h>
static const struct pad_config gpio_table[] = {
/* ------- GPIO Community 0 ------- */
/* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A0, NATIVE, DEEP, NF1), // ESPI_IO0
PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), // ESPI_IO1
PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), // ESPI_IO2
PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), // ESPI_IO3
PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), // ESPI_CS0#
PAD_CFG_NF(GPP_A5, NATIVE, DEEP, NF1), // ESPI_CLK
PAD_CFG_NF(GPP_A6, NATIVE, DEEP, NF1), // ESPI_RESET#
PAD_CFG_NF(GPP_A7, NATIVE, DEEP, NF1), // ESPI_CS1#
PAD_CFG_NF(GPP_A8, UP_20K, DEEP, NF1), // ESPI_CS2#
PAD_CFG_NF(GPP_A9, UP_20K, DEEP, NF1), // ESPI_CS3#
PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1), // ESPI_ALERT0#
PAD_CFG_NF(GPP_A11, UP_20K, DEEP, NF1), // ESPI_ALERT1#
PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), // ESPI_ALERT2#
PAD_CFG_NF(GPP_A13, DN_20K, DEEP, NF1), // ESPI_ALERT3#
_PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */
/* ------- GPIO Group GPP_R ------- */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
PAD_NC(GPP_R5, NONE),
_PAD_CFG_STRUCT(GPP_R6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */
_PAD_CFG_STRUCT(GPP_R7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */
_PAD_CFG_STRUCT(GPP_R8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* n/a */
PAD_CFG_NF(GPP_R9, NATIVE, DEEP, NF1), // PCIE_LNK_DOWN
PAD_CFG_NF(GPP_R10, NATIVE, DEEP, NF1), // ISH_UART0_RTS#
PAD_CFG_NF(GPP_R11, NATIVE, DEEP, NF1), // SX_EXIT_HOLDOFF#
_PAD_CFG_STRUCT(GPP_R12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CLKOUT_48 */
_PAD_CFG_STRUCT(GPP_R13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* ISH_GP7 */
PAD_NC(GPP_R14, NONE),
PAD_NC(GPP_R15, NONE),
PAD_NC(GPP_R16, NONE),
PAD_NC(GPP_R17, NONE),
PAD_CFG_GPO(GPP_R18, 1, PLTRST), /* GPIO */
PAD_NC(GPP_R19, NONE),
/* ------- GPIO Group GPP_B ------- */
PAD_CFG_GPO(GPP_B0, 1, PLTRST), /* GPIO */
PAD_NC(GPP_B1, NONE),
PAD_NC(GPP_B2, NONE),
PAD_NC(GPP_B3, NONE),
PAD_NC(GPP_B4, NONE),
PAD_NC(GPP_B5, NONE),
PAD_NC(GPP_B6, NONE),
PAD_NC(GPP_B7, NONE),
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // SRCCLKREQ3
PAD_NC(GPP_B9, NONE),
PAD_NC(GPP_B10, NONE),
PAD_CFG_GPO(GPP_B11, 1, DEEP), /* GPIO */
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_NC(GPP_B13, NONE),
PAD_NC(GPP_B14, NONE),
PAD_NC(GPP_B15, NONE),
PAD_NC(GPP_B16, NONE),
PAD_NC(GPP_B17, NONE),
PAD_NC(GPP_B18, NONE),
PAD_NC(GPP_B19, NONE),
_PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GSPI1_CLK */
_PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* GSPI1_MISO */
_PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* GSPI1_MOSI */
PAD_CFG_GPO(GPP_B23, 1, PLTRST), /* GPIO */
/* ------- GPIO Community 1 ------- */
/* ------- GPIO Group GPP_D ------- */
PAD_NC(GPP_D0, NONE),
PAD_NC(GPP_D1, NONE),
PAD_NC(GPP_D2, NONE),
PAD_NC(GPP_D3, NONE),
_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML1CLK */
_PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CNV_RF_RESET# */
_PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* MODEM_CLKREQ */
PAD_NC(GPP_D7, NONE),
PAD_NC(GPP_D8, NONE),
_PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML0CLK */
_PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML0DATA */
PAD_CFG_GPO(GPP_D11, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_D12, 1, PLTRST), /* GPIO */
PAD_NC(GPP_D13, NONE),
PAD_NC(GPP_D14, NONE),
_PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SML1DATA */
PAD_NC(GPP_D16, NONE),
PAD_NC(GPP_D17, NONE),
PAD_NC(GPP_D18, NONE),
PAD_NC(GPP_D19, NONE),
PAD_NC(GPP_D20, NONE),
PAD_NC(GPP_D21, NONE),
PAD_NC(GPP_D22, NONE),
PAD_NC(GPP_D23, NONE),
/* ------- GPIO Group GPP_C ------- */
_PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SMBCLK */
_PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SMBDATA */
PAD_CFG_GPO(GPP_C2, 1, PLTRST), /* GPIO */
_PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C2_SDA */
_PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C2_SCL */
PAD_CFG_GPO(GPP_C5, 0, DEEP), /* GPIO */
_PAD_CFG_STRUCT(GPP_C6, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* I2C3_SDA */
_PAD_CFG_STRUCT(GPP_C7, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* I2C3_SCL */
PAD_NC(GPP_C8, NONE),
PAD_NC(GPP_C9, NONE),
PAD_NC(GPP_C10, NONE),
PAD_NC(GPP_C11, NONE),
PAD_CFG_GPO(GPP_C12, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_C13, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_C14, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_C15, 1, PLTRST), /* GPIO */
_PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* I2C0_SDA */
_PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* I2C0_SCL */
_PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* I2C1_SDA */
_PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* I2C1_SCL */
PAD_NC(GPP_C20, NONE),
PAD_NC(GPP_C21, NONE),
PAD_NC(GPP_C22, NONE),
PAD_NC(GPP_C23, NONE),
/* ------- GPIO Group GPP_S ------- */
_PAD_CFG_STRUCT(GPP_S0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SNDW1_CLK */
_PAD_CFG_STRUCT(GPP_S1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SNDW1_DATA */
_PAD_CFG_STRUCT(GPP_S2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SNDW2_CLK */
_PAD_CFG_STRUCT(GPP_S3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SNDW2_DATA */
_PAD_CFG_STRUCT(GPP_S4, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DMIC_CLKA1 */
_PAD_CFG_STRUCT(GPP_S5, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DMIC_DATA1 */
_PAD_CFG_STRUCT(GPP_S6, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DMIC_CLKA0 */
_PAD_CFG_STRUCT(GPP_S7, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DMIC_DATA0 */
/* ------- GPIO Group GPP_G ------- */
PAD_NC(GPP_G0, NONE),
PAD_CFG_GPO(GPP_G1, 0, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_G2, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_G3, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_G4, 1, PLTRST), /* GPIO */
_PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* SLP_DRAM# */
PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_G7, 1, PLTRST), /* GPIO */
_PAD_CFG_STRUCT(GPP_G8, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP3_CTRLCLK */
_PAD_CFG_STRUCT(GPP_G9, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP3_CTRLDATA */
_PAD_CFG_STRUCT(GPP_G10, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP4_CTRLCLK */
_PAD_CFG_STRUCT(GPP_G11, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP4_CTRLDATA */
_PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP1_CTRLCLK */
_PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP1_CTRLDATA */
_PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP2_CTRLCLK */
_PAD_CFG_STRUCT(GPP_G15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE)), /* DDP2_CTRLDATA */
/* ------- GPIO Community 2 ------- */
/* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), /* BATLOW# */
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* ACPRESENT */
PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* LAN_WAKE# */
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* PWRBTN# */
PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S3# */
PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_S4# */
PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* SLP_A# */
PAD_CFG_GPO(GPD7, 0, PWROK), /* GPIO */
PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK */
PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_WLAN# */
PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* SLP_S5# */
PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */
PAD_NC(GPD12, NONE), /* GPIO */
/* ------- GPIO Community 3 ------- */
/* ------- GPIO Group GPP_E ------- */
PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATAXPCIE0 */
PAD_CFG_NF(GPP_E1, NONE, PLTRST, NF1), /* SATAXPCIE1 */
PAD_CFG_GPO(GPP_E2, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_E3, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_E4, 1, PLTRST), /* SATA_DEVSLP0 */
PAD_CFG_NF(GPP_E5, NONE, RSMRST, NF1), /* SATA_DEVSLP1 */
PAD_CFG_GPO(GPP_E6, 1, PLTRST), /* GPIO */
PAD_NC(GPP_E7, NONE),
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2), /* SATALED# */
PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF1), /* USB_OC0# */
PAD_CFG_NF(GPP_E10, NONE, PLTRST, NF1), /* USB_OC1# */
PAD_CFG_NF(GPP_E11, NONE, PLTRST, NF1), /* USB_OC2# */
PAD_CFG_NF(GPP_E12, NONE, PLTRST, NF1), /* USB_OC3# */
/* ------- GPIO Group GPP_F ------- */
_PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SATAXPCIE3 */
_PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SATAXPCIE4 */
_PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* SATAXPCIE5 */
PAD_CFG_GPO(GPP_F3, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_F4, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_F5, 1, PLTRST), /* GPIO */
PAD_NC(GPP_F6, NONE),
PAD_CFG_GPO(GPP_F7, 1, PLTRST), /* GPIO */
PAD_NC(GPP_F8, NONE),
PAD_CFG_GPO(GPP_F9, 1, PLTRST), /* GPIO */
PAD_NC(GPP_F10, NONE),
PAD_CFG_GPO(GPP_F11, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_F12, 1, DEEP), /* GPIO */
PAD_CFG_GPO(GPP_F13, 1, PLTRST), /* GPIO */
PAD_CFG_NF(GPP_F14, NONE, PLTRST, NF1), /* PS_ON# */
PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), /* GPIO */
PAD_CFG_GPO(GPP_F16, 1, PLTRST), /* GPIO */
PAD_NC(GPP_F17, NONE),
PAD_CFG_GPO(GPP_F18, 1, PLTRST), /* GPIO */
_PAD_CFG_STRUCT(GPP_F19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* eDP_VDDEN */
_PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* eDP_BKLTEN */
_PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* eDP_BKLTCTL */
PAD_NC(GPP_F22, NONE),
PAD_CFG_GPO(GPP_F23, 1, PLTRST), /* GPIO */
/* ------- GPIO Community 4 ------- */
/* ------- GPIO Group GPP_H ------- */
PAD_NC(GPP_H0, NONE),
PAD_NC(GPP_H1, NONE),
PAD_NC(GPP_H2, NONE),
PAD_NC(GPP_H3, NONE),
PAD_NC(GPP_H4, NONE),
PAD_NC(GPP_H5, NONE),
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // SRCCLKREQ12
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // SRCCLKREQ13
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // SRCCLKREQ14
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // SRCCLKREQ15
PAD_CFG_GPO(GPP_H10, 1, PLTRST), // GPIO */
PAD_NC(GPP_H11, NONE),
PAD_CFG_GPO(GPP_H12, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_H13, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_H14, 0, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_H15, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_H16, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_H17, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_H18, 0, PLTRST), /* GPIO */
PAD_NC(GPP_H19, NONE),
PAD_NC(GPP_H20, NONE),
PAD_NC(GPP_H21, NONE),
PAD_NC(GPP_H22, NONE),
PAD_CFG_GPO(GPP_H23, 1, PLTRST), /* GPIO */
/* ------- GPIO Group GPP_J ------- */
PAD_CFG_GPO(GPP_J0, 1, PLTRST), /* GPIO */
_PAD_CFG_STRUCT(GPP_J1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CPU_C10_GATE# */
_PAD_CFG_STRUCT(GPP_J2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CNV_BRI_DT */
_PAD_CFG_STRUCT(GPP_J3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* CNV_BRI_RSP */
_PAD_CFG_STRUCT(GPP_J4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CNV_RGI_DT */
_PAD_CFG_STRUCT(GPP_J5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), /* CNV_RGI_RSP */
PAD_NC(GPP_J6, NONE),
PAD_CFG_GPI_TRIG_OWN(GPP_J7, NONE, RSMRST, OFF, ACPI), /* GPIO */
PAD_CFG_GPO(GPP_J8, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_J9, 1, PLTRST), /* GPIO */
/* ------- GPIO Group GPP_K ------- */
PAD_CFG_GPO(GPP_K0, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_K1, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_K2, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_K3, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_K4, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_K5, 1, PLTRST), /* GPIO */
_PAD_CFG_STRUCT(GPP_K6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDSP_HPDA */
_PAD_CFG_STRUCT(GPP_K7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDSP_HPDB */
_PAD_CFG_STRUCT(GPP_K8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CORE_VID0 */
_PAD_CFG_STRUCT(GPP_K9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* CORE_VID1 */
PAD_CFG_GPO(GPP_K10, 1, PLTRST), /* GPIO */
PAD_NC(GPP_K11, NONE),
/* ------- GPIO Community 5 ------- */
/* ------- GPIO Group GPP_I ------- */
_PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* PMCALERT# */
_PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDSP_HPD1 */
_PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* DDSP_HPD2 */
_PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDSP_HPD3 */
_PAD_CFG_STRUCT(GPP_I4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDSP_HPD4 */
_PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), /* DDPB_CTRLCLK */
_PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), /* DDPB_CTRLDATA */
PAD_NC(GPP_I7, NONE),
PAD_CFG_GPO(GPP_I8, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_I9, 1, PLTRST), /* GPIO */
PAD_CFG_GPO(GPP_I10, 1, PLTRST), /* GPIO */
_PAD_CFG_STRUCT(GPP_I11, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C4_SDA */
_PAD_CFG_STRUCT(GPP_I12, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C4_SCL */
_PAD_CFG_STRUCT(GPP_I13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* USB_OC6# */
_PAD_CFG_STRUCT(GPP_I14, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), /* I2C5_SCL */
};

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src/mainboard/erying/tgl/hda_verb.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* Realtek ALC897 */
0x10ec0897, /* Vendor ID */
0x10ec3000, /* Subsystem ID */
15, /* Number of entries */
AZALIA_SUBVENDOR(0, 0x10ec3000),
AZALIA_PIN_CFG(0, 0x11, 0x40000000),
AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
AZALIA_PIN_CFG(0, 0x14, 0x01014020),
AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
AZALIA_PIN_CFG(0, 0x18, 0x01a19030),
AZALIA_PIN_CFG(0, 0x19, 0x02a1903f),
AZALIA_PIN_CFG(0, 0x1a, 0x01813040),
AZALIA_PIN_CFG(0, 0x1b, 0x02214010),
AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1d, 0x4024c601),
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
#if !CONFIG(SOC_INTEL_DISABLE_IGD)
/* Tigerlake HDMI */
0x80862812, /* Vendor ID */
0x80860101, /* Subsystem ID */
2, /* Number of entries */
AZALIA_SUBVENDOR(2, 0x80860101),
AZALIA_PIN_CFG(2, 0x04, 0x18560010),
#endif
};
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;

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src/mainboard/erying/tgl/ramstage.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include "gpio.h"
static void init_mainboard(void *chip_info)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}
struct chip_operations mainboard_ops = {
.init = init_mainboard,
};
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
// PEG0 - Gen4 NVME
params->CpuPcieRpSlotImplemented[0] = 1;
params->CpuPcieRpPeerToPeerMode[0] = 1;
params->CpuPcieRpAcsEnabled[0] = 1;
// PEG1 - PCI-E x16
params->CpuPcieRpSlotImplemented[1] = 1;
params->CpuPcieRpPeerToPeerMode[1] = 1;
params->CpuPcieRpAcsEnabled[1] = 1;
// PCH RootPorts
params->PcieRpAcsEnabled[4] = 1; // M.2 Gen3
params->PcieRpAcsEnabled[8] = 1; // M.2 NGFF
params->PcieRpAcsEnabled[10] = 1; // RTL8111 NIC
params->PcieRpAcsEnabled[11] = 1; // PCI-E x1 Gen3
// Power management: Force-disable ASPM
params->CpuPciePowerGating = 0;
params->CpuPcieClockGating = 0;
params->PchLegacyIoLowLatency = 1;
params->PchDmiAspmCtrl = 0;
params->CpuPcieRpEnableCpm[0] = 0;
params->CpuPcieRpAspm[0] = 0;
params->CpuPcieRpL1Substates[0] = 0;
params->CpuPcieRpEnableCpm[1] = 0;
params->CpuPcieRpAspm[1] = 0;
params->CpuPcieRpL1Substates[1] = 0;
params->PcieRpEnableCpm[4] = 0;
params->PcieRpAspm[4] = 0;
params->PcieRpL1Substates[4] = 0;
params->PcieRpEnableCpm[8] = 0;
params->PcieRpAspm[8] = 0;
params->PcieRpL1Substates[8] = 0;
params->PcieRpEnableCpm[10] = 0;
params->PcieRpAspm[10] = 0;
params->PcieRpL1Substates[10] = 0;
params->PcieRpEnableCpm[11] = 0;
params->PcieRpAspm[11] = 0;
params->PcieRpL1Substates[11] = 0;
}

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/meminit.h>
#include <soc/romstage.h>
static const struct mb_cfg mem_config = {
.type = MEM_TYPE_DDR4,
.ddr4_config = { .dq_pins_interleaved = true },
};
static const struct mem_spd spd_info = {
.topo = MEM_TOPO_DIMM_MODULE,
.smbus = {
[0] = { .addr_dimm[0] = 0x50, },
[1] = { .addr_dimm[0] = 0x52, },
},
};
const bool half_populated = false;
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
// Performance settings
mupd->FspmConfig.EnableAbove4GBMmio = 1;
// iGPU
mupd->FspmConfig.GttSize = 3; // 8MB
mupd->FspmConfig.ApertureSize = 3; // 512MB
mupd->FspmConfig.GtPsmiSupport = 0;
mupd->FspmConfig.IgdDvmt50PreAlloc = 2; // 64MB
// DMI (SoC - PCH) Link settings
mupd->FspmConfig.DmiMaxLinkSpeed = 3;
mupd->FspmConfig.DmiAspm = 0;
mupd->FspmConfig.DmiAspmCtrl = 0;
// Memory settings/training - based on stock
mupd->FspmConfig.SpdProfileSelected = 0; // Default profile
mupd->FspmConfig.RefClk = 0; // 133MHz
mupd->FspmConfig.VddVoltage = 1350; // 1.35V
mupd->FspmConfig.McPllVoltageOffset = 6; // Bump MC VCC by offset of 6
mupd->FspmConfig.Ratio = 0; // Auto
mupd->FspmConfig.RingDownBin = 1;
mupd->FspmConfig.GearRatio = 1; // Gear 1
mupd->FspmConfig.ECT = 1;
mupd->FspmConfig.LCT = 1;
mupd->FspmConfig.SOT = 1;
mupd->FspmConfig.ERDMPRTC2D = 0;
mupd->FspmConfig.RDMPRT = 1;
mupd->FspmConfig.RCVET = 1;
mupd->FspmConfig.JWRL = 1;
mupd->FspmConfig.EWRTC2D = 1;
mupd->FspmConfig.ERDTC2D = 1;
mupd->FspmConfig.WRTC2D = 1;
mupd->FspmConfig.WRVC1D = 1;
mupd->FspmConfig.DIMMODTT = 1;
mupd->FspmConfig.DIMMRONT = 1;
mupd->FspmConfig.WRDSEQT = 1;
mupd->FspmConfig.WRSRT = 0;
mupd->FspmConfig.RDODTT = 1;
mupd->FspmConfig.RDEQT = 1;
mupd->FspmConfig.RDAPT = 1;
mupd->FspmConfig.RDTC2D = 1;
mupd->FspmConfig.WRVC2D = 1;
mupd->FspmConfig.RDVC2D = 1;
mupd->FspmConfig.CMDVC = 1;
mupd->FspmConfig.MrcSafeConfig = 0;
mupd->FspmConfig.LpDdrDqDqsReTraining = 1;
mupd->FspmConfig.SafeMode = 0;
mupd->FspmConfig.MemTestOnWarmBoot = 1;
mupd->FspmConfig.DdrFreqLimit = 3200; // Maximum tested speed.
memcfg_init(mupd, &mem_config, &spd_info, half_populated);
}