soc/intel/pantherlake: Update PlatformDebugOption to Trace Ready
This enables SOC_INTEL_DEBUG_CONSENT to set PlatformDebugOption to Trace Ready to have the safe configurations for Panther Lake ES SoC. This safe configuration will be removed once the feature is fully verified and safe to be set to the default value. BUG=b:373915085 TEST=Build fatcat and check the platform boots without an issue. Change-Id: I1eaabcb2e2aaff16ee4e64d1c7709b229de18459 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84823 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
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@ -94,6 +94,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
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select SOC_INTEL_CSE_LITE_PSR if MAINBOARD_HAS_CHROMEOS && SOC_INTEL_CSE_LITE_SKU
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select SOC_INTEL_CSE_SEND_EOP_LATE if !MAINBOARD_HAS_CHROMEOS
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select SOC_INTEL_CSE_SET_EOP
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select SOC_INTEL_DEBUG_CONSENT # TODO: Remove the safe setting for ES SoC
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select SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO
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select SOC_INTEL_IOE_DIE_SUPPORT
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select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
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