mb/google/brya: Create telith variant
Create the telith variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0) BUG=372506691 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_TELITH Change-Id: I4971b9691d3dd293ca640795967c36472afef9c9 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84759 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Kun Liu
Martin L Roth
parent
ed73b3f2f7
commit
7d56957395
11 changed files with 814 additions and 0 deletions
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@ -542,6 +542,16 @@ config BOARD_GOOGLE_TELIKS
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select HAVE_WWAN_POWER_SEQUENCE
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select SOC_INTEL_TWINLAKE
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config BOARD_GOOGLE_TELITH
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select BOARD_GOOGLE_BASEBOARD_NISSA
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select BOARD_ROMSIZE_KB_16384
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select CHROMEOS_WIFI_SAR if CHROMEOS
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select DRIVERS_GENERIC_BAYHUB_LV2
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select DRIVERS_GENERIC_GPIO_KEYS
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select DRIVERS_GFX_GENERIC
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select DRIVERS_INTEL_MIPI_CAMERA
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select SOC_INTEL_TWINLAKE
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config BOARD_GOOGLE_TEREID
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select BOARD_GOOGLE_BASEBOARD_NISSA
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select BOARD_ROMSIZE_KB_32768
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@ -734,6 +744,7 @@ config DRIVER_TPM_I2C_BUS
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default 0x0 if BOARD_GOOGLE_YAVIKS
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default 0x0 if BOARD_GOOGLE_YAVILLA
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default 0x1 if BOARD_GOOGLE_ZYDRON
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default 0x0 if BOARD_GOOGLE_TELITH
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config DRIVER_TPM_I2C_ADDR
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hex
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@ -808,6 +819,7 @@ config TPM_TIS_ACPI_INTERRUPT
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default 13 if BOARD_GOOGLE_YAVIKS
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default 13 if BOARD_GOOGLE_YAVILLA
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default 13 if BOARD_GOOGLE_ZYDRON
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default 13 if BOARD_GOOGLE_TELITH
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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@ -889,6 +901,7 @@ config MAINBOARD_PART_NUMBER
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default "Yavista" if BOARD_GOOGLE_YAVISTA
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default "Zydron" if BOARD_GOOGLE_ZYDRON
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default "Pujjoga" if BOARD_GOOGLE_PUJJOGA
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default "Telith" if BOARD_GOOGLE_TELITH
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config VARIANT_DIR
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default "agah" if BOARD_GOOGLE_AGAH
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@ -956,6 +969,7 @@ config VARIANT_DIR
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default "zydron" if BOARD_GOOGLE_ZYDRON
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default "yavista" if BOARD_GOOGLE_YAVISTA
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default "pujjoga" if BOARD_GOOGLE_PUJJOGA
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default "telith" if BOARD_GOOGLE_TELITH
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config VBOOT
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select VBOOT_EARLY_EC_SYNC if !(BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO)
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@ -196,3 +196,6 @@ config BOARD_GOOGLE_PUJJOGA
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config BOARD_GOOGLE_ORISA
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bool "-> Orisa"
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config BOARD_GOOGLE_TELITH
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bool "-> Telith"
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8
src/mainboard/google/brya/variants/telith/Makefile.mk
Normal file
8
src/mainboard/google/brya/variants/telith/Makefile.mk
Normal file
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@ -0,0 +1,8 @@
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# SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += variant.c
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125
src/mainboard/google/brya/variants/telith/gpio.c
Normal file
125
src/mainboard/google/brya/variants/telith/gpio.c
Normal file
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@ -0,0 +1,125 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <soc/gpio.h>
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/* Pad configuration in ramstage */
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static const struct pad_config override_gpio_table[] = {
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/* A11 : GPP_A11 ==> EN_SPK_PA */
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PAD_CFG_GPO(GPP_A11, 0, DEEP),
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/* A18 : NC ==> HDMI_HPD_SRC*/
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PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
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/* A20 : DDSP_HPD2 ==> NC */
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PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG),
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/* A21 : GPP_A21 ==> NC */
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PAD_NC_LOCK(GPP_A21, NONE, LOCK_CONFIG),
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/* A22 : GPP_A22 ==> NC */
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PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG),
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/* B5 : I2C2_SDA ==> MIPI_WCAM_SDA */
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PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG),
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/* B6 : I2C2_SCL ==> MIPI_WCAM_SCL */
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PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG),
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/* B11 : NC ==> EN_PP3300_WLAN_X*/
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PAD_CFG_GPO(GPP_B11, 0, DEEP),
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/* D8 : SRCCLKREQ3# ==> NC */
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PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG),
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/* D13 : NC ==> EN_PP1800_WCAM_X */
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PAD_CFG_GPO_LOCK(GPP_D13, 1, LOCK_CONFIG),
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/* E20 : DDP2_CTRLCLK ==> NC */
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PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG),
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/* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */
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PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG),
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/* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */
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PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
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/* F6 : CNV_PA_BLANKING ==> NC */
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PAD_NC(GPP_F6, NONE),
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/* F15 : GSXSRESET# ==> SOC_PEN_DETECT_ODL */
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PAD_CFG_GPI_SCI_HIGH(GPP_F15, NONE, PLTRST, EDGE_BOTH),
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/* F18 : THC1_SPI2_INT# ==> NC */
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PAD_NC(GPP_F18, NONE),
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/* F23 : V1P05_CTRL ==> NC*/
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PAD_NC_LOCK(GPP_F23, NONE, LOCK_CONFIG),
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/* H8 : CNV_MFUART2_RXD ==> NC */
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PAD_NC(GPP_H8, NONE),
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/* H9 : CNV_MFUART2_TXD ==> NC */
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PAD_NC(GPP_H9, NONE),
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/* H12 : UART0_RTS# ==> NC*/
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PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
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/* H13 : UART0_CTS# ==> NC */
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PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
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/* H15 : DDPB_CTRLCLK ==> HDMI_DDC_SCL */
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PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
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/* H17 : DDPB_CTRLDATA ==> HDMI_DDC_SDA */
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PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
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/* R6 : DMIC_CLK_A_1A ==> NC */
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PAD_NC_LOCK(GPP_R6, NONE, LOCK_CONFIG),
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/* R7 : DMIC_DATA_1A ==> NC */
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PAD_NC_LOCK(GPP_R7, NONE, LOCK_CONFIG),
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/* Configure the virtual CNVi Bluetooth I2S GPIO pads */
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/* BT_I2S_BCLK */
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PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
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/* BT_I2S_SYNC */
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PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
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/* BT_I2S_SDO */
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PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
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/* BT_I2S_SDI */
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PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
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/* SSP2_SCLK */
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PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
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/* SSP2_SFRM */
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PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
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/* SSP_TXD */
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PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
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/* SSP_RXD */
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PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
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};
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* C0 : SMBCLK ==> EN_PP3300_TCHSCR_X */
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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/* C1 : SMBDATA ==> TCHSCR_RST_L */
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PAD_CFG_GPO(GPP_C1, 1, DEEP),
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/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
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PAD_CFG_GPO(GPP_H20, 0, DEEP),
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/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
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/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
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/* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
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PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
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/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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};
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const struct pad_config *variant_gpio_override_table(size_t *num)
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{
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*num = ARRAY_SIZE(override_gpio_table);
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return override_gpio_table;
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}
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __VARIANT_EC_H__
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#define __VARIANT_EC_H__
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#include <baseboard/ec.h>
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#endif
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef VARIANT_GPIO_H
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#define VARIANT_GPIO_H
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#include <baseboard/gpio.h>
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#endif
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12
src/mainboard/google/brya/variants/telith/memory/Makefile.mk
Normal file
12
src/mainboard/google/brya/variants/telith/memory/Makefile.mk
Normal file
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@ -0,0 +1,12 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# This is an auto-generated file. Do not edit!!
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# Generated by:
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# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/teliks/memory src/mainboard/google/brya/variants/teliks/memory/mem_parts_used.txt
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SPD_SOURCES =
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SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
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SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 1(0b0001) Parts = H9JCNNNCP3MLYR-N6E, MT62F1G32D4DR-031 WT:B
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SPD_SOURCES += spd/lp5/set-0/spd-4.hex # ID = 2(0b0010) Parts = H9JCNNNFA5MLYR-N6E, MT62F2G32D8DR-031 WT:B
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SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 3(0b0011) Parts = K3KL6L60GM-MGCT
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SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 4(0b0100) Parts = MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT, H58G56BK7BX068
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SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 5(0b0101) Parts = MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT, H58G66BK7BX067
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@ -0,0 +1,19 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# This is an auto-generated file. Do not edit!!
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# Generated by:
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# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/teliks/memory src/mainboard/google/brya/variants/teliks/memory/mem_parts_used.txt
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DRAM Part Name ID to assign
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MT62F512M32D2DR-031 WT:B 0 (0000)
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H9JCNNNBK3MLYR-N6E 0 (0000)
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H9JCNNNCP3MLYR-N6E 1 (0001)
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MT62F1G32D4DR-031 WT:B 1 (0001)
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H9JCNNNFA5MLYR-N6E 2 (0010)
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MT62F2G32D8DR-031 WT:B 2 (0010)
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K3KL6L60GM-MGCT 3 (0011)
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MT62F1G32D2DS-026 WT:B 4 (0100)
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K3KL8L80CM-MGCT 4 (0100)
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H58G56BK7BX068 4 (0100)
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MT62F2G32D4DS-026 WT:B 5 (0101)
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K3KL9L90CM-MGCT 5 (0101)
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H58G66BK7BX067 5 (0101)
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@ -0,0 +1,24 @@
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# This is a CSV file containing a list of memory parts used by this variant.
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# One part per line with an optional fixed ID in column 2.
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# Only include a fixed ID if it is required for legacy reasons!
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# Generated IDs are dependent on the order of parts in this file,
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# so new parts must always be added at the end of the file!
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#
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# Generate an updated Makefile.mk and dram_id.generated.txt by running the
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# part_id_gen tool from util/spd_tools.
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# See util/spd_tools/README.md for more details and instructions.
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# Part Name
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MT62F512M32D2DR-031 WT:B
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H9JCNNNBK3MLYR-N6E
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H9JCNNNCP3MLYR-N6E
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MT62F1G32D4DR-031 WT:B
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H9JCNNNFA5MLYR-N6E
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MT62F2G32D8DR-031 WT:B
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K3KL6L60GM-MGCT
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MT62F1G32D2DS-026 WT:B
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K3KL8L80CM-MGCT
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H58G56BK7BX068
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MT62F2G32D4DS-026 WT:B
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K3KL9L90CM-MGCT
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H58G66BK7BX067
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537
src/mainboard/google/brya/variants/telith/overridetree.cb
Normal file
537
src/mainboard/google/brya/variants/telith/overridetree.cb
Normal file
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@ -0,0 +1,537 @@
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fw_config
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field WIFI 8 9
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option UNKNOWN 0
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option WIFI_6_7921 1
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option WIFI_6E 2
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option WIFI_6_8852 3
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end
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field CAMERA 10 11
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option UF_720P_WF 0
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option UF_1080P 1
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option UF_720P 2
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option UF_1080P_WF 3
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end
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end
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chip soc/intel/alderlake
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register "sagv" = "SaGv_Enabled"
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# EMMC Tx CMD Delay
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# Refer to EDS-Vol2-42.3.7.
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# [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
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# [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
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register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
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# EMMC TX DATA Delay 1
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# Refer to EDS-Vol2-42.3.8.
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# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
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# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
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register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
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# EMMC TX DATA Delay 2
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# Refer to EDS-Vol2-42.3.9.
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# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
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# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
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# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
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# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
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register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
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# EMMC RX CMD/DATA Delay 1
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# Refer to EDS-Vol2-42.3.10.
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# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
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# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
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# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
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# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
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register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
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# EMMC RX CMD/DATA Delay 2
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# Refer to EDS-Vol2-42.3.12.
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# [17:16] stands for Rx Clock before Output Buffer,
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# 00: Rx clock after output buffer,
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# 01: Rx clock before output buffer,
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# 10: Automatic selection based on working mode.
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# 11: Reserved
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# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
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# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
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register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004C"
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# EMMC Rx Strobe Delay
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# Refer to EDS-Vol2-42.3.11.
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# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
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# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
|
||||
register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
|
||||
|
||||
# SOC Aux orientation override:
|
||||
# This is a bitfield that corresponds to up to 4 TCSS ports.
|
||||
# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
|
||||
# TcssAuxOri = 0100b
|
||||
# Bit0 set to "0" indicates has retimer on USBC Port0, on the DB.
|
||||
# Bit2 set to "1" indicates no retimer on USBC Port1, on the MB.
|
||||
# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
|
||||
# motherboard to USBC connector
|
||||
register "tcss_aux_ori" = "5"
|
||||
|
||||
register "typec_aux_bias_pads[0]" = "{
|
||||
.pad_auxp_dc = GPP_A19,
|
||||
.pad_auxn_dc = GPP_A20
|
||||
}"
|
||||
|
||||
register "typec_aux_bias_pads[1]" = "{
|
||||
.pad_auxp_dc = GPP_E22,
|
||||
.pad_auxn_dc = GPP_E23
|
||||
}"
|
||||
|
||||
# FIVR configurations for teliks are disabled since the board doesn't have V1p05 and Vnn
|
||||
# bypass rails implemented.
|
||||
register "ext_fivr_settings" = "{
|
||||
.configure_ext_fivr = 0,
|
||||
}"
|
||||
|
||||
# Enable the Cnvi BT Audio Offload
|
||||
register "cnvi_bt_audio_offload" = "1"
|
||||
|
||||
# Intel Common SoC Config
|
||||
#+-------------+------------------------------+
|
||||
#| Field | Value |
|
||||
#+-------------+------------------------------+
|
||||
#| I2C0 | TPM. Early init is |
|
||||
#| | required to set up a BAR |
|
||||
#| | for TPM communication |
|
||||
#| I2C1 | Touchscreen |
|
||||
#| I2C2 | Sub-board(PSensor)/WCAM |
|
||||
#| I2C3 | Audio |
|
||||
#| I2C5 | Trackpad |
|
||||
#+-------------+------------------------------+
|
||||
register "common_soc_config" = "{
|
||||
.i2c[0] = {
|
||||
.early_init = 1,
|
||||
.speed = I2C_SPEED_FAST_PLUS,
|
||||
.speed_config[0] = {
|
||||
.speed = I2C_SPEED_FAST_PLUS,
|
||||
.scl_lcnt = 55,
|
||||
.scl_hcnt = 30,
|
||||
.sda_hold = 7,
|
||||
}
|
||||
},
|
||||
.i2c[1] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.speed_config[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.scl_lcnt = 160,
|
||||
.scl_hcnt = 79,
|
||||
.sda_hold = 7,
|
||||
}
|
||||
},
|
||||
.i2c[2] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.speed_config[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.scl_lcnt = 157,
|
||||
.scl_hcnt = 79,
|
||||
.sda_hold = 7,
|
||||
}
|
||||
},
|
||||
.i2c[3] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.speed_config[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.scl_lcnt = 157,
|
||||
.scl_hcnt = 79,
|
||||
.sda_hold = 7,
|
||||
}
|
||||
},
|
||||
.i2c[5] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.speed_config[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.scl_lcnt = 152,
|
||||
.scl_hcnt = 79,
|
||||
.sda_hold = 7,
|
||||
}
|
||||
},
|
||||
}"
|
||||
|
||||
# Power limit config
|
||||
register "power_limits_config[ADL_N_041_6W_CORE]" = "{
|
||||
.tdp_pl1_override = 15,
|
||||
.tdp_pl2_override = 25,
|
||||
.tdp_pl4 = 78,
|
||||
}"
|
||||
|
||||
device domain 0 on
|
||||
device ref dtt on
|
||||
chip drivers/intel/dptf
|
||||
## sensor information
|
||||
register "options.tsr[0].desc" = ""CPU_VR""
|
||||
register "options.tsr[1].desc" = ""CPU""
|
||||
register "options.tsr[2].desc" = ""Ambient""
|
||||
register "options.tsr[3].desc" = ""Charger""
|
||||
|
||||
# TODO: below values are initial reference values only
|
||||
## Passive Policy
|
||||
register "policies.passive" = "{
|
||||
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
|
||||
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
|
||||
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000),
|
||||
[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000),
|
||||
[4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 75, 5000),
|
||||
}"
|
||||
|
||||
## Critical Policy
|
||||
register "policies.critical" = "{
|
||||
[0] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN),
|
||||
[1] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN),
|
||||
}"
|
||||
|
||||
register "controls.power_limits" = "{
|
||||
.pl1 = {
|
||||
.min_power = 6000,
|
||||
.max_power = 15000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 200
|
||||
},
|
||||
.pl2 = {
|
||||
.min_power = 25000,
|
||||
.max_power = 25000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 1000
|
||||
}
|
||||
}"
|
||||
|
||||
## Charger Performance Control (Control, mA)
|
||||
register "controls.charger_perf" = "{
|
||||
[0] = { 255, 3000 },
|
||||
[1] = { 24, 1500 },
|
||||
[2] = { 16, 1000 },
|
||||
[3] = { 8, 500 }
|
||||
}"
|
||||
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref igpu on
|
||||
chip drivers/gfx/generic
|
||||
register "device_count" = "4"
|
||||
# DDIA for eDP
|
||||
register "device[0].name" = ""LCD0""
|
||||
# Internal panel on the first port of the graphics chip
|
||||
register "device[0].type" = "panel"
|
||||
# DDIB for HDMI
|
||||
# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
|
||||
register "device[1].name" = ""DD01""
|
||||
# TCP0 (DP-1) for port C0
|
||||
register "device[2].name" = ""DD02""
|
||||
register "device[2].use_pld" = "true"
|
||||
register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))"
|
||||
# TCP1 (DP-2) for port C1
|
||||
register "device[3].name" = ""DD03""
|
||||
register "device[3].use_pld" = "true"
|
||||
register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref ipu on
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_uid" = "0x50000"
|
||||
register "acpi_name" = ""IPU0""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
|
||||
|
||||
register "cio2_num_ports" = "1"
|
||||
register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used
|
||||
register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0""
|
||||
register "cio2_prt[0]" = "1"
|
||||
device generic 0 on
|
||||
probe CAMERA UF_720P_WF
|
||||
probe CAMERA UF_1080P_WF
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref i2c1 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ILTK0001""
|
||||
register "generic.desc" = ""ILITEK Touchscreen""
|
||||
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
|
||||
register "generic.detect" = "1"
|
||||
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
|
||||
register "generic.reset_delay_ms" = "200"
|
||||
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
|
||||
register "generic.enable_delay_ms" = "12"
|
||||
register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
|
||||
register "generic.stop_off_delay_ms" = "200"
|
||||
register "generic.has_power_resource" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 41 on end
|
||||
end
|
||||
chip drivers/generic/gpio_keys
|
||||
register "name" = ""PENH""
|
||||
register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)"
|
||||
register "key.wake_gpe" = "GPE0_DW2_15"
|
||||
register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
|
||||
register "key.wakeup_event_action" = "EV_ACT_ANY"
|
||||
register "key.dev_name" = ""EJCT""
|
||||
register "key.linux_code" = "SW_PEN_INSERTED"
|
||||
register "key.linux_input_type" = "EV_SW"
|
||||
register "key.label" = ""pen_eject""
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref i2c2 on
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_hid" = ""OVTIDB10""
|
||||
register "acpi_uid" = "0"
|
||||
register "acpi_name" = ""CAM0""
|
||||
register "chip_name" = ""Ov 13b10 Camera""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
|
||||
|
||||
register "ssdb.lanes_used" = "4"
|
||||
register "ssdb.vcm_type" = "0x0C"
|
||||
register "vcm_name" = ""VCM0""
|
||||
register "num_freq_entries" = "1"
|
||||
register "link_freq[0]" = "560 * MHz"
|
||||
register "remote_name" = ""IPU0""
|
||||
|
||||
register "has_power_resource" = "1"
|
||||
#Controls
|
||||
register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
|
||||
register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
|
||||
|
||||
register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X
|
||||
register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1200_WCAM_X
|
||||
register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L
|
||||
|
||||
#_ON
|
||||
register "on_seq.ops_cnt" = "5"
|
||||
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
|
||||
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
|
||||
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
|
||||
register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
|
||||
register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
|
||||
|
||||
#_OFF
|
||||
register "off_seq.ops_cnt" = "4"
|
||||
register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
|
||||
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
|
||||
register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
|
||||
register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
|
||||
|
||||
device i2c 36 on
|
||||
probe CAMERA UF_720P_WF
|
||||
probe CAMERA UF_1080P_WF
|
||||
end
|
||||
end
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_uid" = "2"
|
||||
register "acpi_name" = ""VCM0""
|
||||
register "chip_name" = ""DW9714 VCM ""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_VCM"
|
||||
|
||||
register "vcm_compat" = ""dongwoon,dw9714""
|
||||
|
||||
register "has_power_resource" = "1"
|
||||
#Controls
|
||||
register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_AFVDD
|
||||
|
||||
#_ON
|
||||
register "on_seq.ops_cnt" = "1"
|
||||
register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
|
||||
|
||||
#_OFF
|
||||
register "off_seq.ops_cnt" = "1"
|
||||
register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
|
||||
|
||||
device i2c 0C on
|
||||
probe CAMERA UF_720P_WF
|
||||
probe CAMERA UF_1080P_WF
|
||||
end
|
||||
end
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_uid" = "1"
|
||||
register "acpi_name" = ""NVM0""
|
||||
register "chip_name" = ""GT24P64E""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_NVM"
|
||||
|
||||
register "nvm_size" = "0x2000"
|
||||
register "nvm_pagesize" = "1"
|
||||
register "nvm_readonly" = "1"
|
||||
register "nvm_width" = "0x10"
|
||||
register "nvm_compat" = ""atmel,24c64""
|
||||
|
||||
device i2c 50 on
|
||||
probe CAMERA UF_720P_WF
|
||||
probe CAMERA UF_1080P_WF
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref i2c3 on
|
||||
chip drivers/i2c/rt5645
|
||||
register "hid" = ""10EC5650""
|
||||
register "name" = ""RT58""
|
||||
register "desc" = ""Realtek RT5650""
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
|
||||
register "cbj_sleeve" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
|
||||
register "jd_mode" = "2"
|
||||
device i2c 1a on end
|
||||
end
|
||||
end
|
||||
device ref i2c5 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""PNP0C50""
|
||||
register "generic.desc" = ""PRIMAX Touchpad""
|
||||
register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
|
||||
register "generic.wake" = "GPE0_DW2_14"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 15 on end
|
||||
end
|
||||
end
|
||||
device ref cnvi_wifi on
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
register "enable_cnvi_ddr_rfim" = "true"
|
||||
register "add_acpi_dma_property" = "true"
|
||||
device generic 0 on
|
||||
probe WIFI WIFI_6E
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp4 on
|
||||
# PCIe 4 WLAN
|
||||
register "pch_pcie_rp[PCH_RP(4)]" = "{
|
||||
.clk_src = 2,
|
||||
.clk_req = 2,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_DW1_03"
|
||||
register "add_acpi_dma_property" = "true"
|
||||
device pci 00.0 on
|
||||
probe WIFI WIFI_6_7921
|
||||
probe WIFI WIFI_6_8852
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref pch_espi on
|
||||
chip ec/google/chromeec
|
||||
use conn0 as mux_conn[0]
|
||||
use conn1 as mux_conn[1]
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
end
|
||||
device ref pmc hidden
|
||||
chip drivers/intel/pmc_mux
|
||||
device generic 0 on
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port1 as usb2_port
|
||||
use tcss_usb3_port2 as usb3_port
|
||||
device generic 0 alias conn0 on end
|
||||
end
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port2 as usb2_port
|
||||
use tcss_usb3_port1 as usb3_port
|
||||
device generic 1 alias conn1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref tcss_xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref tcss_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C0 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref tcss_usb3_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C1 (DB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
|
||||
device ref tcss_usb3_port1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref xhci on
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C MB (7.5 inch)
|
||||
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C DB (7.1 inch)
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MB (6.4 inch)
|
||||
register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # UFC (3.7 inch)
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN (2.5 inch)
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A0(MLB))
|
||||
chip drivers/usb/acpi
|
||||
device ref xhci_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C0 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref usb2_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C1 (DB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
|
||||
device ref usb2_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A0 (MLB)""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
|
||||
device ref usb2_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 UFC""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port6 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""PCIe Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
|
||||
device ref usb2_port8 on
|
||||
probe WIFI WIFI_6_7921
|
||||
probe WIFI WIFI_6_8852
|
||||
end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""CNVi Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
|
||||
device ref usb2_port10 on
|
||||
probe WIFI WIFI_6E
|
||||
end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A0 (MLB)""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
|
||||
device ref usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 WLAN""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb3_port4 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp7 off end # SDCard
|
||||
device ref hda on
|
||||
chip drivers/sof
|
||||
register "spkr_tplg" = "rt5650_sp"
|
||||
register "jack_tplg" = "rt5650_hp"
|
||||
register "mic_tplg" = "_2ch_pdm0"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
56
src/mainboard/google/brya/variants/telith/variant.c
Normal file
56
src/mainboard/google/brya/variants/telith/variant.c
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <fw_config.h>
|
||||
#include <sar.h>
|
||||
#include <soc/gpio_soc_defs.h>
|
||||
#include <intelblocks/graphics.h>
|
||||
|
||||
/* Per-pipe DDI Function Control 2 */
|
||||
#define TRANS_DDI_FUNC_CTL2_A 0x60404
|
||||
#define TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS (3 << 6)
|
||||
|
||||
const char *get_wifi_sar_cbfs_filename(void)
|
||||
{
|
||||
return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI));
|
||||
}
|
||||
|
||||
static const struct pad_config wifi_pcie_enable_pad[] = {
|
||||
/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
|
||||
PAD_CFG_GPO(GPP_H20, 1, DEEP),
|
||||
/* B11 : NC ==> EN_PP3300_WLAN_X*/
|
||||
PAD_CFG_GPO(GPP_B11, 1, DEEP),
|
||||
};
|
||||
|
||||
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
|
||||
{
|
||||
if (!fw_config_probe(FW_CONFIG(WIFI, WIFI_6E))) {
|
||||
printk(BIOS_INFO, "CNVi bluetooth disabled by fw_config\n");
|
||||
config->cnvi_bt_core = false;
|
||||
printk(BIOS_INFO, "CNVi bluetooth audio offload disabled by fw_config\n");
|
||||
config->cnvi_bt_audio_offload = false;
|
||||
}
|
||||
}
|
||||
|
||||
void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
|
||||
{
|
||||
if (fw_config_probe(FW_CONFIG(WIFI, WIFI_6_7921))
|
||||
|| fw_config_probe(FW_CONFIG(WIFI, WIFI_6_8852))) {
|
||||
printk(BIOS_INFO, "Enable PCie based Wifi GPIO pins.\n");
|
||||
gpio_padbased_override(padbased_table, wifi_pcie_enable_pad,
|
||||
ARRAY_SIZE(wifi_pcie_enable_pad));
|
||||
}
|
||||
}
|
||||
|
||||
void variant_finalize(void)
|
||||
{
|
||||
/*
|
||||
* Panel CSOT MNB601LS1-3 will flicker once during enter Chrome login screen,
|
||||
* it is because it inserts 12 blank frames if it receives the unmute in VB-ID.
|
||||
*
|
||||
* Always override the mute in VB-ID to avoid Tcon EC detected the
|
||||
* audiomute_flag change.
|
||||
*/
|
||||
graphics_gtt_rmw(TRANS_DDI_FUNC_CTL2_A, ~TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS,
|
||||
TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS);
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue