This patch updates the TCH_PAD_INT_N GPP from A13 to F18
The Touch Pad's interrupt line (TCH_PAD_INT_N) was previously connected
to GPP_A13, This patch moves the interrupt line to GPP_F18, aligning it
with the THC1-i2c interface.
Both LPSS-i2c and THC1-i2c share SCL/SDA signals, with the exception of
the interrupt pin. This change ensures the interrupt pin shared between
both the interface.
The Tier-1 PMC GPE programming specifications limit us to configuring
three GPIO banks. Currently, GPP_A, GPP_D, and GPP_E are utilized, as
demonstrated in
[https://github.com/coreboot/coreboot/blob/main/src/mainboard/google/
fatcat/variants/baseboard/fatcat/devicetree.cb#L3]
We encounter a constraint when attempting to add GPP_F as an additional
Tier-1 GPIO due to the exhaustion of available PMC configuration
registers. However, the THC touchpad requires wake-capable registration,
necessitating a PMC GPE entry.
To resolve this, we have opted to configure GPP_F18 as an IOAPIC
interrupt. This solution provides a dedicated pin, avoiding the
complexities of GPIO shared IRQ masking. Furthermore, GPP_F18 supports
both interrupt (IRQ) and wake functionality, as defined by the ACPI
ACPI_IRQ_WAKE_LEVEL_LOW entry.
Snippet of change in runtime ASL code:
w/o cl:
`Name (_S0W, 0x03) // _S0W: S0 Device Wake State
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x0D,
0x03
})`
w/ cl: no such entry
This patch also removed the GPP_F18 entry from the finger print sensor
config to avoid conflicts.
BUG=b:395160736
TEST=able to build google/fatcat. Verfied touchpad functionality
Change-Id: Ied917427225035a484a5873fa734f4c9f14277c0
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Disable smart card reader power saving as W/A to avoid detect issue
BUG=b:383375529
TEST=Check whether the smart card reader exists without a card inserted
localhost~# lsusb
Bus 004 Device 009: ID 2cb7:0007 Fibocom Wireless Inc. L850-GL
Bus 004 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 003 Device 010: ID 058f:9540 Alcor Micro Corp. AU9540 Smartcard Reader
Bus 003 Device 002: ID 0408:5479 Quanta Computer, Inc. HP 5M Camera
Bus 003 Device 012: ID 0bda:8153 Realtek Semiconductor Corp. USB 10/100/1000 LAN
Bus 003 Device 004: ID 8087:0033 Intel Corp.
Bus 003 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Change-Id: Idfff67b8fadd2ca07572fb3dad8bdffbbf7acad0
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Select FSP_TYPE_IOT, so that Nissa-baseboard boards can be built using
FSP binaries from 3rdparty/fsp.
TEST=build/boot google/craask
Change-Id: I0ba45205e3af9daf7c41d393689d8f14d847a446
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Drop duplicate/unused `mclk` field, which corrects the size of the SSDB
struct to 108 bytes. Size/fields confirmed by comparing to DSDT
dumps of UEFI firmware and SSDB struct in linux MIPI driver (ref:
/include/media/ipu-bridge.h).
Change-Id: Iea5b2138d2396e32bcecb3a48ab2b159a9b33345
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add more platform type values. Values sourced from Slimbootloader and
various DSDT dumps on github.
Change-Id: If7ea46aad76dfedf89f764e60d9bf6061f53cbe1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86794
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Newer recovery images change the manifest format yet again, so increase
the lookhead when parsing the bios_image field to ensure we can find it.
TEST=run `./crosfirmware.sh craaskbowl` without erroring out
Change-Id: Idb1862e38a82f3cec8db55993ccf421cf3572c6f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
These boards use BootGuard, which isn't fully working in coreboot as
it requires the bootblock to be relocatable.
Turn off the PMC to workaround the missing BootGuard requirements, so
that they will turn on when pressing the power button.
Change-Id: Idd03684d9fb4573fc160e17ac2c28c39bc8b2ddd
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Updating from commit id 8ac9378a8487 (2024-11-12):
microcode-20241112 Release
to commit id 8a62de41c011 (2025-02-11):
microcode-20250211 Release
This brings in 1 new commit:
8a62de41c0 microcode-20250211 Release
Change-Id: I3ba126335e4dc3deb93ea8e362ea354f18bbbf38
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
The _STA method of redrix i2c3's power resource currently always returns
true. This causes the device to be powered on by the kernel in a boot
critical path (in acpi_bus_init_power) and blocks it for 300ms due to
the sleep in the _ON method. To prevent this sleep from blocking the
boot, enable use_gpio_for_status so that the implementation of _STA
returns the device's actual power state and the kernel powers on the
device in another place that doesn't block boot.
BUG=b:397355818
TEST=Boot the device, confirm that kernel doesn't sleep for 300ms during
acpi_bus_init_power and the touchscreen works without any problems.
Change-Id: I517a9477f7b59b621337c56eedbfcf17b82dc39b
Signed-off-by: Momoko Hattori <momohatt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86749
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The _STA method of drivers/i2c/generic PowerResource currently always
returns true. To allow generating _STA that returns the device's actual
power state, this CL adds a new boolean option `use_gpio_for_status` to
the `drivers_i2c_generic_config` struct, and propagates the value to
`acpi_power_res_params` to reuse the feature implemented for acpi/device
in [1].
[1] https://review.coreboot.org/c/coreboot/+/55027
BUG=b:397355818
TEST=Dump SSDT on redrix with CB:86749
Change-Id: I5c0a423730788d634a780d1d1d8c87a7007cc150
Signed-off-by: Momoko Hattori <momohatt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sam McNally <sammc@google.com>
This provides entries in the SSDT for all display devices, which
allows the kernel to enumerate them.
Change-Id: I350af852ffed5afda4bbc5a85f5b9db035a99995
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86785
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As the USB-C port on this board is not TBT, change the macro to a
regular port as it is more reliable.
Change-Id: I4dae9ff95d448924f1c2a199053be1ad0ca1cece
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86784
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The entry only provided CNVi configuration, and this board does not
use CNVi, so this entry is not required.
Change-Id: I737bed22f5d1545fe91e37d8e55c7c43d1d841fd
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Commit 3a8835f0e8 ("mb/starlabs/*: Unify tcc_offset settings")
unified the TCC offsets based on:
* 70, 80 and 90 degrees for fanless boards
* 80, 90 and 100 degrees for fanned boards
This board has a fan, so make it follow the above.
Change-Id: Ic40ec1a317c787cf7695b37246b2cb337043af2d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
As the USB-C port on this board is not TBT, change the macro to a
regular port as it is more reliable.
Change-Id: Ibcafae6b9bf495e3d41e3a2c49cda070db1c2e0c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This provides entries in the SSDT for all display devices, which
allows the kernel to enumerate them.
Change-Id: Ie3fe24be948b256b47eb8d48fd8a84d6daa2702f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86742
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPP_F18 is currently shared between the fingerprint sensor GSPI0-CS and
the touchpad THC1-INT.
This commit moves the FPS GSPI0-CS signal to GPP_E17, which is a GSPI-0
CS alternative option and moves the current GSPI0A-CS pin GPP_F18 to
not connected.
Schematic version dated march'25 has the rework details.
BUG=b:395147436
TEST=Build and boot google/fatcat. Able to fetch the FPS version using
`ectool --name=cros_fp version`
Change-Id: I1131962e9b6423bbf68fb92189b8910eab49645e
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86702
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Renames ish_fw.bin to trulo_ish.bin to prevent potential conflicts with
other Nissa projects. This aligns with the naming used in the
chromeos-zephyr-ish package.
BUG=b:397821047
TEST=Flash trulo, disassemble SSDT, search for trulo_ish.bin
BRANCH=none
Change-Id: I855ecc87ddb7b69c2c2c8e4287bd9d6ec2e2e991
Signed-off-by: Yuval Peress <peress@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Deku design has a non-sequential mapping between CPU Type-C ports
and EC Typec-C ports. This patch maps the CPU Type-C port to the
correct EC Type-C port for the Intel re-timer driver.
BUG=b:399032094
TEST=Check the Type-C port and EC port mapping in coreboot log
deku-rev1 ~ # cbmem -c |grep "USB Type-C"
[INFO ] USB Type-C 0 mapped to EC port 0
[INFO ] USB Type-C 1 mapped to EC port 2
[INFO ] USB Type-C 2 mapped to EC port 1
[INFO ] USB Type-C 3 mapped to EC port 3
Change-Id: I80fa45a5f40d15c86087dca98bd0fb80a9121e50
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86705
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch moves the debug print which prints the mapping between CPU
Type-C port and EC Type-C port from SoC code to generic driver code.
BUG=b:399032094
TEST=Check the Type-C port and EC port mapping in coreboot log
Change-Id: Iaef5813cc825569a53feba975258f7d5fadecfab
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86704
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch adds the parameter which allows for custom port mapping
between CPU Type-C port and EC Type-C port to accommodate the
non-sequential mapping. Mainboard code must configure this parameter
if the CPU Type-C port to EC Type-C port mapping is not sequential.
BUG=b:399032094
TEST=build and verify TCSS port and EC port mapping
Change-Id: Id92f942e5c6b27342777b3e6fd12aff264ccec1b
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Now that pch_hda_audio_link_hda_enable is hooked up in soc code, enable
it in devicetree to enable the HDA audio link.
Change-Id: I3f902d9b994cb0aac75cda69476500ec7c47b763
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86696
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In CB:86109 it was reported that some options incorrectly don't depend
on EC_DASHARO_EC. Remove `depends on` from all options and instead put
everything behind an `if EC_DASHARO_EC` to ensure options don't cause
issues with boards not using Dasharo EC.
Change-Id: If6303bf7f155749bfcf9145fb93b018247350009
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86698
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It was disabled while debugging S0ix issues during development.
Re-enable it now that S0ix is functional.
Change-Id: Ieab5229474ef93e96908b70e5986949b406fc0fa
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86693
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
libpayload stdint.h only supports typedefs for datatypes of exact
bits. This makes libpayload less flexible to support libraries
that reference different data types.
Add fast data types in types.h.
BUG=b:386913035
Change-Id: Ie9197866ae9b6c27d3f26c11d8409ecb90321c74
Signed-off-by: Masa Nakura <nakura@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86632
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Don't map more than 16MiB in ROM2 decode window when the SPI ROM
size is bigger than 16MiB.
TEST: amd/birman+ still boots with bigger SPI flash sizes.
Change-Id: Ie811f6a38363f2e900611b3f3f407a94d8137c89
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86582
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit binds the cep_enable, enable_fast_vmode and
fast_vmode_i_trip voltage regulator SoC settings to the CepEnable,
EnableFastVmode and IccLimit UPDs respectively.
BUG=b:357011633
TEST=CepEnable, EnableFastVmode and IccLimit are set accordingly
Change-Id: Ie72e4725cb97b4af7843a43eeaedd687d28b6752
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85131
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Intel TXT requires the debug interface to be disabled. There is no
way to program the MSR_IA32_DEBUG_INTERFACE using FSP as needed, so
let coreboot handle it.
TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled
Change-Id: I7ed4382bbe68f03e8eca151245c13928609f434f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Generate SPD id for Nanya memory NT6AP512T32BL-J1
BUG=b:401424949
TEST=run part_id_gen to generate SPD id
Change-Id: I4b207076b73a03059262e0244f5dd0ea24625ff0
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86763
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Generate SPD id for Nanya memory NT6AP512T32BL-J1
BUG=b:401659784
TEST=run part_id_gen to generate SPD id
Change-Id: I655590e43fcd9c3eb704d09edd6dcee51b635256
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add Shuo to x86 maintainer to focus on x86 arch changes impacting
Xeon-SP.
Change-Id: Ia273f3d6fc1e4b13bd1f695976209a95adc03f60
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
It was accidentally deleted in a recent commit, but missed in review
since it is in a comment and not the actual acpigen code.
Change-Id: I0d28c2a67579a135e9002eaab9450353e8eec2d5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Move PCI Option ROM handling code into device/pci_rom.c as it's
already using a majority of functions within this file.
Change-Id: I50fc3bf45a1ab6572ab031b9e24ca2f882a13aad
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Recent AMD iGPUs are not VGA compatible anymore, thus they don't
identify themself as "VGA compatible" anymore by the PCI class code.
Since the PCI VGA Option ROM code assumes it only runs on VGA
compatible devices, relax the ACPI code part to handle display devices
as well. In order to run a VBIOS in coreboot it still must be VGA
compatible, but for ACPI table generation, where no code is run, it's
not necessary any more.
The new code allows to use Linux's amdgpu driver on AMD/glinda.
TEST: On amd/birman+ the amdgpu kernel drivers starts and dmesg shows:
[ 3.010224] [drm] amdgpu kernel modesetting enabled.
The coreboot log shows:
[INFO ] CBFS: Found 'pci1002,150e.rom' @0x10a40 size 0x4400 in mcache @0x1b7dd184
[DEBUG] In CBFS, ROM address for PCI: 00:02:00.0 = 0xff012a6c
[DEBUG] Class Code mismatch ROM 00030000, dev 00038000
[DEBUG] Copying non-VGA ROM image from 0xff012a6c to 0x000d0000, 0x4400 bytes
[...]
Copying initialized VBIOS image from 0x000d0000
[DEBUG] ACPI: * VFCT at 1b5cb960
Change-Id: I623cd80b45b148b91f2796b22a589bbede0feeeb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86386
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Currently the VBIOS is placed somewhere in DRAM when necessary.
While generating ACPI tables the code attempts to find the VBIOS
by looking at "known" places.
Simplify the code and keep track of the VBIOS using a pointer in
struct device by filling it in pci_rom_load().
The following patches will reuse this pointer to generalize the
code even more.
Change-Id: Ib27d30e3b07740d6098d4f7a5c4f5d8bce976f00
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86385
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Do not assume that a VBIOS has been run when loaded below 1MiB.
On recent AMD platforms the VBIOS is loaded into the C/D-segment,
but it's not run as CONFIG_VGA_ROM_RUN is not set.
Since commit 5f5aa79 "device/pci_rom: Move VBIOS checksum fix" the
VBIOS has a valid checksum in ati_rom_acpi_fill_vfct(), thus it's
not possible to tell if it has been run or ATOMBIOS tables have
been modified.
Update the debug message to avoid confusion.
Change-Id: I63289ecf2c212f3d95e022e8c47dcd0ac610d970
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86732
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Correct the comments, and use the definations where available
for the sleep assertion values
Change-Id: Idfd382a166c8101b5d9a79bd18c40d6763c05e7b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/ is still needed due to
Intel FSP repo does not ship all header files.
TEST=Build and boot on intel/archercity CRB
Change-Id: I778d3535c273dff653330518653bdefcb45e66f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80360
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The EC code will monitor Body to choose corresponding DPTF oem variable
table. When it changes, this event will send to the ACPI FW through host
event and then pass onto the DPTF kernel driver.
BUG=b:394177292
BRANCH=firmware-trulo-15217.771.B
TEST=emerge-nissa coreboot
Change-Id: I7ed72157d3480fca5fd1a58b5d9bc3e321f4a628
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Use DPTF_FEATURE_DYNAMIC_THERMAL_TABLE_SWITCH to support
body detection to DPTF on the Uldrenite.
BUG=b:394177292
BRANCH=firmware-trulo-15217.771.B
TEST=emerge-nissa coreboot
Change-Id: I6e98b9c3fd1b38d10a1aa7c30d5d92e1638449f2
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86494
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Adjust I2C/data fall Time to 13.5 ns and I2C data hold time to 353 ns
BUG=b:397150937
BRANCH=firmware-trulo-15217.771.B
TEST=Confirm the measured waveform of the Touchpad .
Change-Id: I16a9967f7e99892f2aa337ad9290252ab63a5b97
Signed-off-by: jamie_chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86743
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch changes child record count to 1 (i.e., compute die). The
number of crashlog agent/SRAM storage count is reduced in Crashlog
Discovery table (CRASHLOG_HEADER) for Panther Lake to 1 aka compute
die compared to MTL where crashlog units were compute die and GT die
source= 733648-LNLFAS-15.3.4,812562 PTL FAS 16.5.2 PTL
Dis-Aggreagation CrashLog
BUG=None
TEST=Build fatcat and verify the child record count
Change-Id: I209366d324c95b7a32afdcfb792c34d927a0508e
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
