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mb/starlabs/*: Correct comments/use defs for sleep assertion

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Correct the comments, and use the definations where available
for the sleep assertion values

Change-Id: Idfd382a166c8101b5d9a79bd18c40d6763c05e7b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Sean Rhodes 2025-03-06 13:48:52 +00:00
commit 89c7a5b766
9 changed files with 36 additions and 36 deletions
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8
src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
View file

@ -11,10 +11,10 @@ chip soc/intel/alderlake
}"
# Power
register "pch_slp_s3_min_assertion_width" = "2" # 50ms
register "pch_slp_s4_min_assertion_width" = "3" # 1s
register "pch_slp_sus_min_assertion_width" = "3" # 500ms
register "pch_slp_a_min_assertion_width" = "3" # 2s
register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_1_MS"
register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_3S"
register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S"
register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS"
device domain 0 on
device ref igpu on

8
src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
View file

@ -20,10 +20,10 @@ chip soc/intel/alderlake
}"
# Power
register "pch_slp_s3_min_assertion_width" = "2" # 50ms
register "pch_slp_s4_min_assertion_width" = "3" # 1s
register "pch_slp_sus_min_assertion_width" = "3" # 500ms
register "pch_slp_a_min_assertion_width" = "3" # 2s
register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_1_MS"
register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_3S"
register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S"
register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS"
# Device Tree
device domain 0 on

8
src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb
View file

@ -21,10 +21,10 @@ chip soc/intel/alderlake
}"
# Power
register "pch_slp_s3_min_assertion_width" = "2" # 50ms
register "pch_slp_s4_min_assertion_width" = "3" # 1s
register "pch_slp_sus_min_assertion_width" = "3" # 500ms
register "pch_slp_a_min_assertion_width" = "3" # 2s
register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_1_MS"
register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_3S"
register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S"
register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS"
# Device Tree
device domain 0 on

8
src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
View file

@ -29,10 +29,10 @@ chip soc/intel/cannonlake
}"
# Power
register "PchPmSlpS3MinAssert" = "2" # 50ms
register "PchPmSlpS4MinAssert" = "3" # 1s
register "PchPmSlpSusMinAssert" = "3" # 500ms
register "PchPmSlpAMinAssert" = "3" # 2s
register "PchPmSlpS3MinAssert" = "2" # 1ms
register "PchPmSlpS4MinAssert" = "3" # 3s
register "PchPmSlpSusMinAssert" = "3" # 1s
register "PchPmSlpAMinAssert" = "3" # 98ms
# PCIe Clock
register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"

8
src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
View file

@ -27,10 +27,10 @@ chip soc/intel/skylake
}"
# Power
register "PmConfigSlpS3MinAssert" = "2" # 50ms
register "PmConfigSlpS4MinAssert" = "3" # 1s
register "PmConfigSlpSusMinAssert" = "3" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmConfigSlpS3MinAssert" = "2" # 1ms
register "PmConfigSlpS4MinAssert" = "3" # 3s
register "PmConfigSlpSusMinAssert" = "3" # 1s
register "PmConfigSlpAMinAssert" = "3" # 98ms
# Enable the correct decode ranges on the LPC bus.
register "lpc_ioe" = "LPC_IOE_EC_4E_4F |

8
src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
View file

@ -22,10 +22,10 @@ chip soc/intel/alderlake
}"
# Power
register "pch_slp_s3_min_assertion_width" = "2" # 50ms
register "pch_slp_s4_min_assertion_width" = "3" # 1s
register "pch_slp_sus_min_assertion_width" = "3" # 500ms
register "pch_slp_a_min_assertion_width" = "3" # 2s
register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_1_MS"
register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_3S"
register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S"
register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS"
# Device Tree
device domain 0 on

8
src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
View file

@ -34,10 +34,10 @@ chip soc/intel/tigerlake
}"
# Power
register "PchPmSlpS3MinAssert" = "2" # 50ms
register "PchPmSlpS4MinAssert" = "3" # 1s
register "PchPmSlpSusMinAssert" = "3" # 500ms
register "PchPmSlpAMinAssert" = "3" # 2s
register "PchPmSlpS3MinAssert" = "2" # 1ms
register "PchPmSlpS4MinAssert" = "3" # 3s
register "PchPmSlpSusMinAssert" = "3" # 1s
register "PchPmSlpAMinAssert" = "3" # 98ms
# Enable the correct decode ranges on the LPC bus.
register "lpc_ioe" = "LPC_IOE_EC_4E_4F |

8
src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb
View file

@ -22,10 +22,10 @@ chip soc/intel/alderlake
}"
# Power
register "pch_slp_s3_min_assertion_width" = "2" # 50ms
register "pch_slp_s4_min_assertion_width" = "3" # 1s
register "pch_slp_sus_min_assertion_width" = "3" # 500ms
register "pch_slp_a_min_assertion_width" = "3" # 2s
register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_1_MS"
register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_3S"
register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S"
register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS"
device domain 0 on
device ref igpu on

8
src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb
View file

@ -25,10 +25,10 @@ chip soc/intel/alderlake
}"
# Power
register "pch_slp_s3_min_assertion_width" = "2" # 50ms
register "pch_slp_s4_min_assertion_width" = "3" # 1s
register "pch_slp_sus_min_assertion_width" = "3" # 500ms
register "pch_slp_a_min_assertion_width" = "3" # 2s
register "pch_slp_s3_min_assertion_width" = "SLP_S3_ASSERTION_1_MS"
register "pch_slp_s4_min_assertion_width" = "SLP_S4_ASSERTION_3S"
register "pch_slp_sus_min_assertion_width" = "SLP_SUS_ASSERTION_1_S"
register "pch_slp_a_min_assertion_width" = "SLP_A_ASSERTION_98_MS"
# PM Util
register "pmc_gpe0_dw0" = "PMC_GPP_F"