Each error source descriptor basically has these values at the
beginning. The error source descriptors are added in the follow up
patches.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic6873cb8cf7373435be3ce26382aa8ae37cd5938
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add validation checks in camera_enable() for required parameters:
- ssdb.lanes_used
- ssdb.platform
- rom_address (when rom_type is set)
- vcm_address (when vcm_type is set)
Remove default values for ssdb.platform and ssdb.lanes_used from
camera_fill_ssdb_defaults() since these parameters are now required
and validated. All boards in the tree explicitly set these values
in their devicetree configurations, so the defaults were never used.
Also remove the unused cio2 and cio2_config variables that were only
used for the lanes_used default logic.
Change-Id: Idcb84c25b94ed9259698aafba201cc4f4e0f1af7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90517
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add support for non-VGA devices (e.g., Intel IPU) in the generic
graphics driver by:
- Adding DOD_NONVGA bit definition per ACPI spec 6.5 table B-2
- Adding non_vga_device boolean field to device config structure
- Increasing device array size from 6 to 7 to accommodate IPU
- Updating ACPI _DOD generation to use DOD_NONVGA flag for non-VGA
devices instead of DOD_FW_DETECT
This allows proper ACPI enumeration of non-VGA devices whose power
is related to the VGA device, such as Intel Image Processing Units.
TEST=tested with rest of patch train on screebo, redrix, and others.
Change-Id: I60472e1232959fe407f63b4b8e6bffba995e7f79
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90516
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Refactor the MIPI camera driver to support two ACPI device generation
modes via a Kconfig choice:
1. Windows/Linux mode (MIPI_ACPI_TYPE_WINDOWS_LINUX): Generates a
single ACPI device for the camera sensor and any associated VCM or
NVM devices on the same I2C bus. The IPU ACPI device is attached to
the iGPU, not standalone. This is the preferred method for Windows
and mainline Linux.
2. ChromeOS mode (MIPI_ACPI_TYPE_CHROMEOS): Generates separate ACPI
devices for each camera component (sensor, CIO2, VCM, NVM). The IPU
ACPI device is generated separately from the iGPU. This maintains
compatibility with the existing ChromeOS-style setup.
The implementation uses runtime conditionals to select between the two
modes. Common helper functions are shared between modes, while device-
specific logic is conditional based on the selected ACPI type.
The default selection is MIPI_ACPI_TYPE_CHROMEOS for ChromeOS builds and
MIPI_ACPI_TYPE_WINDOWS_LINUX otherwise.
Change-Id: I0bc4894aff04d6b296011e85d790d624890da055
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90522
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add support for Computer Vision Framework Support DSM UUID with ACPI-
compliant query handling and ASL documentation. Currently we are
always returning Zero (unsupported/disabled), but support will be
added in future patches.
This UUID is utilized by the standard Intel drivers under both Windows
and mainline Linux.
TEST=tested with rest of patch train on screebo, redrix, and others.
Change-Id: I6db88285d757826fa0f3eb5aa4bb1cc4176b95b3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90490
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add camera_generate_dsm_i2c_v2() to support the I2C V2 DSM UUID
(5815c5c8-c47d-477b-9a8d-76173176414b) which returns I2C device
addresses in a buffer format, rather than individually. Includes
ACPI-compliant function query handling (Arg2==0) and ASL code
documentation.
This UUID is utilized by the standard Intel drivers under both Windows
and mainline Linux.
TEST=tested with rest of patch train on screebo, redrix, and others.
Change-Id: Ifd35b53b21d0d1be9e9802059c724bf544ca1a1a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90489
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename UUID macros to match external conventions used in Linux kernel
and Windows Camera DDK:
- SENSOR_NAME_UUID -> UUID_DSM_SENSOR
- SENSOR_TYPE_UUID -> UUID_DSM_I2C
Rename functions for clarity:
- camera_generate_dsm_sensor_name -> camera_generate_dsm_sensor
- camera_generate_dsm_sensor_type -> camera_generate_dsm_i2c
Add ACPI-compliant function query support (Arg2==0) to sensor DSM,
returning bitmask of supported functions as required by ACPI spec.
Add ASL documentation comment blocks above each DSM generator function
showing the generated ACPI code structure.
Improve variable naming (i2c_dev_count, i2c_dev_idx) for readability.
TEST=tested with rest of patch train on screebo, redrix, and others.
Change-Id: I38facaf85ea59aa82621d82555858c0d72b1ee30
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Refactor camera_generate_dsm() to call separate functions for each
DSM UUID type, improving code organization and maintainability, in
preparation for adding the generation of additional DSM UUIDs in
subsequent patches.
This is a non-functional change.
TEST=tested with rest of patch train on screebo, redrix, and others.
Change-Id: I8b3fb6e3004ea30aa7c11217c9971bddb977ded5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90487
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add ssdb.rom_type and rom_address registers to board variants for MIPI
camera sensor SSDB settings, which are necessary for the Intel driver
stack under Windows and mainline Linux. A handful of boards, mostly not
released to the public, include a commented-out placeholder as ROM type
24C1024 is currently unsupported.
TEST=tested with rest of patch train on screebo, redrix, and others.
Change-Id: I16b44609c1b07ac686d67cc59b4b5311495117ae
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90486
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Apply the change of commit a97fb7f960
("mb/google/volteer/variants: Update Power Limit2 minimum value")
to drobit since it looks like it has been forgotten. It is the
last variant where pl2 min != max.
TEST=Build and boot google/drobit and verify sane clock speeds and
tempoeratures under full CPU load.
Change-Id: I7b09825ebd95fd2795408cdaa0396bbf19baded9
Signed-off-by: Ingo Reitz <9l@9lo.re>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90501
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add CFR option "touchpad_wake" (default: false) to allow users to
enable touchpad wake from sleep. Wake is disabled by default to
prevent random wakeups when systems are moved while sleeping.
Implementation:
- Add touchpad_wake CFR option to System form
- Add device alias "touchpad" to variant devicetree files
(add touchpad2 where a 2nd touchpad option is present)
- Update variant GPIO configs to support wake capability
(this was set inconsistently)
- Conditionally disable wake in ramstage based on CFR option
When the option is disabled (default), config->wake and
config->irq.wake are set to 0, preventing the touchpad ACPI device
from defining wake methods and capability.
TEST_1: Build for ELDRID, boot system into mainlinue Linux (Fedora).
Close the lid to suspend the system, firmly grab it with both hands and
jump 10 times. Make sure that system doesn't wake up from sleep state.
TEST_2: Build for DROBIT, boot system into mainline Linux (NixOS).
Close the lid to suspend the system, firmly grab it with both hands and
jump few times. Make sure that system doesn't wake up from sleep state.
Tested-by: Ingo Reitz <9l@9lo.re>
Change-Id: Ie3b5013bcf2d5ea45388bcdce987dd9ae5870597
Co-authored-by: Alicja Michalska <alicja.michalska@9elements.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add CFR option "touchpad_wake" (default: false) to allow users to
enable touchpad wake from sleep. Wake is disabled by default to
prevent random wakeups when systems are moved while sleeping.
Implementation:
- Add touchpad_wake CFR option to System form
- Add device alias "touchpad" to variant devicetree files
- Conditionally disable wake in ramstage based on CFR option
When the option is disabled (default), config->wake and
config->irq.wake are set to 0, preventing the touchpad ACPI device
from defining wake methods and capability.
TEST=Build for KOHAKU, boot into mainline Linux (Fedora 43, kernel
6.18). Suspend the machine, close the lid, apply pressure to trackpad
area. Ensure that system doesn't wake up.
Change-Id: I620d7c0f0ebec8ca72ec018c93747f58735fd3e5
Co-authored-by: Alicja Michalska <alicja.michalska@9elements.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90491
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The STATESTS register is a very simple read/write-1-clear status
register. OS drivers have to read and clear it all the time with-
out any quirk handling. So it seems unlikely that this sequence
was ever necessary for any coreboot-supported chip.
More likely, that sequence was copied from the dance around the
reset bit when Poulsbo support was added in commit be61a17351
("Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board
which uses it.").
TEST= Verbs were loaded correctly on off-tree HP ProBook 450 G3.
Change-Id: I1fbea8ffb71a2fcb4ce5f42b3cb8f816ec336c5b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89653
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The azalia_set_bits() function does some sequencing specific to the
CRST# bit. Name it accordingly and adapt its signature.
The while loop was also changed to match the other functions (e.g.
wait_for_ready()).
TEST= Verbs were loaded correctly on off-tree HP ProBook 450 G3.
Change-Id: I5ac766f2ddf8b48b436a54469815bf799ae31d52
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89652
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The spec[1] says a codec is allowed to take up to 521us before sig-
naling an initialization request. Our original SB600 implementation
had a 1ms delay here since commit 4505948fae ("Use the correct device
for switching on HDA.")
Most codecs are a lot faster, which is probably why nobody noticed
the missing delay. For instance, the Realtek ALC272 datasheet spe-
cifies a 1 frame (1/48kHz) maximum[2]. It doesn't hurt, though, to
be correct here. We have a lot longer delays around.
[1] High Definition Audio Specification 1.0a: "4.3 Codec Discovery"
[2] ALC272 datasheet: "9.2.1. Link Reset and Initialization Timing"
TEST= Verbs were loaded correctly on off-tree HP ProBook 450 G3.
Change-Id: Ifd3357758fb3678e60b4c6edcfbdb60b3bda9746
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This adds the release notes template for the upcoming March 2026
release of coreboot.
Change-Id: I7702ee6b5dffce067503ff6e4ccb6508d30bf48f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
These are the preliminary release notes. They'll need to be updated
with any changes done this week. We'll need another patch after the tag
to capture the final statistics. The notes will be changed from
"Upcoming release" after the tag is done.
Change-Id: Ic8c5a4f374adc6560eff8383d45d05d16ba84759
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90497
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
non-cacheable
Add support to split the dram_aop memory region into three in order to
map dram_aop_cmd_db as non-cacheable. The purpose of dram_aop_config
is memory region where the aop_devcfg.mbn image is loaded.
Test=1. Build and boot on X1P42100.
2. Dump the MMU table in coreboot ramstage and verify whether the region
is mapped as non-cacheable.
Change-Id: Id73d878b7d343f248a845bd5727c43e22c4c348a
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90521
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support to map AOP CMD-DB region as uncached region in MMU. The
reason for this change is that the CMD-DB region is configured as
read-only region and any write to this region will be treated as
fatal. Mapping it as cacheable can lead to cache-line writebacks,
causing invalid accesses and device crashes.
Test=1. Create an image.serial.bin and ensure it boots on X1P42100.
MMU Table dump from Trace32:
'M:0000000081C60000--0000000081C7FFFF| AM:0000000081C60000--0000000081C7FFFF| s | | 00001000| read/write access exec | yes| inn| non-cacheable | 1| no | \\ramstage\Global\_dram_aop_cmd_db'
Change-Id: I296b505f670f3be28eb998fdac8164a85bf757b0
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90464
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On WCL RVP, ISH (Intel Sensor Hub) shares UART with FPS (Finger Print
Sensor), we can enable either ISH UART or FPS UART, or disable both
UART by changing the DIP switch settings. When DIP switch is not set
for ISH, ISH RX signal is disconnected, causing ISH low power mode
failure. Therefore, NC ISH RX pin mux to minimize the impact on ISH PM.
As a result, ISH console won't accept input since this pin is not
connected.
BUG=b:428084925
TEST=DIP SW1317 3-6, 4-5 on WCL RVP DT card ON to enable FPS UART,
ISH main firmware boots up and runs successfully.
SW1317 all switches OFF to disable both FPS and ISH UART, ISH main
firmware boots up and runs successfully.
Put system into suspend state and resume back. System enters into
low power mode as substate_residencies are updated. Verified using
console command "cat /sys/kernel/debug/pmc_core/substate_residencies".
Change-Id: I1165e0151c0a6d0e82038215703626e863739b39
Signed-off-by: Megha Verma <megha.verma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bhat D, Krishna P <krishna.p.bhat.d@intel.com>
Reviewed-by: P, Usha <usha.p@intel.com>
The mipi_cmd_func_t callback for mipi_panel_parse_init_commands()
currently doesn't support passing additional data for storing context.
Therefore user code would need to store any extra data in global
variables. For example, in the upcoming DSI dual channel support for
MediaTek platforms, the callback needs to know whether the MIPI panel
supports dual channel or not. To support that use case, pass an extra
`user_data` argument to mipi_cmd_func_t.
BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a
BRANCH=none
Change-Id: Id5d7b168cdcadfe8d8435c29d7e855a535815057
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Update off-mode detection logic to use ChromeEC host events. If
the system is powered on by AC insertion (without power button
or lid open events), identify the boot as off-mode charging.
BUG=b:457566143
TEST=Verify off-mode battery charging on Google/Quenbi.
Change-Id: Ibfbbf9cbeabd229595f625104f94eb814012e2f8
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90511
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
pcie_rp5 and pcie_rp6 belong to the same PCIe controller group
(Port C1–C2). Within this controller, pcie_rp5 represents function 0
and pcie_rp6 represents function 1. For multi-function PCIe root
ports, function 0 must be enabled for the controller to initialize
fully.
If only pcie_rp6 (function 1) is enabled, the controller does not
complete initialization and the downstream LAN device fails to
enumerate. Enabling pcie_rp5 ensures the PCIe controller group is
brought up correctly and allows the RTL8111H LAN device behind
pcie_rp6 to enumerate as expected.
BUG=b:466908212
TEST=Build and boot to OS in kodkod.
kodkod:/ # pclspci -v
01:00.0 Class 0200: Device 10ec:8168 (rev 15)
DeviceName: Ethernet controller
Kernel driver in use: r8169
Change-Id: I4332f3d612f1f66cd30dda7da723c47bcfce35a3
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Define the QCLIB_GA_ENABLE_PD_NEGOTIATION bit in the QcLib global
attributes. This flag signals to QcLib that Power Delivery
negotiation should be performed.
BUG=b:457566143
TEST=Verify different boot modes on Google/Quenbi.
TEST=Verify that PD negotiation is skipped in normal mode.
Change-Id: Ia046f68ebeacaa1c1d9a73c4b957315c9f7b68b6
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90512
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the section guid is CPER_SEC_PROC_IA32X64_GUID we want the x86
processor specific section instead of the generic one.
This was probably some kind copy error from the line above.
Change-Id: I6a6a885bf8ab97cb5d256513cf8134078b707d3c
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90476
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Introduce a weak function qclib_mainboard_override to allow
mainboards to customize QcLib policies or global attributes.
This hook is called from the SoC-specific QcLib initialization
path.
BUG=b:457566143
TEST=Configure QcLib policy for Google/Quenbi.
Change-Id: I0397b7138db260973ea86852cfa9f408e14d195d
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Ensure that existing flags in global_attributes are not overwritten
when enabling UART logging. Using a bitwise OR preserves any
previously set attributes.
BUG=b:457566143
TEST=Verify the QcLib global attributes.
With this CL -
```
[DEBUG] Global Attributes[0x3]..Table Entries Count[8]
```
Change-Id: Iffceb06cb800ba4c9e5c07381745cbed1fb7d550
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90509
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the SSRAM memory layout in memlayout.ld to reserve
space for several new regions.
The following regions are added to the SSRAM section:
- qsee: 100K at 0x14680000
- qdss_usb_trace: 8K at 0x146A6000
- aop_imem: 8K at 0x146A8000
The memory map diagram in the comments is also updated to reflect the
reservation of aop_imem and qdss_usb_trace.
BUG=b:456953373
TEST=Able to build and boot google/quenbih.
Change-Id: I17c2a97d31cdcb81ffdd0c83d8c6d19b9a03a91b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90443
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Relocate the PRERAM_STACK region to a new address to resolve a memory
conflict with the QSEE Trust Zone environment.
Details:
- The previous location of the PRERAM_STACK starting at 0x14680000 in
SSRAM is now reserved for QC QSEE.
- This change moves the 16KB PRERAM_STACK from 0x14680000 (SSRAM) to
the available memory region starting at 0x14850000 in the BSRAM.
BUG=b:456953373
BRANCH=None
TEST=Able to build google/bluey.
Change-Id: Ifa9bc457e28b9ec21aa59c6ab9114993f23b2bc8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Implement the newly introduced PRERAM_STACK and POSTRAM_STACK macros in
the x1p42100 memory layout, addressing the memory constraints on this
SoC.
Changes
- Pre-RAM Stack: The temporary stack used before DRAM is ready is
defined using PRERAM_STACK(0x14680000, 16K) in the SSRAM region,
replacing the old generic STACK definition.
- Post-RAM Stack: The final stack is defined using
POSTRAM_STACK(0x80000000, 16K) at the start of DRAM.
- The POSTRAM_DMA_COHERENT region is shifted up to 0x80004000 to
accommodate the new 16KB post-RAM stack, avoiding memory overlap.
This guarantees a distinct and properly sized stack region for each
stage of the boot process, resolving conflicts with Trust Zone and
ensuring a clean stack transition during the RAM stage.
BUG=b:456953373
BRANCH=None
TEST=Able to build google/bluey.
w/o this patch
```
[SPEW ] stack: top_of_stack address is 0x14684000
```
w/ this patch
```
[SPEW ] stack: top_of_stack address is 0x80004000
```
Change-Id: Iccf3f99aff31a8e44386ea52b2196b49797caa79
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90405
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change prepares an alternative entry point for the ARM64
ramstage. It is written in assembly language, avoids the usage of the
stack, and overrides the program stack pointer (SP register) if the
`preram_stack` and `postram_stack` point to different addresses.
Previous Boot Flow:
- header.ld -> jump into `stage_entry` C code for ROMSTAGE onwards ->
`stage_entry` being called and followed by `main` function
Updated Boot Flow:
- header.ld -> jump into `_start` (assembly entry point) for
ramstage specifically -> Update the existing SP (stack pointer)
register if the `preram_` or `postram_` stack address is not
same -> call into `stage_entry` and follow the `main` function.
BUG=b:456953373
BRANCH=None
TEST=Able to build google/bluey.
Change-Id: I4eec24aff1c9d01180c3452a3631dd344656c771
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90403
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor the stack definition macros to explicitly define separate
memory regions for the stack, addressing resource conflicts on
certain SoCs like Qualcomm x1p42100.
The original STACK macro is split into PRERAM_STACK and
POSTRAM_STACK.
Motivation:
On the Qualcomm x1p42100 SoC, the boot flow presents two
constraints for the initial stack location:
- Boot IMEM is unavailable after the ADSP is loaded.
- The existing SSRAM stack address is reserved for QC QSEE by the
Trust Zone.
Solution:
- PRERAM_STACK: Used by coreboot (e.g., till romstage) for static
stack allocation (from an alternative SSRAM or BOOT IMEM region).
- POSTRAM_STACK: Used starting from ramstage, leveraging the
DRAM-mapped memory.
This conditional split allows coreboot to manage stack memory
independently for the limited environment before DRAM is fully
initialized (ENV_ROMSTAGE_OR_BEFORE), resolving the hardware memory
conflicts while maintaining compatibility with existing code via
aliasing.
BUG=b:456953373
BRANCH=None
TEST=Able to build google/bluey.
Change-Id: I6356adc63d595f59050e6dc5961404be4a9534c0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90402
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
On the X1P42100 SoC, the System Debug Image (SDI) flow is handled by
the Always-On Processor (AOP), unlike previous architectures (e.g.,
Kodiak) which utilized a dedicated 'QcSDI' image.
Rename the memory region at 0x14699000 from 'qcsdi' to 'aop_sdi' to
accurately reflect ownership by the AOP and to align with the new
chipset architecture. This change clarifies the memory map and serves
as a prerequisite for removing legacy QcSDI artifacts once the
modern SDI flow is fully enabled.
BUG=b:456953373
TEST=Build and boot on google/quenbih target.
Change-Id: Ic5626c06decaadfd459aa21bde4efcfec92e1e47
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90505
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The script was failing when origin/main doesn't exist. Instead of
trying to detect or use a main branch, simply save the current HEAD
hash and restore it when done. This works regardless of branch names
or remote configuration.
Also improve the clean check to use git diff-files instead of
comparing to a specific branch.
Change-Id: I237de4b1e8a06fd4e1e3ef08286208c130e7a6bd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90502
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace the incorrect Intel confidential license header with the
proper BSD license header in the MemInfoHob.h file to align with
the standard licensing used for Intel FSP vendorcode.
BUG=None
TEST=None
Change-Id: I242d9abedc2910f819c70be597c5d1cbca996a2a
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This fixes the build failure for commit 0b4d41004 (mb/lenovo/sklkbl: Add
Lenovo Thinkpad X280 as a variant) caused by a discrepancy between
memory/Makefile.mk and the actual content of spd/ddr4.
Change-Id: I92a4446e7bd457a7f09a107a0cb0fe1d7a6e1de4
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90503
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This proliferates the fixes from commit e5d10e5d23, CB:90023 ("mb/
lenovo/t480: Fix headphone jack") to the other SKL/KBL Thinkpad
variants T580, T470s, and T480s. This has been only validated on the
former two machines, but since the hardware changes between the
different models appear to be minimal, it should be safe to deploy
this fix to the T480s variant blindly.
Change-Id: I1edf8dc33231b9d1e1cf2eaf3f4f296736b7be32
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The hardware of this machine is mostly identical to the already
supported Thinkpad Tx80 machines. Minor differences are the absence of
SODIMM slots (i.e. all RAM is soldered on), two fewer eDP lane pairs,
and different PCIe lane assignment.
All the hardware configuration settings (VBT, GPIO register dumps,
hda verbs, and so on) have been obtained running the latest BIOS/EC
firmware (1.59/N20ET74W, 1.15/N20HT28W). PCIe port assignments as well
as USB, RAM SPD and GPIO assignments have been cross-checked against
publicly available schematics (Finn-1).
Basic functionality has been validated on a Thinkpad X280 part number
20KF-002QUS with 16GB onboard RAM, i7-8650U CPU. The laptop has been
tested with SeaBIOS 1.17 as a payload booting either debian 13 or
Windows 10. A cursory check of the hardware (video, wifi, audio, wired
ethernet, reboot, sleep) shows no issues. This patch also includes a
fix for the headphone jack detection that's been already validated
on the Thinkpad T480 with commit e5d10e5d23 ("mb/lenovo/t480: Fix
headphone jack").
Change-Id: Ia8e6c40b200dee240d08d79253fbbe0842882a80
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90254
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Logs such as "DRAM-K: calibration failed: status = 1" give little
information about the failure reason. Add get_status_string() and use it
to print the return status as a string.
Change-Id: If20282f0de7ba8ce884d0016fe8da1dc93a33ea4
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90484
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Optimize the `sdram_size` function by caching the calculated SDRAM
size in a static variable. This prevents redundant calls to
`mtk_dram_size()` or `mem_chip_info_total_density_bytes()` if the size
has already been determined, improving performance in scenarios where
`sdram_size` is called multiple times.
BUG=none
TEST=emerege-tanjiro coreboot
Change-Id: I0ca0df80ee9cb781a5bb6d55ee28a2c1153be0ad
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90485
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
