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device/azalia: Repurpose azalia_set_bits() for link-reset only

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The azalia_set_bits() function does some sequencing specific to the
CRST# bit. Name it accordingly and adapt its signature.

The while loop was also changed to match the other functions (e.g.
wait_for_ready()).

TEST= Verbs were loaded correctly on off-tree HP ProBook 450 G3.

Change-Id: I5ac766f2ddf8b48b436a54469815bf799ae31d52
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89652
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber 2024-07-20 13:38:07 +02:00 • committed by Matt DeVillier
commit 6e074550a5
1 changed files with 12 additions and 15 deletions
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27
src/device/azalia_device.c
View file

@ -9,38 +9,35 @@
#include <timer.h>
#include <types.h>
static enum cb_err azalia_set_bits(void *port, u32 mask, u32 val)
static enum cb_err azalia_assert_reset(u8 *base, bool reset)
{
const u32 val = reset ? 0 : HDA_GCTL_CRST; /* active-low CRST# */
struct stopwatch sw;
u32 reg32;
clrsetbits32(port, mask, val);
clrsetbits32(base + HDA_GCTL_REG, HDA_GCTL_CRST, val);
/* Wait for readback of register to match what was just written to it */
/* Wait for the controller to complete the link-reset sequence */
stopwatch_init_msecs_expire(&sw, 50);
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
reg32 = read32(port);
reg32 &= mask;
} while ((reg32 != val) && !stopwatch_expired(&sw));
u32 reg32 = read32(base + HDA_GCTL_REG);
if ((reg32 & HDA_GCTL_CRST) == val)
return CB_SUCCESS;
} while (!stopwatch_expired(&sw));
/* Timeout occurred */
if (stopwatch_expired(&sw))
return CB_ERR;
return CB_SUCCESS;
return CB_ERR;
}
enum cb_err azalia_enter_reset(u8 *base)
{
/* Set bit 0 to 0 to enter reset state (BAR + 0x8)[0] */
return azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0);
return azalia_assert_reset(base, true);
}
enum cb_err azalia_exit_reset(u8 *base)
{
/* Set bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) != CB_SUCCESS)
if (azalia_assert_reset(base, false) != CB_SUCCESS)
return CB_ERR;
/* Codecs have up to 25 frames (at 48kHz) to signal an