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mb/google/ocelot/var/ocelot: disable ISH UART0 RX pin

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On WCL RVP, ISH (Intel Sensor Hub) shares UART with FPS (Finger Print
Sensor), we can enable either ISH UART or FPS UART, or disable both
UART by changing the DIP switch settings. When DIP switch is not set
for ISH, ISH RX signal is disconnected, causing ISH low power mode
failure. Therefore, NC ISH RX pin mux to minimize the impact on ISH PM.
As a result, ISH console won't accept input since this pin is not
connected.

BUG=b:428084925
TEST=DIP SW1317 3-6, 4-5 on WCL RVP DT card ON to enable FPS UART,
ISH main firmware boots up and runs successfully.
SW1317 all switches OFF to disable both FPS and ISH UART, ISH main
firmware boots up and runs successfully.
Put system into suspend state and resume back. System enters into
low power mode as substate_residencies are updated. Verified using
console command "cat /sys/kernel/debug/pmc_core/substate_residencies".

Change-Id: I1165e0151c0a6d0e82038215703626e863739b39
Signed-off-by: Megha Verma <megha.verma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bhat D, Krishna P <krishna.p.bhat.d@intel.com>
Reviewed-by: P, Usha <usha.p@intel.com>
This commit is contained in:
Megha Verma 2025-11-13 14:29:50 +05:30 • committed by Matt DeVillier
commit 1b5f105595
2 changed files with 2 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/mainboard/google/ocelot/variants/ocelot/fw_config.c
View file

@ -392,8 +392,6 @@ static const struct pad_config ish_disable_pads[] = {
PAD_NC(GPP_B22, NONE),
/* GPP_B23: ISH_GP_6_SNSR_HDR */
PAD_NC(GPP_B23, NONE),
/* GPP_D05: ISH_UART0_ECAIC_RXD */
PAD_NC(GPP_D05, NONE),
/* GPP_D06: ISH_UART0_ECAIC_TXD */
PAD_NC(GPP_D06, NONE),
/* GPP_F23: SMC_LID / ISH_GP9A*/
@ -413,8 +411,6 @@ static const struct pad_config ish_enable_pads[] = {
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
/* GPP_B23: ISH_GP_6_SNSR_HDR */
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
/* GPP_D05: ISH_UART0_ECAIC_RXD */
PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2),
/* GPP_D06: ISH_UART0_ECAIC_TXD */
PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
/* GPP_F23: SMC_LID / ISH_GP9A*/

2
src/mainboard/google/ocelot/variants/ocelot/gpio.c
View file

@ -135,6 +135,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_D02, 0, DEEP),
/* GPP_D03: X4_SLOT_WAKE_N */
PAD_CFG_GPI_SCI_LOW(GPP_D03, NONE, DEEP, LEVEL),
/* GPP_D05: disable ISH_UART0_RXD */
PAD_NC(GPP_D05, NONE),
/* GPP_D07: ISH_UART0_RTS_N_SNSR_HDR */
PAD_NC(GPP_D07, NONE),
/* GPP_D08: ISH_UART0_CTS_N_SNSR_HDR */