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vc/intel/fsp/fsp2_0/wildcatlake: Update WCL FSP headers to FSP WCL.3393.02

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Update Wildcatlake FSP headers from version WCL.3393.02

FspmUpd.h: Add below upds
* Vdd2HVoltage
* Vdd1Voltage
* Vdd2LVoltage
* VddqVoltage

FspsUpd.h: Add below upds
* UfsInlineEncryption
* MaxActiveDisplays

MemInfoHob.h:
* PprTargetedStatus - PPR status of each Targeted PPR request

BUG=b:464402767
TEST=Able to build google/ocelot with the latest header changes

Change-Id: I66f22452fb7cd771752afe8bd7c0c3e5dac2106e
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This commit is contained in:
Sowmya V 2025-12-12 21:03:26 +05:30 • committed by Matt DeVillier
commit fad9878a3e
3 changed files with 47 additions and 5 deletions
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26
src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
View file

@ -3121,7 +3121,31 @@ typedef struct {
/** Offset 0x0B31 - Reserved
**/
UINT8 Reserved93[55];
UINT8 Reserved93[17];
/** Offset 0x0B42 - VDD2 Voltage
Voltage is multiple of 5mV where 0 means Auto.
**/
UINT16 Vdd2HVoltage;
/** Offset 0x0B44 - VDD1 Voltage
Voltage is multiple of 5mV where 0 means Auto.
**/
UINT16 Vdd1Voltage;
/** Offset 0x0B46 - VDD2L Voltage Override
Voltage is multiple of 5mV where 0 means Auto.
**/
UINT16 Vdd2LVoltage;
/** Offset 0x0B48 - VDDQ Voltage Override
Voltage is multiple of 5mV where 0 means Auto.
**/
UINT16 VddqVoltage;
/** Offset 0x0B4A - Reserved
**/
UINT8 Reserved94[30];
} FSP_M_CONFIG;
/** Fsp M UPD Configuration

22
src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspsUpd.h
View file

@ -458,9 +458,17 @@ typedef struct {
**/
UINT8 UfsEnable[2];
/** Offset 0x014D - Reserved
/** Offset 0x014D - UFS Inline Encryption enable/disable
Enable/Disable UFS Inline Encryption feature, One byte for each Controller - (1,0)
to enable Inline Encryption for controller 0 and (0, 1) to enable Inline Encryption
for controller 1
$EN_DIS
**/
UINT8 Reserved12[4];
UINT8 UfsInlineEncryption[2];
/** Offset 0x014F - Reserved
**/
UINT8 Reserved12[2];
/** Offset 0x0151 - Enable/Disable PCIe tunneling for USB4
Enable/Disable PCIe tunneling for USB4, default is enable
@ -2026,9 +2034,15 @@ typedef struct {
**/
UINT8 LidStatus;
/** Offset 0x1401 - Reserved
/** Offset 0x1401 - Select MaxActiveDisplays
Max Active Display : 0 - Default VBT, 1 - 1 display, 2 - 2 displays, Maximum supported
is 2 displays only
**/
UINT8 Reserved50[67];
UINT8 MaxActiveDisplays;
/** Offset 0x1402 - Reserved
**/
UINT8 Reserved50[66];
/** Offset 0x1444 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.

4
src/vendorcode/intel/fsp/fsp2_0/wildcatlake/MemInfoHob.h
View file

@ -35,6 +35,9 @@ extern EFI_GUID gSiMemoryPlatformDataGuid;
#define _MAX_RANK_IN_CHANNEL (4) ///< The maximum number of ranks per channel.
#define _MAX_SDRAM_IN_DIMM (5) ///< The maximum number of SDRAMs per DIMM.
// Must match the corresponding definition in CMrcExtTypes.h
#define PPR_REQUEST_MAX (2)
// Must match definitions in
// Intel\OneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h
#define HOB_MAX_SAGV_POINTS 4
@ -359,6 +362,7 @@ typedef struct {
BOOLEAN MixedEccDimms; ///< TRUE if both ECC and nonECC Dimms were detected in the system
UINT8 MaxRankCapacity; ///< Maximum possible rank capacity in [GB]
UINT16 PprFailingChannelBitMask; ///< PPR failing channel mask
BOOLEAN PprTargetedStatus[PPR_REQUEST_MAX]; ///< PPR status of each Targeted PPR request (0 = Targeted PPR was successful, 1 = PPR failed)
} MEMORY_INFO_DATA_HOB;
/**