This patch configures the GPIO pins for ISH to notify EC about the
tablet mode change in accordance with schematic_20240607.
BUG=b:347811875
TEST=Build and boot google/trulo. Placed the device in tabletmode & on
EC console,"tabletmode" command shows "tablet mode".
Change-Id: Id22e397e46b522428ffdabe34a445ed7e4fb6fc5
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This reverts commit 88a496a9c8.
This workaround is not valid with the latest Intel PRQ silicon,
so I'm dropping it now. Additionally, able to boot to ChromeOS without
any hang, and I also ran an S0ix cycle without any failures.
BUG=b:244082753
TEST=Able to boot google/rex0 to CrOS.
Change-Id: Idf0da5841705888d2787f61dd6e6fada2fbe3e3e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84368
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes the redundant crashlog config (SOC_INTEL_CRASHLOG)
entry from BOARD_GOOGLE_BRYA0 and BOARD_GOOGLE_BRASK.
BOARD_GOOGLE_BRYA_COMMON already selects a crashlog config, and
brya0/brask board eventually selects the BOARD_GOOGLE_BRYA_COMMON
config, making SOC_INTEL_CRASHLOG redundant.
TEST=Successfully built and booted google/brya0.
Change-Id: Iaff7954d4dafb4c6ca72a1521dfb434fb36b495a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84364
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes the redundant crashlog config (SOC_INTEL_CRASHLOG)
entry from BOARD_GOOGLE_BASEBOARD_BROX. BOARD_GOOGLE_BROX_COMMON
already selects a crashlog config, and brox baseboard eventually selects
the BOARD_GOOGLE_BROX_COMMON config, making SOC_INTEL_CRASHLOG
redundant.
TEST=Successfully built and booted google/brox.
Change-Id: Idcb03d13ee3943f188246663d47f47cb8afccbd9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84363
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Commit bc8f5405b5 ("tgl mainboards: Move usb{2,3}_ports settings into
XHCI device scope") not only moved the USB port definitions under the
XHCI device reference, but also combined multiple register definitions.
In doing so, it broke the inheritance from the baseboard, since the
variant overridetree registers now replaced the entire usb2_ports/
usb3_ports structs, rather than replacing individual array elements
therein. This resulted in any USB ports inherited from the baseboard
and not overridden by the variant being non-functional as they were
not included in the resulting combined devicetree.
To fix this, return to overriding individual array elements in the
usb2/3_ports structs.
TEST=build/boot google/drobit. Verify all USB ports present and
functional. Verify mainboard/static.c in built shows all ports.
Change-Id: I54921fa4ecf594a1ecbcfa7c45e5d745d4a95652
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84348
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
1)Modify jubilant cpu power limit setting depend on the brox
baseboad settgins,refer to CL:
https://review.coreboot.org/c/coreboot/+/83752
2)Update PL1,PL2, and PL4 value from jubilant thermal design
PL1 = 15W
PL2 = 41W
PL4 = 87W
BUG=b:364441688
BRANCH=None
TEST=Able to successfully boot on jubilant photo SKU1 and SKU2
boards with AC w/o battery.
Test on AC 65W and 45W w/o battery,and check the PL values.
Change-Id: I9a143d9faaa6c57b0d314c0ff6c0e55f556d7216
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
This commit refactors the long battery string implementation to include
caching of the EC response for battery information (model, serial, and
manufacturer).
This optimization reduces resume time by approximately 63ms by
minimizing communication overhead between the AP and EC.
BUG=b:366338622
TEST=Verified on google/tivviks_ufs:
* Long battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING is enabled.
* Short battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING=n.
Change-Id: I32ae5b5e618f20335f3d344811a97f1416df529e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Older ChromeOS devices (pre-CR50) do not support reading long battery
strings. This commit adds a Kconfig option,
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING, to enable or disable this
feature.
This allows devices with TPM_GOOGLE (CR50/TI50) to read and display
long battery strings, while older devices like google/link, wolf, samus,
and chell will continue to display only the first 8 characters.
This change ensures compatibility with older devices while enabling
the display of complete battery information on newer platforms.
BUG=b:366338622
TEST=Verified on google/tivviks_ufs:
* Long battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING is enabled.
* Short battery string is displayed when
EC_GOOGLE_CHROMEEC_READ_BATTERY_LONG_STRING=n.
Change-Id: I7859809278b7e926bbe8beb1a0a9e12c7e6c220d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84352
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
When battery is disconnected and only adaptor is connected higher PL2
power draw causes cpu brown out and system does not boot to kernel. To
avoid this set Boot frequency UPD to 1. Reduce PL4 value to overcome
power spikes from SoC during boot. Remove Psys implementation as it
impacts active state platform performance.
BUG=b:335046538,b:329722827
BRANCH=None
TEST=Able to successfully boot on 3 different Brox proto2 SKU1
and SKU2 boards with 65W, 45W and 30W adaptors for 3
iterations of cold boot.
Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
FSP n-1 headers in vc/intel/fsp/fsp2_0/graniterapid are updated to
pass compilation with full platform codes.
Change-Id: I1d13ddd4db8409a4928bd1bf152a9c284d138e48
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
For Xeon-SP, DCACHE_BSP_STACK_SIZE is by default 0x10000. For GNR,
this default size is enough. Use the default size so that more
CAR spaces could be saved for other purpose.
Change-Id: I68a79df150c4954ef8d703987d7c0bb446ba4cda
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84302
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
List of changes:
1. Add required SoC programming till ramstage.
2. Include only required headers into include/soc.
3. Skeleton code used to call FSP-S API.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: I61930726ad0c765bfa1d72c5df893262be884834
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84332
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The calculation of non-eviction ways (used for cache-as-ram
configuration) has been simplified by removing conditional move
instructions and directly adding the remainder to the quotient.
This achieves the same ceiling operation but with potentially improved
efficiency (less instructions).
No functional changes are expected.
TEST=Able to build and boot google/rex.
Change-Id: I7cf5ff19ec440d049edc3bf52c660dea96b1f08a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
BUG=b:362672785
TEST=Build Brox firmware and boot to OS. Ensure that the BRDS table is
populated under the right ACPI device scope.
Scope (\_SB.PCI0.XHCI.RHUB.HS10)
{
Name (BRDS, Package (0x02)
{
0x00000001,
Package (0x0A)
{
0x00000012,
0x00000001,
0x00000001,
0x7C,
0x70,
0x70,
0x70,
0x70,
0x70,
0x70
}
})
}
Change-Id: I9a74a995bca8d412b85c243c7f2f98c9917b5e76
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84296
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
With the release 20240910 of the Intel microcode repository, it also
includes the updated microcode file with version 0x129, which makes the
one from the coreboot blobs repo superfluous. Thus, use the one from the
Intel repository again.
Change-Id: I7fb58874719a8373072419e34b3f8923f7db927d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84295
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These identifiers are not included in the GPU list from Intel [1].
At the same time, 0x9B44 is not PCI DID of graphics device at all:
8086:9B44 - 10th Gen Core Processor Host Bridge/DRAM Registers [2].
[1] https://web.archive.org/web/20240731152818/https://
dgpu-docs.intel.com/devices/hardware-table.html
[2] https://web.archive.org/web/20231004011832/https://devicehunt.com/
view/type/pci/vendor/8086/device/9B44
Change-Id: I8ff7b062f930cb63ffd9caf240874742bd53fc23
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
According to the Intel GPU list[1], 0x3E9B is DID of "Intel UHD Graphics
630" for the Coffee Lake processor family and has already been added to
the pci_ids.h as PCI_IDE_INTEL_CFL_H_GT2.
At the same time, the real PCI DID for Comet Lake-H GT2 is 0x9BC2 [1],
which is missing in the file.
[1] https://web.archive.org/web/20240731152818/https://
dgpu-docs.intel.com/devices/hardware-table.html
Change-Id: Iacab0a03388af3f6fd5d78a597580037889e8ef2
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Should make the sorting order of the paths more obvious.
Change-Id: Ie73e717f37f80a11a903e99cc094ea4d76e1ca1f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83827
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Alder Lake "Client" FSP paths have been replaced by symlinks to
Raptor Lake in the FSP repo. Hence we get the same files anyway and
can spare us to maintain the individual paths.
Change-Id: Ia9b256ce1940894e2cf31acaa4a83ea39f6723b6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
These aren't used so remove them
Change-Id: I340b3474fba1bc7fbde520138ae99c3e355882bf
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reporting the battery serial number to ACPI causes Windows to say
there isn't a battery present. As the serial number is as useful as
waterproof towel, don't do it.
Change-Id: I97a28b1d8d7bb45ea4790c8125cd3c1bc52ee5f9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
As the merlin EC supports both the IT8987 and IT5570, move the
check into the code so the same variant directory can be used
for both chips.
Change-Id: I8c43a367e42f7e56ddd26b1c8fe7bf4b275d4ac3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83632
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the USB configs are in the devicetree, only the
bootblock_mainboard_early_init function remains in early_init.c. It is
identical between every variant except the E6230, which enabled fewer
decode ranges in the LPC_EN register. Enabling the additional decode
ranges probably shouldn't cause issues, so go with the majority.
TEST=Timeless builds do not change with the exception of the E6230.
Change-Id: Ic43915888f5893652991b7402ebab3bd3a2cf278
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Joxer experienced error messages during developer mode entry due to
failed USB-C1 probing.
This patch adds the `DB_USB DB_1C` probe directive to the `conn1`
device in the overridetree, ensuring USB-C1 is only probed when
`FW_CONFIG` supports the applicable hardware SKU.
This should resolve the error flood seen during dev mode entry on
Joxer.
BUG=b:364240631
TEST=Able to build and boot google/joxer to OS without any error.
w/o this patch:
send_packet: CrosEC result code 9
send_packet: CrosEC result code 3
Failed to get PD_MUX_INFO port1 ret:-3
update_all_tcss_ports_states: port C1: get_usb_pd_mux_info failed
send_packet: CrosEC result code 9
send_packet: CrosEC result code 3
Failed to get PD_MUX_INFO port1 ret:-3
w/ this patch:
No error reported during dev mode entry
Change-Id: I8cdefa01409d5a8a75032f30dacde40057e064dd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
The `!FSP_USE_REPO` is most specific, if we're not using the FSP repo,
we can ignore all the FSP-repo paths. Hence put these first.
Having `FSP_TYPE_IOT` selected is also more specific, we can ignore all
the "Client" paths then. This makes sure that we don't catch a "Client"
by accident (otherwise we'd have to add a `!FSP_TYPE_IOT` for those).
Change-Id: Ibe9931d8f964a337c46fde31a3bc22c69d40eded
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Extracted from NDA spec #56995:
"The A/B recovery scheme formally separates the SPI flash space into
different partitions; a primary, “A” and secondary, “B”, which hold
the same set of system firmware. Under this scheme, the partitions A
and B can hold identical contents initially, but each partition can be
updated individually.
Normally the system boots from partition A, but if the A partition is
found to be corrupted, the system will switch to partition B and
boot. The OEM BIOS can then choose to continue the boot from partition
B, or repair partition A using contents from partition B."
The Cezanne platform supports both A/B recovery and no recovery
method. It needs this flag passed to amdfwtool to enable the A/B
recovery layout.
Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add a Kconfig choice to select the IGD UMA allocation, which selects a
precompiled ACPB binary with the corresponding UMA value set. Default
to the previous value (128MB) for non-ChromeOS builds, and 64MB for
ChromeOS as that is the value used there.
TEST=build/boot google/morphius, verify UMA size changes with selection
via dxdiag tool under Windows.
Change-Id: I6debd10527c33ce37ef3ada20955c8f7b7500039
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84237
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
