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mb/starlabs/starbook/adl: Alphabetize and group FSP UPDs

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Change-Id: I63612af7320dfdbe57029b898b4cf07e9d6f13b0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Sean Rhodes 2024-09-09 10:30:10 +01:00 • committed by Felix Held
commit 78f5c3b8c5
1 changed files with 2 additions and 15 deletions
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17
src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
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@ -1,22 +1,9 @@
chip soc/intel/alderlake
# Graphics
# TODO:
# register "panel_cfg" = "{
# .up_delay_ms = 200, // T3
# .backlight_on_delay_ms = 0, // T7
# .backlight_off_delay_ms = 50, // T9
# .down_delay_ms = 0, // T10
# .cycle_delay_ms = 500, // T12
# .backlight_pwm_hz = 200, // PWM
# }"
# FSP Memory
# FSP UPDs
register "eist_enable" = "true"
register "enable_c6dram" = "1"
register "sagv" = "SaGv_Enabled"
# FSP Silicon
register "eist_enable" = "true"
# Serial I/O
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,