tree: use boolean for hybrid_storage_mode

Change-Id: I84aad5497d17065f9d42776452f2d2d24cd50a91
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/mainboard/intel/adlrvp/devicetree.cb

@@ -83,7 +83,7 @@ chip soc/intel/alderlake
 	}"
 
 	# Hybrid storage mode
-	register "hybrid_storage_mode" = "1"
+	register "hybrid_storage_mode" = "true"
 
 	# Enable CPU PCIE RP 1 using CLK 0
 	register "cpu_pcie_rp[CPU_RP(1)]" = "{

src/mainboard/intel/adlrvp/devicetree_m.cb

@@ -76,7 +76,7 @@ chip soc/intel/alderlake
 	}"
 
 	# Hybrid storage mode
-	register "hybrid_storage_mode" = "1"
+	register "hybrid_storage_mode" = "true"
 
 	# Enable CPU PCIE RP 1 using CLK 0
 	register "cpu_pcie_rp[CPU_RP(1)]" = "{

src/mainboard/msi/ms7d25/devicetree.cb

@@ -82,7 +82,7 @@ chip soc/intel/alderlake
 		[DDI_PORT_4] = DDI_ENABLE_HPD,
 	}"
 
-	register "hybrid_storage_mode" = "1"
+	register "hybrid_storage_mode" = "true"
 	register "dmi_power_optimize_disable" = "1"
 
 	# FIVR configuration

src/mainboard/msi/ms7e06/devicetree.cb

@@ -12,7 +12,7 @@ chip soc/intel/alderlake
 	register "pmc_gpe0_dw1" = "GPP_VPGIO"
 	register "pmc_gpe0_dw2" = "GPD"
 
-	register "hybrid_storage_mode" = "1"
+	register "hybrid_storage_mode" = "true"
 	register "dmi_power_optimize_disable" = "1"
 
 	# FIVR configuration