These identifiers are not included in the GPU list from Intel [1].
At the same time, 0x9B44 is not PCI DID of graphics device at all:
8086:9B44 - 10th Gen Core Processor Host Bridge/DRAM Registers [2].
[1] https://web.archive.org/web/20240731152818/https://
dgpu-docs.intel.com/devices/hardware-table.html
[2] https://web.archive.org/web/20231004011832/https://devicehunt.com/
view/type/pci/vendor/8086/device/9B44
Change-Id: I8ff7b062f930cb63ffd9caf240874742bd53fc23
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
According to the Intel GPU list[1], 0x3E9B is DID of "Intel UHD Graphics
630" for the Coffee Lake processor family and has already been added to
the pci_ids.h as PCI_IDE_INTEL_CFL_H_GT2.
At the same time, the real PCI DID for Comet Lake-H GT2 is 0x9BC2 [1],
which is missing in the file.
[1] https://web.archive.org/web/20240731152818/https://
dgpu-docs.intel.com/devices/hardware-table.html
Change-Id: Iacab0a03388af3f6fd5d78a597580037889e8ef2
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This just orders the EXCLUDED_DIRS directories in a row based manner,
since there are quite a few them now and it is arguably easier to read
and to add new directories if they are written in a row based fashion.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I802aece355bba4900e71824d802c4b2438726e84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Should make the sorting order of the paths more obvious.
Change-Id: Ie73e717f37f80a11a903e99cc094ea4d76e1ca1f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83827
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Alder Lake "Client" FSP paths have been replaced by symlinks to
Raptor Lake in the FSP repo. Hence we get the same files anyway and
can spare us to maintain the individual paths.
Change-Id: Ia9b256ce1940894e2cf31acaa4a83ea39f6723b6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
These aren't used so remove them
Change-Id: I340b3474fba1bc7fbde520138ae99c3e355882bf
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reporting the battery serial number to ACPI causes Windows to say
there isn't a battery present. As the serial number is as useful as
waterproof towel, don't do it.
Change-Id: I97a28b1d8d7bb45ea4790c8125cd3c1bc52ee5f9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
As the merlin EC supports both the IT8987 and IT5570, move the
check into the code so the same variant directory can be used
for both chips.
Change-Id: I8c43a367e42f7e56ddd26b1c8fe7bf4b275d4ac3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83632
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the USB configs are in the devicetree, only the
bootblock_mainboard_early_init function remains in early_init.c. It is
identical between every variant except the E6230, which enabled fewer
decode ranges in the LPC_EN register. Enabling the additional decode
ranges probably shouldn't cause issues, so go with the majority.
TEST=Timeless builds do not change with the exception of the E6230.
Change-Id: Ic43915888f5893652991b7402ebab3bd3a2cf278
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
ifdtool will exit with success while encountering an unrecognized flag.
For example, -g is a newly introduced flag, when we want to call it with
an older version of ifdtool, we will get the return value 0 and cause
confusion.
This patch change the exit status for unrecognized flags and doesn't
change the exit status for -h and -?.
BUG=b:362983041
BRANCH=none
TEST=futility update --servo --image /var/tmp/image.bin --quirks
unlock_csme on the servo host with old ifdtool
Signed-off-by: Hsuan Ting Chen <roccochen@google.com>
Change-Id: I046ad7ec790cda41a98a1de5cd730d32f65a9067
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Joxer experienced error messages during developer mode entry due to
failed USB-C1 probing.
This patch adds the `DB_USB DB_1C` probe directive to the `conn1`
device in the overridetree, ensuring USB-C1 is only probed when
`FW_CONFIG` supports the applicable hardware SKU.
This should resolve the error flood seen during dev mode entry on
Joxer.
BUG=b:364240631
TEST=Able to build and boot google/joxer to OS without any error.
w/o this patch:
send_packet: CrosEC result code 9
send_packet: CrosEC result code 3
Failed to get PD_MUX_INFO port1 ret:-3
update_all_tcss_ports_states: port C1: get_usb_pd_mux_info failed
send_packet: CrosEC result code 9
send_packet: CrosEC result code 3
Failed to get PD_MUX_INFO port1 ret:-3
w/ this patch:
No error reported during dev mode entry
Change-Id: I8cdefa01409d5a8a75032f30dacde40057e064dd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Commit 35599f9a66 (Docs: Replace Recommonmark with MyST Parser)
converted recommonmark style toctrees in bulk using a script. This was
done by searching for lists of references, which is how recommonmark
denoted toctree entries. However, this also converted lists of external
URLs, which would not normally be included in the toctree. Revert these
cases back to lists of URLs as they were before the migration.
Change-Id: Ie4da3d908d4b84c2c7e3572fb4baaeed1f8edb45
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The content of this page fits lib the best, which also reflects the
location of the rmodule runtime code in the src tree. This also fixes a
"document isn't included in any toctree" warning from Sphinx since it is
now added to the lib/index.md toctree.
Change-Id: I86545f4c1a7e1b3ccefa4f6085e764536f33f29c
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Increase the header levels of headers following the initial "Relocatable
Modules (rmodules)" so that there is only one title for the page with
the other headings as subheadings. Also fix header capitalization while
we're here.
Change-Id: I72ae99ba10bf5b2386da2cc702efaf25328d6811
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84239
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `!FSP_USE_REPO` is most specific, if we're not using the FSP repo,
we can ignore all the FSP-repo paths. Hence put these first.
Having `FSP_TYPE_IOT` selected is also more specific, we can ignore all
the "Client" paths then. This makes sure that we don't catch a "Client"
by accident (otherwise we'd have to add a `!FSP_TYPE_IOT` for those).
Change-Id: Ibe9931d8f964a337c46fde31a3bc22c69d40eded
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Currently, cbfstool prints the following error message when the added
file doesn't fit in the region:
E: Could not add [file, 1024 bytes (1 KB)@0x0]; too big?
It requires manual inspection to know the space left in the region. To
make that easier, also print the maximum empty CBFS entry size in the
error message:
E: Could not add file [header 76 + content 1024 bytes (1 KB)] @0x0;
Largest empty slot: 512 bytes
Change-Id: I00bcc83abe8b0a33dcd7b75521e6cfccd8953661
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Extracted from NDA spec #56995:
"The A/B recovery scheme formally separates the SPI flash space into
different partitions; a primary, “A” and secondary, “B”, which hold
the same set of system firmware. Under this scheme, the partitions A
and B can hold identical contents initially, but each partition can be
updated individually.
Normally the system boots from partition A, but if the A partition is
found to be corrupted, the system will switch to partition B and
boot. The OEM BIOS can then choose to continue the boot from partition
B, or repair partition A using contents from partition B."
The Cezanne platform supports both A/B recovery and no recovery
method. It needs this flag passed to amdfwtool to enable the A/B
recovery layout.
Change-Id: Id1c8028faee9c544628d65fd77be2a378ed7eab6
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add a Kconfig choice to select the IGD UMA allocation, which selects a
precompiled ACPB binary with the corresponding UMA value set. Default
to the previous value (128MB) for non-ChromeOS builds, and 64MB for
ChromeOS as that is the value used there.
TEST=build/boot google/morphius, verify UMA size changes with selection
via dxdiag tool under Windows.
Change-Id: I6debd10527c33ce37ef3ada20955c8f7b7500039
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84237
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MyST Parser uses {eval-rst} to denote embedded reStructuredText blocks,
not eval_rst as was previously used by recommonmark.
Change-Id: I3476d205605675690eb0d434f4ae9b7b2f091748
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84238
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Xeon-SP supports MMIO high range, a.k.a. MMIO range above 4G. FSP will
assign domain MMIO high windows from this range.
However, there will be unassigned parts among these high windows for
non-domain device usage (e.g. misc devices belonging to an IIO stack
but not belonged to any PCIe domains under that stack). This will cause
segmentation in MTRR UC coverage.
For example, in SPR-XCC where only CPM0/HQM0 are supported and
instantiated to PCIe domains, MMIO ranges are still reserved for
CPM1/HQM1. See more at src/soc/intel/xeon_sp/spr/ioat.c.
Reserve MMIO high range as a whole under domain0/00:0.0. During MTRR
calculation, this reservation will connect the discontinued domain MMIO
high windows together to form one continuous range, and save MTRR
register usage from inadequacy.
This change is initially raised for SPR but could be effective for GNR
as well.
TESTED = Build and boot in intel/archercity CRB, MTRR register usage
decreases from 7 to 3 in 2S system.
TESTED = Only setting MTRR for below 4GB ranges test fails with
LinuxBoot on SPR (through x86_setup_mtrrs_with_detect_no_above_4gb)
tsc: Detected 2000.000 MHz processor
last_pfn = 0x2080000 max_arch_pfn = 0x10000000000
x86/PAT: Configuration [0-7]: WB WC UC- UC WB WP UC- WT
WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing 129024MB of RAM.
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at arch/x86/kernel/cpu/mtrr/cleanup.c:978 mtrr_trim_uncached_memory+0x2b9/0x2f9
...
Call Trace:
? 0xffffffff8f600000
? setup_arch+0x4bb/0xaed
? printk+0x53/0x6a
? start_kernel+0x55/0x507
? load_ucode_intel_bsp+0x1c/0x4d
? secondary_startup_64_no_verify+0xc2/0xcb
random: get_random_bytes called from init_oops_id+0x1d/0x2c with crng_init=0
---[ end trace 0e56686fd458f0c5 ]---
update e820 for mtrr
modified physical RAM map:
modified: [mem 0x0000000000000000-0x0000000000000fff] reserved
...
modified: [mem 0x00000000ff000000-0x000000207fffffff] reserved
last_pfn = 0x6354e max_arch_pfn = 0x10000000000
Memory KASLR using RDRAND RDTSC...
x2apic: enabled by BIOS, switching to x2apic ops
Using GB pages for direct mapping
...
Initmem setup node 0 [mem 0x0000000000001000-0x000000006354dfff]
DMA zone: 28769 pages in unavailable ranges
DMA32 zone: 19122 pages in unavailable ranges
BUG: unable to handle page fault for address: ff24b56eba60cff8
BAD
Oops: 0000 [#1] SMP NOPTI
CPU: 0 PID: 0 Comm: swapper Tainted: G W 5.10.50 #2
...
Call Trace:
? set_pte_vaddr_p4d+0x24/0x35
? __native_set_fixmap+0x21/0x28
? map_vsyscall+0x35/0x56
? setup_arch+0xa00/0xaed
? printk+0x53/0x6a
? start_kernel+0x55/0x507
? load_ucode_intel_bsp+0x1c/0x4d
? secondary_startup_64_no_verify+0xc2/0xcb
CR2: ff24b56eba60cff8
---[ end trace 0e56686fd458f0c6 ]---
RIP: 0010:fill_pud+0xa/0x62
...
Kernel panic - not syncing: Attempted to kill the idle task!
---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]---
Change-Id: Ib2a0e1f1f13e797c1fab6aca589d060c4d3fa15b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83538
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use the AZALIA_PIN_DESC macro from include/device/azalia_device.h
instead of magic numbers, as well as the enums for each of the register
field values. The macros were generated by running util/hda-decoder
against the original azalia logs used for the original board ports.
TEST=Timeless builds for all variants did not change between main
and this patch
Change-Id: If5ecee39efbddbba101f820dead82efcb848b6bc
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84099
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Add a Kconfig choice to select the IGD UMA allocation. Default to the
previous value (32MB).
TEST=build/boot google/liara, verify UMA size changes with selection.
Change-Id: Ia53d6d39d4f06c896ec13808234144b89da101f8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84235
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add definitions for the GPIO pins on Panther Lake SoC,
as well as GPIO IRQ routing information and defines for ACPI ASL.
For now, add the following GPIO communities and GPIO groups:
Comm. 0: GPP_V, GPP_C
Comm. 1: GPP_F, GPP_E
Comm. 3: CPUJTAG, GPP_H, GPP_A, VGPIO3
Comm. 4: GPP_S
Comm. 5: GPP_B, GPP_D, VGPIO
ref doc:
- PT EDS vol2
- Panther Lake H GPIO Implementation Summary (#817954)
BUG=b:348678529
TEST=Verify on Intel Silicon platform for PTL using google/fatcat
mainboard. Note that these GPIO changes cannot be verified along as
they are merely data structure and defines for the SOC. With the
GPIO ASL, we should see the following GPIO instances under
/sys/bus/acpi/devices when booting to OS:
INTC10BC:00/ INTC10BC:01/ INTC10BC:02/ INTC10BC:03/ INTC10BC:04/
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Based on DOC #767454 (public) version 1.2. Allows to boot the
HARDKERNEL ODROID H4+ with N97 SoC. Without this patch the MCH ID
was not recognized and the SA driver did not pick up the stolen
ranges, causing the PCI MMIO allocation to be placed in the stolen
areas.
TEST=Boot HARDKERNEL ODROID H4+ with N97 SoC to Ubuntu 23.04.
Change-Id: I0fbdb12c6411e4109e68a13960b4570701629bc9
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84212
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add a Kconfig choice to select the default IGD memory allocation, for
users/boards which do not use an option table to set it.
TEST=build/boot google/link, verify IGD size changes with selection.
Change-Id: I83d57cf4657cfccbb21416c5da05eeff9e95a44f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The Max size of L2 table is 0x400. If we set it to other value, the
the A/B recovery image can not boot on Cezanne/Majolica platform.
The affected boards are Birman, Chausie, Skyrim, Mayan. Other boards
are binary identical. Tested on Skyrim and image can boot.
Change-Id: I2c0af6579dbe2a3a61e1fe9c79d69491fd45a5bb
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84194
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the `BUILDING_WITH_DEBUG_FSP` Kconfig option from SoC-specific
files to the FSP2_0 driver Kconfig to avoid duplication. Also slightly
improves the option's prompt and help text.
TEST=Built and booted google/rex successfully.
Change-Id: I5c3dce59c396f6c1665a3ed1b8c1bb5df0f5a8d4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This patch adds a new Kconfig option `FSP_PUBLISH_MBP_HOB` to
control the creation of the ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP.
Disabling this option can improve boot time on platforms that
do not utilize the MBP HOB, such as ChromeOS devices.
The option is disabled by default on ChromeOS and enabled
by default on other platforms.
On ADL-P based platforms, this option is forced to be enabled
as ADL-P FSP relies on MBP HOB for ChipsetInit version for
ChipsetInit sync.
Removed SoC specific implementation of `FSP_PUBLISH_MBP_HOB` config
from MTL and TGL config file.
TEST=Tested on ADL-P and ADL-N platforms. Verified that MBP HOB is
created when `FSP_PUBLISH_MBP_HOB` is enabled and not created when
it is disabled.
Also verified that the system boots successfully in both cases.
Change-Id: I21da00259c0b9bcca6f545291a6259e9cce8d900
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Signing is performed with test keys by default, set
CONFIG_SIGNING_KEYS_DIR to a non-empty value to use other keys.
Depending on the version of the Talos II firmware this alone might not
allow booting because coreboot replaces only part of the stock firmware
and its newer versions enable secure boot by default (not to be confused
with SecureBoot in EFI). The signing performed in this commit is still
a prerequisite and might as well be done on its own. Fixing operation
with newer stock firmware will be done in a follow-up change.
Change-Id: Id88baef5ecb1f8ffd74a7f464bbbaaaea0ca643d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested using `edk2` from
`github.com/starlabsltd/edk2/tree/uefipayload_vs`:
* Windows 11
* Ubuntu 22.04
* Manjaro 22
No known issues.
https://starlabs.systems/pages/byte-specification
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Idff2d883a8c29f0fee9d633708aac92061a45132
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add specific virtual wire mapping structure for:
- First pad group does not starts with bit position 0.
- vw_index and position are not continuous in between groups within a
community.
BUG=
TEST=boot to OS and use iotools to read the registers that use 16-bit
port ID such as IOM AUX Bias Ctrl register to verify the 16-bit group
ID field.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I986d4f4fe59b110e5075cab8742dfe8b336d034b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
According to the Intel OPS spec, the DC power from display is
12~19V@8A max. It can't set PsysPmax by unknown voltage, so get
voltage by ec command "ectool adcread 4" then calculate PsysPmax value.
The OPS display can supply 90W power, configure psys_pl2 to limit
the system power to 90W.
BUG=b:329037849
BRANCH=firmware-brya-14505.B
TEST= USE="fw_debug" LOCALES="en" emerge-brask chromeos-bmpblk
intel-rplfsp intel-adlfsp coreboot chromeos-bootimage
Check adcread value by ectool adcread 4. If get 19540, PsysPmax
should be 19540 * 8000 ~= 156 W.
Check FSP debug log have the following message.
PsysPmax = 156W
Change-Id: Ic6e9c6ce9f3179c7d63c1169695fbc23188456dd
Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
This patch skips event logging for current boot information at ramstage
if CSE sync is scheduled at payload. Given that CSE sync could initiate
a system reset, resulting in redundant boot information logs, the
payload should handle the logging of boot information following CSE
sync.
BUG=b:360082747
TEST=Verified elog boot info is not logged at ramstage
Change-Id: Ia29ec350facc6850c04bb988027ecb146e648a50
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84120
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add control for the 1.2V enable pin in VCM to comply the mipi camera
power sequence.
2.8V enable --> 1.2V enable --> reset
BUG=b:362386165
TEST=Run ITS test
Change-Id: I495b2e266ee3d24ed3334bb9c173b3993d095e8e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84211
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
