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amdfwtool: Set L2 table size as 0x400

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The Max size of L2 table is 0x400. If we set it to other value, the
the A/B recovery image can not boot on Cezanne/Majolica platform.

The affected boards are Birman, Chausie, Skyrim, Mayan. Other boards
are binary identical. Tested on Skyrim and image can boot.

Change-Id: I2c0af6579dbe2a3a61e1fe9c79d69491fd45a5bb
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84194
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Zheng Bao 2024-08-26 19:21:05 +08:00 • committed by Felix Held
commit 9ee17ffceb
2 changed files with 4 additions and 3 deletions
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6
util/amdfwtool/amdfwtool.c
View file

@ -870,7 +870,7 @@ static void integrate_psp_ab(context *ctx, psp_directory_table *pspdir,
BUFF_TO_RUN_MODE(*ctx, pspdir2, AMD_ADDR_REL_BIOS);
pspdir->entries[count].address_mode =
SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS);
pspdir->entries[count].size = _MAX(TABLE_ALIGNMENT,
pspdir->entries[count].size = _MAX(TABLE_L2_SIZE_MAX,
pspdir2->header.num_entries *
sizeof(psp_directory_entry) +
sizeof(psp_directory_header));
@ -1216,11 +1216,11 @@ static void integrate_bios_levels(context *ctx, amd_cb_config *cb_config)
if (cb_config->recovery_ab) {
add_psp_firmware_entry(ctx, ctx->pspdir2, ctx->biosdir2,
AMD_FW_BIOS_TABLE, TABLE_ALIGNMENT);
AMD_FW_BIOS_TABLE, TABLE_L2_SIZE_MAX);
if (ctx->pspdir2_b != NULL)
add_psp_firmware_entry(ctx, ctx->pspdir2_b,
ctx->biosdir2_b, AMD_FW_BIOS_TABLE,
TABLE_ALIGNMENT);
TABLE_L2_SIZE_MAX);
} else if (ctx->biosdir2) {
current_table_save = ctx->current_table;
ctx->current_table = BUFF_TO_RUN_MODE(*ctx, ctx->biosdir, AMD_ADDR_REL_BIOS);

1
util/amdfwtool/amdfwtool.h
View file

@ -11,6 +11,7 @@
#define ERASE_ALIGNMENT 0x1000U
#define TABLE_ALIGNMENT 0x1000U
#define TABLE_L2_SIZE_MAX 0x400U
#define BLOB_ALIGNMENT 0x100U
#define TABLE_ERASE_ALIGNMENT _MAX(TABLE_ALIGNMENT, ERASE_ALIGNMENT)
#define BLOB_ERASE_ALIGNMENT _MAX(BLOB_ALIGNMENT, ERASE_ALIGNMENT)