mb/starlabs/byte_adl: Add Alder Lake N Byte Mk II

Tested using `edk2` from
`github.com/starlabsltd/edk2/tree/uefipayload_vs`:
* Windows 11
* Ubuntu 22.04
* Manjaro 22

No known issues.

https://starlabs.systems/pages/byte-specification

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Idff2d883a8c29f0fee9d633708aac92061a45132
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>

Documentation/mainboard/index.md

@@ -333,6 +333,8 @@ StarLite Mk IV <starlabs/lite_glkr.md>
 StarLite Mk V <starlabs/lite_adl.md>
 StarBook Mk V <starlabs/starbook_tgl.md>
 StarBook Mk VI <starlabs/starbook_adl.md>
+Byte Mk II <starlabs/byte_adl.md>
+
 Flashing devices <starlabs/common/flashing.md>
 ```
 

Documentation/mainboard/starlabs/byte_adl.md

@@ -0,0 +1,83 @@
+# StarBook Mk V
+
+## Specs
+
+- CPU (full processor specs available at https://ark.intel.com)
+    - Intel N200 (Alder Lake)
+- EC
+    - ITE IT5570E
+    - Charger, using AC adapter or USB-C PD
+    - Suspend / resume
+- GPU
+    - Intel® Iris® Xe Graphics
+    - GOP driver is recommended, VBT is provided
+    - HDMI video
+    - DisplayPort video
+    - USB-C DisplayPort video
+- Memory
+    - 1 x DDR4 SODIMM
+- Networking
+    - 9560 2230 WiFi / Bluetooth
+    - Realtek RLT8111 1Gbps
+    - Realtek RLT8125B 2.5Gbps
+- Sound
+    - SoundWire SN6140
+    - Combined headphone / microphone 3.5-mm jack
+    - HDMI audio
+    - USB-C DisplayPort audio
+- Storage
+    - M.2 PCIe SSD
+- USB
+    - 2 x USB 3.1 Gen 2 Type-A (front)
+    - 1 x USB 3.1 Gen 2 Type-C (front)
+    - 2 x USB 3.1 Gen 2 Type-A (back)
+
+## Building coreboot
+
+Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file.
+
+### Preliminaries
+
+Prior to building coreboot the following files are required:
+* Intel Flash Descriptor file (descriptor.bin)
+* Intel Management Engine firmware (me.bin)
+* ITE Embedded Controller firmware (ec.bin)
+
+The files listed below are optional:
+- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
+
+These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
+
+### Build
+
+The following commands will build a working image:
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_byte_adl
+make
+```
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Vendor              | Winbond    |
++---------------------+------------+
+| Model               | W25Q256.V  |
++---------------------+------------+
+| Size                | 32 MiB     |
++---------------------+------------+
+| Package             | SOIC-8     |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+| External flashing   | yes        |
++---------------------+------------+
+```
+
+Please see [here](common/flashing.md) for instructions on how to flash with fwupd.

src/mainboard/starlabs/byte_adl/Kconfig

@@ -0,0 +1,104 @@
+config BOARD_STARLABS_BYTE_SERIES
+	def_bool n
+	select EC_STARLABS_ITE
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_TPM2
+	select NO_UART_ON_SUPERIO
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select VALIDATE_INTEL_DESCRIPTOR
+
+config BOARD_STARLABS_BYTE_ADL
+	select BOARD_ROMSIZE_KB_16384
+	select BOARD_STARLABS_BYTE_SERIES
+	select CRB_TPM
+	select DRIVERS_INTEL_PMC
+	select EC_STARLABS_MERLIN
+	select EC_STARLABS_NEED_ITE_BIN
+	select HAVE_INTEL_PTT
+	select SOC_INTEL_ALDERLAKE
+	select SOC_INTEL_ALDERLAKE_PCH_N
+	select SOC_INTEL_COMMON_BLOCK_TCSS
+	select SOC_INTEL_CRASHLOG
+	select SPI_FLASH_WINBOND
+
+if BOARD_STARLABS_BYTE_SERIES
+
+config CONSOLE_SERIAL
+	default n if !EDK2_DEBUG
+
+config D3COLD_SUPPORT
+	default n
+
+config DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
+
+config DIMM_SPD_SIZE
+	default 512
+
+config EC_GPE_SCI
+	default 0x6e
+
+config EC_STARLABS_ADD_ITE_BIN
+	default n
+
+config EC_STARLABS_ITE_BIN_PATH
+	string
+	depends on EC_STARLABS_NEED_ITE_BIN
+	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin"
+
+config EC_VARIANT_DIR
+	default "merlin"
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/vboot.fmd" if VBOOT
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
+
+config IFD_BIN_PATH
+	string
+	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/flashdescriptor.bin"
+
+config MAINBOARD_DIR
+	default "starlabs/byte_adl"
+
+config MAINBOARD_FAMILY
+	string
+	default "Y2"
+
+config MAINBOARD_PART_NUMBER
+	default "Byte Mk II"
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "Byte"
+
+config ME_BIN_PATH
+	string
+	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/intel_me.bin"
+
+config POWER_STATE_DEFAULT_ON_AFTER_FAILURE
+	default n
+
+config EDK2_BOOTSPLASH_FILE
+	string
+	default "3rdparty/blobs/mainboard/starlabs/Logo.bmp"
+
+config SOC_INTEL_CSE_SEND_EOP_EARLY
+	default n
+
+config UART_FOR_CONSOLE
+	default 0
+
+config USE_PM_ACPI_TIMER
+	default n
+
+config VBOOT
+	select VBOOT_VBNV_FLASH
+
+config VARIANT_DIR
+	default "mk_ii"
+
+endif

src/mainboard/starlabs/byte_adl/Kconfig.name

@@ -0,0 +1,4 @@
+comment "Star Labs Byte Series"
+
+config BOARD_STARLABS_BYTE_ADL
+	bool "Star Labs Byte Mk II (N200)"

src/mainboard/starlabs/byte_adl/Makefile.mk

@@ -0,0 +1,15 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+subdirs-y += variants/$(VARIANT_DIR)
+
+bootblock-y += bootblock.c
+
+verstage-$(CONFIG_VBOOT) += vboot.c
+
+romstage-$(CONFIG_VBOOT) += vboot.c
+
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c
+ramstage-y += hda_verb.c
+ramstage-y += mainboard.c
+ramstage-y += smbios.c

src/mainboard/starlabs/byte_adl/acpi/ec.asl

@@ -0,0 +1 @@
+/* SPDX-License-Identifier: GPL-2.0-only */

src/mainboard/starlabs/byte_adl/acpi/mainboard.asl

@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope (\_SB) {
+	#include "sleep.asl"
+}

src/mainboard/starlabs/byte_adl/acpi/sleep.asl

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method (MPTS, 1, NotSerialized)
+{
+	RPTS (Arg0)
+}
+
+Method (MWAK, 1, NotSerialized)
+{
+	RWAK (Arg0)
+}

src/mainboard/starlabs/byte_adl/acpi/superio.asl

@@ -0,0 +1 @@
+/* SPDX-License-Identifier: GPL-2.0-only */

src/mainboard/starlabs/byte_adl/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: Star Labs
+Board name: Byte
+Category: desktop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/starlabs/byte_adl/bootblock.c

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <soc/gpio.h>
+#include <variants.h>
+
+void bootblock_mainboard_init(void)
+{
+	const struct pad_config *pads;
+	size_t num;
+
+	pads = variant_early_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+}

src/mainboard/starlabs/byte_adl/cmos.default

@@ -0,0 +1,15 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# hardcoded
+boot_option=Fallback
+# console
+debug_level=Debug
+# cpu
+vtd=Enable
+power_profile=Balanced
+me_state=Disable
+# Devices
+wireless=Enable
+webcam=Enable
+# EC
+mirror_flag=Disable

src/mainboard/starlabs/byte_adl/cmos.layout

@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# Bank: 1
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# coreboot config options: ramtop
+304	80	h	0	ramtop
+
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	2	boot_option
+388	4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	3	debug_level
+# coreboot config options: cpu
+#400	8	r	0	reserved for century byte
+408	1	e	1	vtd
+416	2	e	5	power_profile
+424	1	e	4	me_state
+432	4	h	0	me_state_counter
+
+# coreboot config options: Devices
+504	1	e	1	wireless
+
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# Bank: 2
+# embedded controller settings (outside the checksummed area)
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID	value	text
+1	0	Disable
+1	1	Enable
+
+2	0	Fallback
+2	1	Normal
+
+3	0	Emergency
+3	1	Alert
+3	2	Critical
+3	3	Error
+3	4	Warning
+3	5	Notice
+3	6	Info
+3	7	Debug
+3	8	Spew
+
+4	0	Enable
+4	1	Disable
+
+5	0	Power Saver
+5	1	Balanced
+5	2	Performance
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984

src/mainboard/starlabs/byte_adl/dsdt.asl

@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20220930
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/alderlake/acpi/southbridge.asl>
+		#include <soc/intel/alderlake/acpi/tcss.asl>
+
+		#include <soc/intel/common/block/acpi/acpi/gna.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	/* Star Labs EC */
+	#include <ec/starlabs/merlin/acpi/ec.asl>
+
+	Scope (\_SB)
+	{
+		/* HID Driver */
+		#include <ec/starlabs/merlin/acpi/hid.asl>
+
+		/* Suspend Methods */
+		#include <ec/starlabs/merlin/acpi/suspend.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}

src/mainboard/starlabs/byte_adl/hda_verb.c

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/azalia_device.h>
+#include <option.h>
+#include <types.h>
+
+#define AZALIA_CODEC_SN6140	0x14f11f87
+
+static const u32 override_verb[] = {
+	AZALIA_PIN_CFG(0, 0x1a, 0x00000000),
+};
+
+static void disable_microphone(u8 *base)
+{
+	azalia_program_verb_table(base, override_verb, ARRAY_SIZE(override_verb));
+}
+
+void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
+{
+	if (viddid == AZALIA_CODEC_SN6140) {
+		printk(BIOS_DEBUG, "CMOS: viddid = %08x\n", viddid);
+		if (get_uint_option("microphone", 1) == 0)
+			disable_microphone(base);
+	}
+}

src/mainboard/starlabs/byte_adl/include/variants.h

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _BASEBOARD_VARIANTS_H_
+#define _BASEBOARD_VARIANTS_H_
+
+#include <soc/gpio.h>
+
+enum cmos_power_profile {
+	PP_POWER_SAVER = 0,
+	PP_BALANCED    = 1,
+	PP_PERFORMANCE = 2,
+};
+#define NUM_POWER_PROFILES 3
+
+enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback);
+
+/*
+ * The next set of functions return the gpio table and fill in the number of
+ * entries for each table.
+ */
+const struct pad_config *variant_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+
+void devtree_update(void);
+
+#endif /* _BASEBOARD_VARIANTS_H_ */

src/mainboard/starlabs/byte_adl/mainboard.c

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <soc/ramstage.h>
+#include <option.h>
+#include <variants.h>
+
+enum cmos_power_profile get_power_profile(enum cmos_power_profile fallback)
+{
+	const unsigned int power_profile = get_uint_option("power_profile", fallback);
+	return power_profile < NUM_POWER_PROFILES ? power_profile : fallback;
+}
+
+static void init_mainboard(void *chip_info)
+{
+	const struct pad_config *pads;
+	size_t num;
+
+	pads = variant_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+
+	devtree_update();
+}
+
+struct chip_operations mainboard_ops = {
+	.init = init_mainboard,
+};

src/mainboard/starlabs/byte_adl/smbios.c

@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <chip.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <ec/starlabs/merlin/ec.h>
+#include <smbios.h>
+#include <types.h>
+#include <uuid.h>
+#include <variants.h>
+
+/* Get the Embedded Controller firmware version */
+void smbios_ec_revision(uint8_t *ec_major_revision, uint8_t *ec_minor_revision)
+{
+	u16 ec_version = ec_get_version();
+
+	*ec_major_revision = ec_version >> 8;
+	*ec_minor_revision = ec_version & 0xff;
+}
+
+const char *smbios_system_sku(void)
+{
+	return CONFIG_MAINBOARD_FAMILY;
+}
+
+u8 smbios_mainboard_feature_flags(void)
+{
+	return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE;
+}
+
+const char *smbios_chassis_version(void)
+{
+	return smbios_mainboard_version();
+}
+
+const char *smbios_chassis_serial_number(void)
+{
+	return smbios_mainboard_serial_number();
+}

src/mainboard/starlabs/byte_adl/variants/mk_ii/Makefile.mk

@@ -0,0 +1,9 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+
+romstage-y += romstage.c
+
+ramstage-y += devtree.c
+ramstage-y += gpio.c
+ramstage-y += hda_verb.c

src/mainboard/starlabs/byte_adl/variants/mk_ii/board.fmd

@@ -0,0 +1,14 @@
+FLASH	0x1000000 {
+	SI_ALL	0x600000 {
+		SI_DESC			0x1000
+		SI_ME			0x411000
+	}
+	SI_BIOS 0xa00000 {
+		EC@0x0			0x20000
+		RW_MRC_CACHE@0x20000	0x10000
+		SMMSTORE@0x30000	0x40000
+		CONSOLE@0x70000		0x20000
+		FMAP@0x90000		0x1000
+		COREBOOT(CBFS)
+	}
+}

src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb

@@ -0,0 +1,219 @@
+chip soc/intel/alderlake
+	# FSP UPDs
+	register "enable_c6dram"		= "true"
+	register "eist_enable"			= "true"
+	register "cnvi_bt_audio_offload"	= "true"
+	register "cnvi_bt_core"			= "true"
+	register "sagv"				= "SaGv_Enabled"
+
+	# Serial I/O
+	register "serial_io_uart_mode" = "{
+		[PchSerialIoIndexUART0]		= PchSerialIoSkipInit,
+	}"
+
+	# Power
+	register "pch_slp_s3_min_assertion_width"	= "2"			# 50ms
+	register "pch_slp_s4_min_assertion_width"	= "3"			# 1s
+	register "pch_slp_sus_min_assertion_width"	= "3"			# 500ms
+	register "pch_slp_a_min_assertion_width"	= "3"			# 2s
+
+	device domain 0 on
+		device ref igpu		on
+			register "ddi_ports_config" = "{
+				[DDI_PORT_A]			= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_B]			= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_1]			= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_2]			= DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+			}"
+		end
+		device ref tcss_xhci	on
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+		device ref gna		on  end
+		device ref xhci		on
+			# Front panel USB Type C
+			register "usb2_ports[0]"		= "USB2_PORT_MID(OC_SKIP)"
+			register "tcss_ports[0]"		= "TCSS_PORT_DEFAULT(OC_SKIP)"
+
+			# Back Top USB Type A [5]
+			register "usb2_ports[1]"		= "USB2_PORT_MID(OC_SKIP)"
+			register "usb3_ports[2]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+
+			# Back Bottom USB Type A [6]
+			register "usb2_ports[2]"		= "USB2_PORT_MID(OC_SKIP)"
+			register "usb3_ports[3]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+
+			# Front Left USB Type A [3]
+			register "usb2_ports[5]"		= "USB2_PORT_MID(OC_SKIP)"
+			register "usb3_ports[1]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+
+			# Front Right USB Type A [2]
+			register "usb2_ports[6]"		= "USB2_PORT_MID(OC_SKIP)"
+			register "usb3_ports[0]"		= "USB3_PORT_DEFAULT(OC_SKIP)"
+
+			# Internal Bluetooth
+			register "usb2_ports[9]"		= "USB2_PORT_MID(OC_SKIP)"
+
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc"		= ""USB Type-C""
+						register "type"		= "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"		= ""Back Top USB Type-A""
+						register "type"		= "UPC_TYPE_USB3_A"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"		= ""Back Top USB Type-C""
+						register "type"		= "UPC_TYPE_USB3_A"
+						device ref usb3_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"		= ""Back Bottom USB Type-A""
+						register "type"		= "UPC_TYPE_USB3_A"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"		= ""Back Bottom USB Type-C""
+						register "type"		= "UPC_TYPE_USB3_A"
+						device ref usb3_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"		= ""Front Left USB Type-A""
+						register "type"		= "UPC_TYPE_USB3_A"
+						device ref usb2_port6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"		= ""Front Left USB Type-C""
+						register "type"		= "UPC_TYPE_USB3_A"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"		= ""Front Right USB Type-A""
+						register "type"		= "UPC_TYPE_USB3_A"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"		= ""Front Right USB Type-C""
+						register "type"		= "UPC_TYPE_USB3_A"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc"		= ""Internal Bluetooth""
+						register "type"		= "UPC_TYPE_INTERNAL"
+						device ref usb2_port10 on end
+					end
+				end
+			end
+		end
+		device ref shared_sram	on  end
+		device ref cnvi_wifi	on  end
+		device ref sata		on
+			register "sata_salp_support"		= "1"
+			register "sata_ports_enable[0]"		= "1"
+			register "sata_ports_dev_slp[0]"	= "1"
+			register "sata_ports_enable[1]"		= "1"
+			register "sata_ports_dev_slp[1]"	= "1"
+		end
+		device ref pcie_rp9	on				# RLT8111 (LAN 1)
+			register "pch_pcie_rp[PCH_RP(9)]" = "{
+				.clk_src			= 2,
+				.clk_req			= 2,
+				.flags				= PCIE_RP_LTR | PCIE_RP_AER,
+
+			}"
+			smbios_slot_desc			"SlotTypePciExpressGen4x1"
+								"SlotLengthShort"
+								"SlotTypePci"
+								"SlotDataBusWidth4X"
+		end
+		device ref pcie_rp10	on				# RLT8125B (LAN 2)
+			register "pch_pcie_rp[PCH_RP(10)]" = "{
+				.clk_src			= 3,
+				.clk_req			= 3,
+				.flags				= PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			smbios_slot_desc			"SlotTypePciExpressGen3X4"
+								"SlotLengthShort"
+								"SlotTypePci"
+								"SlotDataBusWidth4X"
+		end
+		device ref pcie_rp12	on				# SSD x4
+			register "pch_pcie_rp[PCH_RP(12)]" = "{
+				.clk_src			= 0,
+				.clk_req			= 0,
+				.flags				= PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			smbios_slot_desc			"SlotTypePciExpressGen3X4"
+								"SlotLengthLong"
+								"M.2/M 2280"
+								"SlotDataBusWidth4X"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
+				register "reset_gpio"		= "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)"
+				register "srcclk_pin"		= "0"
+				device generic 0 on end
+			end
+		end
+		device ref uart0	on  end
+		device ref pch_espi	on
+			register "gen1_dec"			= "0x00040069"
+			register "gen2_dec"			= "0x00fc0201"
+			register "gen3_dec"			= "0x000c0081"
+
+			chip ec/starlabs/merlin
+				# Port pair 4Eh/4Fh
+				device pnp 4e.00 on  end			# IO Interface
+				device pnp 4e.01 off end			# Com 1
+				device pnp 4e.02 off end			# Com 2
+				device pnp 4e.04 off end			# System Wake-Up
+				device pnp 4e.05 off end			# PS/2 Mouse
+				device pnp 4e.06 off end			# PS/2 Keyboard
+				device pnp 4e.0a off end			# Consumer IR
+				device pnp 4e.0f off end			# Shared Memory/Flash Interface
+				device pnp 4e.10 off end			# RTC-like Timer
+				device pnp 4e.11 off end			# Power Management Channel 1
+				device pnp 4e.12 off end			# Power Management Channel 2
+				device pnp 4e.13 off end			# Serial Peripheral Interface
+				device pnp 4e.14 off end			# Platform EC Interface
+				device pnp 4e.17 off end			# Power Management Channel 3
+				device pnp 4e.18 off end			# Power Management Channel 4
+				device pnp 4e.19 off end			# Power Management Channel 5
+			end
+		end
+		device ref pmc		hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						use usb2_port1 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
+		device ref hda		on
+			subsystemid 0x14f1 0x035e
+			register "pch_hda_sdi_enable[0]"		= "1"
+			register "pch_hda_audio_link_hda_enable"	= "1"
+			register "pch_hda_idisp_codec_enable"		= "1"
+			register "pch_hda_idisp_link_frequency"		= "HDA_LINKFREQ_96MHZ"
+			register "pch_hda_idisp_link_tmode"		= "HDA_TMODE_8T"
+		end
+		device ref smbus	on  end
+	end
+	chip drivers/crb
+		device mmio 0xfed40000 on end
+	end
+end

src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c

@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <chip.h>
+#include <cpu/intel/turbo.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <option.h>
+#include <types.h>
+#include <variants.h>
+
+void devtree_update(void)
+{
+	config_t *cfg = config_of_soc();
+
+	struct soc_intel_common_config *common_config;
+	common_config = chip_get_common_soc_structure();
+
+	struct soc_power_limits_config *soc_conf_4core =
+		&cfg->power_limits_config[ADL_N_041_6W_CORE];
+
+	struct device *nic_dev = pcidev_on_root(0x14, 3);
+
+	/* Update PL1 & PL2 based on CMOS settings */
+	switch (get_power_profile(PP_POWER_SAVER)) {
+	case PP_POWER_SAVER:
+		disable_turbo();
+		soc_conf_4core->tdp_pl1_override	= 6;
+		soc_conf_4core->tdp_pl2_override	= 10;
+		common_config->pch_thermal_trip		= 30;
+		break;
+	case PP_BALANCED:
+		soc_conf_4core->tdp_pl1_override	= 10;
+		soc_conf_4core->tdp_pl2_override	= 25;
+		common_config->pch_thermal_trip		= 25;
+		break;
+	case PP_PERFORMANCE:
+		soc_conf_4core->tdp_pl1_override	= 20;
+		soc_conf_4core->tdp_pl2_override	= 35;
+		common_config->pch_thermal_trip		= 20;
+		break;
+	}
+
+	/* Enable/Disable Bluetooth based on CMOS settings */
+	if (get_uint_option("wireless", 1) == 0) {
+		cfg->usb2_ports[9].enable = 0;
+		nic_dev->enabled = 0;
+	}
+}

src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c

@@ -0,0 +1,459 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <variants.h>
+
+/* Early pad configuration in bootblock */
+const struct pad_config early_gpio_table[] = {
+	/* H10:		UART0 RXD		Debug Connector		*/
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11:		UART0 TXD		Debug Connector		*/
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+/* Pad configuration in ramstage. */
+const struct pad_config gpio_table[] = {
+	/* GPD0:	Battery Low					*/
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+	/* GPD1:	Charger Connected				*/
+	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+	/* GPD2:	LAN Wake					*/
+	PAD_NC(GPD2, NONE),
+	/* GPD3:	Power Button					*/
+	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
+	/* GPD4:	Sleep S3					*/
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+	/* GPD5:	Sleep S4					*/
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+	/* GPD6:	Sleep A						*/
+	PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+	/* GPD7:	Power Adapter Disable				*/
+	PAD_CFG_GPO(GPD7, 0, PWROK),
+	/* GPD8:	Suspend Clock					*/
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+	/* GPD9:	Wireless LAN Sleep				*/
+	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+	/* GPD10:	Sleep S5					*/
+	PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+	/* GPD11:	LAN PHY Enable					*/
+	PAD_NC(GPD11, NONE),
+
+	/* A0:		ESPI IO 0					*/
+	/* A1:		ESPI IO 1					*/
+	/* A2:		ESPI IO 2					*/
+	/* A3:		ESPI IO 3					*/
+	/* A4:		ESPI CS 0					*/
+	/* A5:		Not Connected					*/
+	PAD_NC(GPP_A5, NONE),
+	/* A6:		Not Connected					*/
+	PAD_NC(GPP_A6, NONE),
+	/* A7:		Embedded Controller SCI				*/
+	PAD_NC(GPP_A7, NONE),
+	/* A8:		Not Connected					*/
+	PAD_NC(GPP_A8, NONE),
+	/* A9:		ESPI Clock					*/
+	/* A10:		ESPI Reset					*/
+	/* A11:		Not Connected					*/
+	PAD_NC(GPP_A11, NONE),
+	/* A12:		PCH M.2 SSD PEDET				*/
+	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+	/* A13:		BlueTooth RF Kill				*/
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),
+	/* A14:		Type C VBUS OverCurrent				*/
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+	/* A15:		Test Point 3					*/
+	PAD_NC(GPP_A15, NONE),
+	/* A16:		USB 2 OverCurrent B				*/
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	/* A17:		Not Connected					*/
+	PAD_NC(GPP_A17, NONE),
+	/* A18:		DDI B DP HPD					*/
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+	/* A19:		TCP0 HPD					*/
+	PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1),
+	/* A20:		Test Point 2					*/
+	PAD_NC(GPP_A20, NONE),
+	/* A21:		Fingerprint Reader Interrupt			*/
+	PAD_NC(GPP_A21, NONE),
+	/* A22:		Fingerprint Reader Reset			*/
+	PAD_NC(GPP_A22, NONE),
+	/* A23:		Not Connected					*/
+	PAD_NC(GPP_A23, NONE),
+
+
+	/* B0:		Core Vendor ID 0				*/
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+	/* B1:		Core Vendor ID 1				*/
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+	/* B2:		BC PROCHOT					*/
+	PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT),
+	/* B3:		Not Connected					*/
+	PAD_NC(GPP_B3, NONE),
+	/* B4:		Not Connected					*/
+	PAD_NC(GPP_B4, NONE),
+	/* B5:		I2C 2 SDA		Touch Panel SDA		*/
+	PAD_NC(GPP_B5, NONE),
+	/* B6:		I2C 2 SCL		Touch Panel Clock	*/
+	PAD_NC(GPP_B6, NONE),
+	/* B7:		I2C 3 SDA		Touchpad SDA		*/
+	PAD_NC(GPP_B7, NONE),
+	/* B8:		I2C 3 SCL		Touchpad Clock		*/
+	PAD_NC(GPP_B8, NONE),
+	/* B9:		Not Connected					*/
+	PAD_NC(GPP_B9, NONE),
+	/* B10:		Not Connected					*/
+	PAD_NC(GPP_B10, NONE),
+	/* B11:		I2C PMC PD Interrupt	Test Point 28		*/
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+	/* B12:		PM SLP S0					*/
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* B13:		PLT RST						*/
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* B14:		Top Swap Override	Weak Internal PD 20K
+				High:	Enabled
+				Low:	Disabled			*/
+	PAD_CFG_GPO(GPP_B14, 0, PLTRST),
+	/* B15:		Not Connected					*/
+	PAD_NC(GPP_B15, NONE),
+	/* B16:		Not Connected					*/
+	PAD_NC(GPP_B16, NONE),
+	/* B17:		Not Connected					*/
+	PAD_NC(GPP_B17, NONE),
+	/* B18:		Reboot Support		Weak Internal PD 20K
+				High:	Disabled
+				Low:	Enabled				*/
+	PAD_NC(GPP_B18, NONE),
+	/* B19:		Not Connected					*/
+	PAD_NC(GPP_B19, NONE),
+	/* B20:		Not Connected					*/
+	PAD_NC(GPP_B20, NONE),
+	/* B21:		Not Connected					*/
+	PAD_NC(GPP_B21, NONE),
+	/* B22:		Not Connected					*/
+	PAD_NC(GPP_B22, NONE),
+	/* B23:		Not used	MiPi Camera			*/
+	PAD_NC(GPP_B23, NONE),
+	/* B24:		Not Connected					*/
+	PAD_NC(GPP_B24, NONE),
+	/* B25:		Not Connected					*/
+	PAD_NC(GPP_B25, NONE),
+
+	/* C0:		SMB Clock					*/
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	/* C1:		SMB Data					*/
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+	/* C2:		TLS Confidentiality	Weak Internal PD 20K
+				Low:	Disabled
+				High:	Enabled				*/
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST),
+	/* C3:		SML 0 Clock					*/
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+	/* C4:		SML 0 Data					*/
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+	/* C5:		Boot Strap		Weak Internal PD 20K
+				Low:	ESPI
+				High:	Disabled			*/
+	PAD_CFG_GPO(GPP_C5, 0, DEEP),
+	/* C6:		SML 1 Clock					*/
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
+	/* C7:		SML 1 Data					*/
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
+	/* C8:		Not Connected					*/
+	PAD_NC(GPP_C8, NONE),
+	/* C9:		Not Connected					*/
+	PAD_NC(GPP_C9, NONE),
+	/* C10:		Not Connected					*/
+	PAD_NC(GPP_C10, NONE),
+	/* C11:		Not Connected					*/
+	PAD_NC(GPP_C11, NONE),
+	/* C12:		Not Connected					*/
+	PAD_NC(GPP_C12, NONE),
+	/* C13:		Not Connected					*/
+	PAD_NC(GPP_C13, NONE),
+	/* C14:		Not Connected					*/
+	PAD_NC(GPP_C14, NONE),
+	/* C15:		Not Connected					*/
+	PAD_NC(GPP_C15, NONE),
+	/* C16:		Not Connected					*/
+	PAD_NC(GPP_C16, NONE),
+	/* C17:		Not Connected					*/
+	PAD_NC(GPP_C17, NONE),
+	/* C18:		Not Connected					*/
+	PAD_NC(GPP_C18, NONE),
+	/* C19:		Not Connected					*/
+	PAD_NC(GPP_C19, NONE),
+	/* C20:		Not Connected					*/
+	PAD_NC(GPP_C20, NONE),
+	/* C21:		Not Connected					*/
+	PAD_NC(GPP_C21, NONE),
+	/* C22:		Not Connected					*/
+	PAD_NC(GPP_C22, NONE),
+	/* C23:		Not Connected					*/
+	PAD_NC(GPP_C23, NONE),
+
+	/* D0:		Not used		Audio ID 0		*/
+	PAD_NC(GPP_D0, NONE),
+	/* D1:		Not used		Audio ID 1		*/
+	PAD_NC(GPP_D1, NONE),
+	/* D2:		Not used		Audio ID 2		*/
+	PAD_NC(GPP_D2, NONE),
+	/* D3:		Not Connected					*/
+	PAD_NC(GPP_D3, NONE),
+	/* D4:		Not Connected					*/
+	PAD_NC(GPP_D4, NONE),
+	/* D5:		Clock Request 0		PCH M.2 SSD		*/
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	/* D6:		Clock Request 1		Wireless LAN		*/
+	PAD_NC(GPP_D6, NONE),
+	/* D7:		Clock Request 2		LAN 1			*/
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+	/* D8:		Clock Request 3		LAN 2			*/
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+	/* D9:		GSPI 2 FPS					*/
+	PAD_NC(GPP_D9, NONE),
+	/* D10:		GSPI 2 Clock					*/
+	PAD_NC(GPP_D10, NONE),
+	/* D11:		GSPI 2 MISO FPS					*/
+	PAD_NC(GPP_D11, NONE),
+	/* D12:		GSPI 2 MOSI FPS					*/
+	PAD_NC(GPP_D12, NONE),
+	/* D13:		Wireless LAN Wake				*/
+	PAD_CFG_GPO(GPP_D13, 1, PLTRST),
+	/* D14:		Test Point 10					*/
+	PAD_NC(GPP_D14, NONE),
+	/* D15:		Not Connected					*/
+	PAD_NC(GPP_D15, NONE),
+	/* D16:		PCH M.2 SSD Power Enable			*/
+	PAD_CFG_GPO(GPP_D16, 1, PLTRST),
+	/* D17:		Not Connected					*/
+	PAD_NC(GPP_D17, NONE),
+	/* D18:		Not Connected					*/
+	PAD_NC(GPP_D18, NONE),
+	/* D19:		Test Point 6					*/
+	PAD_NC(GPP_D19, NONE),
+
+	/* E0:		SATA x PCIe					*/
+	PAD_NC(GPP_E0, NONE),
+	/* E1:		Not used		Accelerometer Interrupt	*/
+	PAD_NC(GPP_E1, NONE),
+	/* E2:		Not Connected					*/
+	PAD_NC(GPP_E2, NONE),
+	/* E3:		WiFi RF Kill					*/
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),
+	/* E4:		Test Point 7					*/
+	PAD_NC(GPP_E4, NONE),
+	/* E5:		Not Connected					*/
+	PAD_NC(GPP_E5, NONE),
+	/* E6:		JTAG ODT		No internal PD
+				Low:	Disabled
+				High:	Enabled				*/
+	PAD_CFG_GPO(GPP_E6, 0, DEEP),
+	/* E7:		Embedded Controller SMI				*/
+	PAD_NC(GPP_E7, NONE),
+	/* E8:		DRAM Sleep					*/
+	PAD_NC(GPP_E8, NONE),
+	/* E9:		USB OverCurrent 0				*/
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	/* E10:		Not Connected					*/
+	PAD_NC(GPP_E10, NONE),
+	/* E11:		Not Connected					*/
+	PAD_NC(GPP_E11, NONE),
+	/* E12:		Touchpad Interrupt				*/
+	PAD_NC(GPP_E12, NONE),
+	/* E13:		PWD Amplifier Input				*/
+	PAD_CFG_GPO(GPP_E13, 0, PLTRST),
+	/* E14:		EDP HPD						*/
+	PAD_NC(GPP_E14, NONE),
+	/* E15:		Not Connected		LAN RESET		*/
+	PAD_NC(GPP_E15, NONE),
+	/* E16:		Not Connected					*/
+	PAD_NC(GPP_E16, NONE),
+	/* E17:		Test Point 1					*/
+	PAD_NC(GPP_E17, NONE),
+	/* E18:		Not Connected					*/
+	PAD_NC(GPP_E18, NONE),
+	/* E19:		Thunderbolt LSX RXD				*/
+	PAD_NC(GPP_E19, NONE),
+	/* E20:		Not Connected					*/
+	PAD_NC(GPP_E20, NONE),
+	/* E21:		Not Connected					*/
+	PAD_NC(GPP_E21, NONE),
+	/* E22:		Not Connected					*/
+	PAD_NC(GPP_E22, NONE),
+	/* E23:		Not Connected					*/
+	PAD_NC(GPP_E23, NONE),
+
+	/* F0:		CNV BRI Data					*/
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+	/* F1:		CNV BRI Response				*/
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
+	/* F2:		CNV RGI Data					*/
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
+	/* F3:		CNV RGI Response				*/
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
+	/* F4:		CNV RF Reset					*/
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+	/* F5:		Not used		MODEM_CLKREQ		*/
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
+	/* F6:		CNV PA Blanking					*/
+	PAD_NC(GPP_F6, NONE),
+	/* F7:		TBT LSX VCCIO		Weak Internal PD 20K
+				Low:	1.8V
+				High:	3.3V				*/
+	PAD_CFG_GPO(GPP_F7, 0, DEEP),
+	/* F8:		Not Connected					*/
+	PAD_NC(GPP_F8, NONE),
+	/* F9:								*/
+	PAD_NC(GPP_F9, NONE),
+	/* F10:		Weak Internal PD 20K				*/
+	PAD_CFG_GPO(GPP_F10, 1, PLTRST),
+	/* F11:		Not Connected					*/
+	PAD_NC(GPP_F11, NONE),
+	/* F12:		Not Connected					*/
+	PAD_NC(GPP_F12, NONE),
+	/* F13:		Not Connected					*/
+	PAD_NC(GPP_F13, NONE),
+	/* F14:		Not Connected					*/
+	PAD_NC(GPP_F14, NONE),
+	/* F15:		Not Connected					*/
+	PAD_NC(GPP_F15, NONE),
+	/* F16:		Not Connected					*/
+	PAD_NC(GPP_F16, NONE),
+	/* F17:		Not used		Touch Panel Reset	*/
+	PAD_NC(GPP_F17, NONE),
+	/* F18:		Not used		Touch Panel Interrupt	*/
+	PAD_NC(GPP_F18, NONE),
+	/* F19:		Not Connected					*/
+	PAD_NC(GPP_F19, NONE),
+	/* F20:		CPU M.2 SSD Reset				*/
+	PAD_NC(GPP_F20, NONE),
+	/* F21:		GPPC_F21					*/
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+	/* F22:		Not Connected					*/
+	PAD_NC(GPP_F22, NONE),
+	/* F23:		Not Connected					*/
+	PAD_NC(GPP_F23, NONE),
+
+	/* H0:		PCH M.2 SSD Reset				*/
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST),
+	/* H1:		BFX Strap 2 Bit 3	Weak Internal PD 20K	*/
+	PAD_CFG_GPO(GPP_H1, 1, PLTRST),
+	/* H2:		Wireless LAN Reset				*/
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST),
+	/* H3:		Not Connected					*/
+	PAD_NC(GPP_H3, NONE),
+	/* H4:		I2C 0 SDA		GSensor			*/
+	PAD_NC(GPP_H4, NONE),
+	/* H5:		I2C 0 SDL		GSensor			*/
+	PAD_NC(GPP_H5, NONE),
+	/* H6:		Test Point 4					*/
+	PAD_NC(GPP_H6, NONE),
+	/* H7:		Test Point 5					*/
+	PAD_NC(GPP_H7, NONE),
+	/* H8:		Not Connected					*/
+	PAD_NC(GPP_H8, NONE),
+	/* H9:		Not Connected					*/
+	PAD_NC(GPP_H9, NONE),
+	/* H12:		Not Connected					*/
+	PAD_NC(GPP_H12, NONE),
+	/* H13:		PCH M.2 SSD Device Sleep			*/
+	PAD_CFG_GPO(GPP_H13, 0, PLTRST),
+	/* H14:		Not Connected					*/
+	PAD_NC(GPP_H14, NONE),
+	/* H15:		DDPB Control Clock				*/
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+	/* H16:		Not Connected					*/
+	PAD_NC(GPP_H16, NONE),
+	/* H17:		DDPB Control Data				*/
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* H18:		CPI C10 Gate					*/
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+	/* H19:		Clock Request 4					*/
+	PAD_NC(GPP_H19, NONE),
+	/* H20:		Not Connected					*/
+	PAD_NC(GPP_H20, NONE),
+	/* H21:		Not Connected					*/
+	PAD_NC(GPP_H21, NONE),
+	/* H22:		Not Connected					*/
+	PAD_NC(GPP_H22, NONE),
+	/* H23:		Clock Request 5					*/
+	PAD_NC(GPP_H23, NONE),
+
+	/* S0:		Not Connected					*/
+	PAD_NC(GPP_S0, NONE),
+	/* S1:		Not Connected					*/
+	PAD_NC(GPP_S1, NONE),
+	/* S2:		Not Connected					*/
+	PAD_NC(GPP_S2, NONE),
+	/* S3:		Not Connected					*/
+	PAD_NC(GPP_S3, NONE),
+	/* S4:		Not Connected					*/
+	PAD_NC(GPP_S4, NONE),
+	/* S5:		Not Connected					*/
+	PAD_NC(GPP_S5, NONE),
+	/* S6:		DMIC Clock					*/
+	PAD_NC(GPP_S6, NONE),
+	/* S7:		DMIC Data					*/
+	PAD_NC(GPP_S7, NONE),
+
+	/* T0:		 Not Connected					*/
+	PAD_NC(GPP_T0, NONE),
+	/* T1:		 Not Connected					*/
+	PAD_NC(GPP_T1, NONE),
+	/* T2:		 Not Connected					*/
+	PAD_NC(GPP_T2, NONE),
+	/* T3:		 Not Connected					*/
+	PAD_NC(GPP_T3, NONE),
+	/* T4:		 Not Connected					*/
+	PAD_NC(GPP_T4, NONE),
+	/* T5:		 Not Connected					*/
+	PAD_NC(GPP_T5, NONE),
+	/* T6:		 Not Connected					*/
+	PAD_NC(GPP_T6, NONE),
+	/* T7:		 Not Connected					*/
+	PAD_NC(GPP_T7, NONE),
+	/* T8:		 Not Connected					*/
+	PAD_NC(GPP_T8, NONE),
+	/* T9:		 Not Connected					*/
+	PAD_NC(GPP_T9, NONE),
+	/* T10:		 Not Connected					*/
+	PAD_NC(GPP_T10, NONE),
+	/* T11:		 Not Connected					*/
+	PAD_NC(GPP_T11, NONE),
+	/* T12:		 Not Connected					*/
+	PAD_NC(GPP_T12, NONE),
+	/* T13:		 Not Connected					*/
+	PAD_NC(GPP_T13, NONE),
+	/* T14:		 Not Connected					*/
+	PAD_NC(GPP_T14, NONE),
+	/* T15:		 Not Connected					*/
+	PAD_NC(GPP_T15, NONE),
+
+	/* R0:		HDA BCLK					*/
+	PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1),
+	/* R1:		HDA SYNC					*/
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
+	/* R2:		HDA SDO						*/
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
+	/* R3:		HDA SDI						*/
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
+	/* R4:		HDA Reset					*/
+	PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1),
+	/* R5:		Not Connected					*/
+	PAD_NC(GPP_R5, NONE),
+	/* R6:		Not Connected					*/
+	PAD_NC(GPP_R6, NONE),
+	/* R7:		Not Connected					*/
+	PAD_NC(GPP_R7, NONE),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}

src/mainboard/starlabs/byte_adl/variants/mk_ii/hda_verb.c

@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+#include <stdint.h>
+
+const uint32_t cim_verb_data[] = {
+	/* coreboot specific header */
+	0x14f11f87,	/* Codec Vendor / Device ID: SoundWire SN6140 */
+	0x14f1035e,	/* Subsystem ID */
+	17,		/* Number of jacks (NID entries) */
+
+	/* Reset Codec First */
+	AZALIA_RESET(0x1),
+
+	/* HDA Codec Subsystem ID Verb-table */
+	AZALIA_SUBVENDOR(0, 0x14f1035e),
+
+	/*
+	 * Configuration:
+	 *
+	 * Port A (0x16)	04214040	Headphone
+	 * Port B (0x18)	40F001F0
+	 * Port C (0x1a)	90A72150	DMIC
+	 * Port D (0x19)	04A19020	Headset Microphone
+	 * Port E (0x1d)	0
+	 * Port F (0x1e)	0
+	 * Port G (0x17)	90173160	Speaker
+	 * Port H (0x1f)	0
+	 * Port I (0x21)	40f001f0
+	 * Port M (0x22)	0
+	 */
+
+	0x01c49100,
+	0x000f0000,
+	0x000f0000,
+	0x000f0000,
+
+	0x000f0000,
+	0x01c49000,
+	0x000f0000,
+	0x000f0000,
+
+	0x0017ff00,
+	0x0017ff00,
+	0x000f0000,
+	0x000f0000,
+
+	0x000f0000,
+	0x000f0000,
+	0x000f0000,
+	0x000f0000,
+
+	AZALIA_PIN_CFG(0, 0x01, 0x00000000),
+
+	0x0017205e,	/* SSID */
+	0x00172103,
+	0x001722f1,
+	0x00172314,
+
+	AZALIA_PIN_CFG(0, 0x16, 0x04214040),
+	AZALIA_PIN_CFG(0, 0x18, 0x40f001f0),
+	AZALIA_PIN_CFG(0, 0x1a,	0x90a72150),
+	AZALIA_PIN_CFG(0, 0x19, 0x04a19020),
+	AZALIA_PIN_CFG(0, 0x1d,	0x00000000),
+	AZALIA_PIN_CFG(0, 0x1e, 0x00000000),
+	AZALIA_PIN_CFG(0, 0x17, 0x90173160),
+	AZALIA_PIN_CFG(0, 0x1f,	0x00000000),
+	AZALIA_PIN_CFG(0, 0x21, 0x40f001f0),
+	AZALIA_PIN_CFG(0, 0x22, 0x00000000),
+
+	0x01c31028,	/* Class D Gain */
+	0x01b30420,	/* Set EAPD */
+	0x01c31028,
+	0x01b30420,
+
+	0x80862815,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	10,		/* Number of 4 dword sets */
+
+	AZALIA_SUBVENDOR(2, 0x80860101),
+
+	AZALIA_PIN_CFG(2, 0x04, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x08, 0x18561010),
+	AZALIA_PIN_CFG(2, 0x0a, 0x18561010),
+	AZALIA_PIN_CFG(2, 0x0b, 0x18561010),
+	AZALIA_PIN_CFG(2, 0x0c, 0x18561010),
+	AZALIA_PIN_CFG(2, 0x0d, 0x18561010),
+	AZALIA_PIN_CFG(2, 0x0e, 0x18561010),
+	AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/starlabs/byte_adl/variants/mk_ii/romstage.c

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <option.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+#include <types.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg mem_config = {
+		.type = MEM_TYPE_DDR4,
+	};
+
+	const bool half_populated = true;
+
+	const struct mem_spd ddr4_spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = {
+				.addr_dimm[0] = 0x50,
+			}
+		},
+	};
+
+	memcfg_init(mupd, &mem_config, &ddr4_spd_info, half_populated);
+
+	const uint8_t vtd = get_uint_option("vtd", 1);
+	mupd->FspmConfig.VtdDisable = !vtd;
+};

src/mainboard/starlabs/byte_adl/variants/mk_ii/vboot.fmd

@@ -0,0 +1,24 @@
+FLASH	0x1000000 {
+	SI_ALL					0x600000 {
+		SI_DESC					0x1000
+		SI_ME					0x411000
+	}
+	SI_BIOS 0xa00000 {
+		EC@0x0				0x20000
+		RO_SECTION@0x20000		0x253000 {
+			FMAP@0x0			0x1000
+			COREBOOT(CBFS)@0x1000		0x210000
+			GBB@0x211000			0x40000
+			RO_FRID@0x251000		0x40
+			RO_VPD(PRESERVE)@0x252000	0x1000
+		}
+		MISC_RW@0x273000		0x10000 {
+			RW_MRC_CACHE@0x0		0x10000
+		}
+		SMMSTORE@0x290000		0x40000
+		CONSOLE@0x2d0000		0x20000
+		RW_NVRAM(PRESERVE)@0x2f0000	0x6000
+		RW_VPD(PRESERVE)@0x2f6000	0x2000
+		RW_LEGACY(CBFS)@0x32e000	0x60000
+	}
+}

src/mainboard/starlabs/byte_adl/vboot.c

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <bootmode.h>
+
+int get_recovery_mode_switch(void)
+{
+	return 0;
+}