Provide a weak devtree_update() hook and invoke it early in ramstage
at BS_PRE_DEVICE. Mainboards can override devtree_update() to
enable/disable devices at runtime based on CMOS/NVRAM settings.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic84ddb25e1da050543c230ea457042b8a8a3061f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Introduce platform_handle_emergency_low_battery() to handle the
pre-shutdown sequence when battery levels are critical.
This hook ensures:
1. Visual feedback is provided (Lightbar set to red).
2. The event is logged to ELOG for post-mortem analysis.
3. A delay is enforced to ensure logs are committed and the user
notices the alert before the AP powers off.
BUG=none
BRANCH=none
TEST=Verified lightbar turns red and ELOG is recorded on low battery
boot.
Change-Id: I3f1b2757002d7a2a76dfb51d24a04e2d81b061bb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
For most targets it's known if the CPU supports alternative SMRR
registers or not. Only on model_6fx runtime detection is necessary.
On all platforms this allows the compiler to optimize the code and
thus shrink the code size if alternative SMRR aren't supported.
TEST=On Lenovo X220 the ramstage is 308 bytes smaller.
Change-Id: I3a965d142f79ad587b8cedc9b4646b05e2a45f8b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91014
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Without explicit DDR5 support, print_spd_info() was decoding DDR5 DIMMs
with the DDR4 SPD layout, so banks, ranks, rows, columns, and module
size were all displaying incorrect values.
Add DDR5-specific decoding in spd_bin.c using JESD400-5 byte positions.
Define these offsets in ddr5.h and branch in each getter when
dram_type is DDR5 so printed SPD info matches the actual module.
Fix printk reporting DIMM module size to only report "per channel" when
the DIMM actually contains multiple channels.
TEST=build/boot on out-of-tree board Erying SRMJ4 and Starlabs Starbook
MTL. Verify DIMM info printed in cbmem console is correct.
Change-Id: I7f418db3f89c67c2a71b2c327bb511a78faf7300
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91145
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce FRAMEBUFFER_SPLASH_TEXT to allow rendering status messages
directly into the linear framebuffer. This enables displaying dynamic
information, such as battery levels or system status, during the
bootsplash stage without requiring complex graphics libraries.
Changes:
- Add Kconfig option to toggle framebuffer text support.
- User to call `render_text_to_framebuffer` to display the text message.
- Include render_text.c in ramstage build when
FRAMEBUFFER_SPLASH_TEXT is enabled.
- Create 24x32 font table entry using GoogleSansFlex_24pt-Medium.ttf.
TEST=Able to build google/fatcat.
Change-Id: I6ac25d8d8a9d3d77a9cc2f8c6e0139268b2066b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91092
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Expose calculate_logo_coordinates() by moving its declaration to
bootsplash.h and removing the static qualifier in render_bmp.c.
This allows other parts of the codebase, such as the upcoming text
rendering logic, to reuse the existing logo positioning math to
calculate destination coordinates based on alignment settings.
Change-Id: I8f8b767b093d6bc2befefdc55fe2effa38b95752
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91154
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce the infrastructure required to display an off-mode charging
notification. This is used when a device boots due to power cable
insertion but should remain in a charging state rather than booting
the full operating system.
Changes:
- Add BOOTSPLASH_OFF_MODE_CHARGING to bootsplash_type.
- Define platform_is_off_mode_charging_active() with a weak inline
fallback to allow platforms to signal off-mode charging status.
- Update bmp_logo.c to recognize "off_mode_charging.bmp" and select
it as the active logo type when charging is active.
- Modify render_bmp.c to handle layout and rendering for the charging
logo, including support for footer text if enabled.
- Ensure the rendering flow bails out early after displaying the
charging notification to prevent standard OS boot splash.
BUG=b:473480933
TEST=Able to build google/fatcat.
Change-Id: Ief4c65eaf0178ff3d736363c3e56acfe1adba14a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91106
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current bmp_logo_filename implementation returns static filenames
based on Kconfig or ChromeOS branding levels. This lacks flexibility
for boards that need to select a logo dynamically at runtime (e.g.,
based on SKU ID or hardware straps).
Introduce a weak function mainboard_bmp_logo_filename() that can be
overridden by mainboard code. If the mainboard implementation returns
a non-NULL string, that filename is used; otherwise, the logic falls
back to the existing default behavior.
BUG=None
BRANCH=None
TEST=Verified that a mainboard can override the logo filename by
implementing mainboard_bmp_logo_filename. Verified default behavior
is preserved when no override is present.
Change-Id: Ia410dfb2a7a88779bb8eb4551605747bb326d353
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91082
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Expose the existing i2c block read functionality usually used in
romstage to the smbus_bus_operations for use in ramstage.
This allows faster reading of I2C EEPROM in ramstage.
TEST=Can read I2C EEPROM on Lenovo X220 using I2C block read.
Change-Id: I1264f17317c3095f9661b0ab6aa3124a00ce86c5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91028
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Using this, the compiler is going to check if the printf formatting is
correct for our printk messages.
Since we already have the macro, might as well use it.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I247f24ed64c2be7fc411f5e2fdd38715698bc4e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90829
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The generic Intel SMM S5 entry path disables all GPEs before asserting
SLP_EN, which clears OS-armed wake enables (e.g. LAN_WAKE) and prevents
Wake-on-LAN from S5.
Add a mainboard override hook, mainboard_smi_sleep_finalize(), called
after the S5 teardown but before SLP_EN is asserted, allowing boards to
restore required wake sources.
Change-Id: I9e97308ed94961fc4c08a10714b1b53f198bb593
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Commit ad6e3c847f ("tree: Drop Intel Ice Lake support") removed most
of the Ice Lake PCI IDs, but missed the ones with the ICP prefix
(Ice Point? Ice Lake Point?). Remove all PCI_DID_INTEL_ICP* defines
and references in common block drivers.
Change-Id: I9d33c69d174130aa781a00441fca367e0a67bcb4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90904
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
With the current implementation of assert() for ENV_TEST, the printk()
function must be linked. As we are already using cmocka's mock_assert()
implementation for unit tests, those printk() calls within
assert-related macros should be changed to no-ops.
Also, disable __build_time_assert() for ENV_TEST.
Change-Id: Ia9bea29a32362d68dff89bb7bbf417126ac31fb7
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90870
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`tests/stubs/console.c` also implements printk for our test functions.
Change-Id: Ic6ad8832515b90f4706cb9c5b9d9525a25485992
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
A later patch changes the .config file which we use for our tests.
However that causes the PLATFORM_USES_FSP2_0 option to be enabled, which
in turn causes build errors in our tests, because the function is
obviously not defined in our tests. Create a stub function of sorts like
we do for other coreboot table entries.
It also moves the declaration of the `lb_string_platform_blob_version`
function to coreboot_tables.h, since it doesn't belong in the FSP header
file. Because of that we can also remove the
`if (CONFIG_PLATFORM_USES_FSP2_0)`
check, which makes the code a bit cleaner.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7721dfe4d287b2274a383bb7e5337b85a0f3f148
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
This patch adds Nova Lake specific device IDs to the header files and
driver-specific code.
Note: Device IDs D750h - D75Fh are intentionally omitted and will be
added in a future patch once validation is complete.
Reference:
- Nova Lake External Design Specification (EDS) Volume 1 (#844316)
BUG=none
Change-Id: I00900c4f796b8bcc40f2bc09917172c71039c8a6
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90748
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In our current tree this is always the case. The coreboot code (as far
as I know) doesn't have a hard requirement on that. But if these values
differ then it is usually always a mistake made by the programmer and it
is hard to catch since the value don't really depend on each other.
So until a time in which there comes a platform which needs a flashmap
that doesn't cover the whole flash, this check is introduced.
For that purpose we need to replace the default .config file for tests,
because otherwise the check won't match.
The config file that is used now is based on the fact that we use the
same mainboard for the `.config` as for the `fmap_config.h` in
`tests/include/tests/lib/fmap/fmap_config.h`
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I8bc05a17a2630516ede949660b4fc428f199f3ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90264
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
fwupd checks SMBIOS Type 0 BIOS Characteristics Extension Byte 2 bit 3
(UEFI Specification Supported) when deciding if UEFI capsule updates are
supported.
Set the flag when coreboot is built with the EDK2 payload.
Change-Id: I4d24deeca88cde5411225f8d113704f5a04e8a34
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
On AMD platforms the PSP can boot from different SPI CS lines
and do a recovery boot in case the default CS0 isn't usable.
Allow the SoC to provide the current boot_device CS line by
adding a new weak function.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic9ed54b7979405d433f22458265f09701cda842e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
For all functions which check flags, return a bool type instead of an
int type.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I39f0e2f392ec999f7622ed28c5755dd4d0eecf42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add CPUID definition and CPU table entry for Intel Nova Lake processor
(CPUID 0x300f30). This enables basic CPU initialization and
multiprocessor support for Nova Lake platforms
Reference:
- Nova Lake External Design Specification (EDS) Volume 1 (#844316)
BUG=none
Change-Id: Iea89ebfa8bae3448edfb3b757443ec9902cede5e
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Based on the "TCG ACPI Specification" Version 1.3 published 2021.
Add an enum for the ACPI start methods and use it instead of hardcoding
various numbers in plain code.
Change-Id: I8b66527ee7417e231fe52e0a609b8c100de522b0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89458
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Rename the define for "Secondary PCI Express Extended
Capability" and move it close to the other existing defines.
Cosmetic change. No functionality was changed.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I3b1ce6820f508661d3241c36c90febe0c73b7a5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
It is needed in a later commit that is not upstream yet.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I260dcf199178d28387e7af06c6fb0b03c97c4bb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90692
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some payloads such as depthcharge need to run MIPI panel power-off
commands before booting to the kernel. Otherwise, the abnormal power-off
timing would prevent the pixel charge from being cleared before
power-off, leading to the risk of LCD overpotential hence resulting in
image stickiness or flicker upon restarting.
Therefore, add a 'poweroff' field to the panel_serializable_data struct,
which, in a follow-up patch, will be passed to payloads for running the
power-off commands. Each MIPI panel can define the power-off commands in
that field.
As both init and power-off commands are supported, remove "_init" from
related structs and enums.
BUG=b:474187570
TEST=emerge-jedi coreboot libpayload
BRANCH=skywalker
Change-Id: I1a7c0a14d5c197a0887a26269e4c36e498e8b7ae
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90737
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Move the MIPI panel init command parsing function
mipi_panel_parse_init_commands() and related macros and structs from
drivers/mipi/ to commonlib/mipi/, so that the function can be shared
with payloads.
In a follow-up patch, a 'poweroff' field will be added to the
panel_serializable_data struct and then passed to payloads, so that
payloads can utilize mipi_panel_parse_init_commands() to run the panel
poweroff commands.
BUG=b:474187570
TEST=emerge-jedi coreboot libpayload
BRANCH=skywalker
Change-Id: I19011669f03d060e9f030b673687cbe5965d7e2f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90736
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Rename `fill_lb_framebuffer` to `get_lb_framebuffer` to better
reflect that it returns framebuffer information.
The new `get_lb_framebuffer` returns a constant pointer to the
framebuffer structure instead of filling a provided structure.
This simplifies the API and avoids an unnecessary memory copy.
The file `edid_fill_fb.c` is renamed to `framebuffer_info.c`
to better match the function it now contains.
Call sites in `coreboot_table.c` and `render_bmp.c` are
updated to use the new API.
TEST=emerge-tanjiro coreboot; check the FW logo is correctly drawn.
BUG=b:319511268
Change-Id: I8d7b20a0524b6bc9fff9e6461fa0c253345df790
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90725
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
They are needed in a later patch which is not yet upstream.
source: AMD64 Architecture Programmers Manual Rev 3.42
Change-Id: I4f5bb5533d8f0e1765749d24ef0b22805ad1554a
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90480
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use flexible array member cper_ia32x64_context to simplify the struct
usage.
Change-Id: I729cb914031b55b2b58bc9e459ee0ea15c7626e8
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90479
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The naming of the parameters was quite confusing which caused them to be
used incorrectly. For example the cper_ia32x64_ctx_sz_bytype function
was given the register size in bytes, but it sill multiplied it by 8,
thinking that it got the number of registers instead.
Fix the parameter names to make it more obvious what is the number of
register array entries and what is the actual size in bytes of the
array.
Change-Id: I17a0fadba57ee8ede996eead4cdfb20f1ab3031e
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90477
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The pic_width and pic_height fields of dsc_config are equivalent to
edid.mode.ha and edid.mode.va, respectively. To remove duplicate
information in panel_serializable_data, remove these two fields from
dsc_config.
BUG=b:424782827
TEST=emerge-tanjiro coreboot
BRANCH=none
Change-Id: I7f1dd4b431a610fa928b29da420b0c0e0bef5fcc
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90561
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Separating the bootblock into two copies (in BOOTBLOCK and TOPSWAP fmap
regions) breaks the CBFS verification as TSPI CRTM knows nothing about
the new regions and looks for bootblock in a hard-coded COREBOOT fmap
region.
Introduce and use cbfs_unverified_area_type_alloc() which is an
extension of cbfs_unverified_area_alloc(), very similar to how
cbfs_ro_type_map() is an extension of cbfs_ro_map(). This allows to
specify a region of the bootblock file and skip verification because
bootblock serves as a container of hashes and is not verified itself.
The branching is done on the state of RTC BUC to always use the current
bootblock. Somewhat confusingly, the measurement always uses BOOTBLOCK
region because with active Top Swap that's the way to access a
memory-mapped TOPSWAP region.
Makefile.mk now verifies both COREBOOT and COREBOOT_TS regions.
cbfstool needed a few updates as well:
- recognize both "BOOTBLOCK" and "TOPSWAP" regions
- recognize both "COREBOOT" and "COREBOOT_TS" regions
- reset metadata cache before processing each region as cache may now
be invalid
SMM doesn't link with vboot functions, so cbfs_file_hash_mismatch() has
to skip verification in SMM due to the use of CMOS options backend.
This is a part of the bootblock redundancy feature proposed
on the mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
Tested by successfully booting into Protectli VP6670 with Top Swap and
CBFS Verification features enabled and Top Swap state being toggled.
Change-Id: Ia75e714ae84d8c0ae09b27495e3056313b109999
Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89691
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Define ENV_RAMSTAGE_LOADER in rules.h similar to ENV_PAYLOAD_LOADER
to simplify the current code and avoid code duplication when adding
zstd support.
Change-Id: I8c049c640b11c6f0b51e37dd2c368bb786ca9b0f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90153
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Move the xxhash lib to commonlib/bsd folder so that it can be
easily included by tools. Update use of standard headers to
allow compilation on POSIX compatible systems as well.
Use the new xxhash lib in cbfstool over the existing duplicated
xxhash lib residing in lz4/lib.
Change-Id: I21041409d5b734cecf43294dcaf3bf17531dbc15
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89682
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on AMD doc #48882 PUB Rev 3.10 [1]. Now, the IVHD type 11h and
40h have a second 64bit EFR value that should be filled with IOMMU MMIO
offset 0x1A0 register value if EFR is supported.
[1] https://docs.amd.com/v/u/en-US/48882_IOMMU
Change-Id: I0da79bed8994671c651328cd7a29d9480a122528
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Each error source descriptor basically has these values at the
beginning. The error source descriptors are added in the follow up
patches.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic6873cb8cf7373435be3ce26382aa8ae37cd5938
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The mipi_cmd_func_t callback for mipi_panel_parse_init_commands()
currently doesn't support passing additional data for storing context.
Therefore user code would need to store any extra data in global
variables. For example, in the upcoming DSI dual channel support for
MediaTek platforms, the callback needs to know whether the MIPI panel
supports dual channel or not. To support that use case, pass an extra
`user_data` argument to mipi_cmd_func_t.
BUG=b:424782827
TEST=util/abuild/abuild -x -t GOOGLE_SAPPHIRE -a
BRANCH=none
Change-Id: Id5d7b168cdcadfe8d8435c29d7e855a535815057
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Refactor the stack definition macros to explicitly define separate
memory regions for the stack, addressing resource conflicts on
certain SoCs like Qualcomm x1p42100.
The original STACK macro is split into PRERAM_STACK and
POSTRAM_STACK.
Motivation:
On the Qualcomm x1p42100 SoC, the boot flow presents two
constraints for the initial stack location:
- Boot IMEM is unavailable after the ADSP is loaded.
- The existing SSRAM stack address is reserved for QC QSEE by the
Trust Zone.
Solution:
- PRERAM_STACK: Used by coreboot (e.g., till romstage) for static
stack allocation (from an alternative SSRAM or BOOT IMEM region).
- POSTRAM_STACK: Used starting from ramstage, leveraging the
DRAM-mapped memory.
This conditional split allows coreboot to manage stack memory
independently for the limited environment before DRAM is fully
initialized (ENV_ROMSTAGE_OR_BEFORE), resolving the hardware memory
conflicts while maintaining compatibility with existing code via
aliasing.
BUG=b:456953373
BRANCH=None
TEST=Able to build google/bluey.
Change-Id: I6356adc63d595f59050e6dc5961404be4a9534c0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90402
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
The Armv9-A architecture introduces the Memory Tagging Extension (MTE),
which uses a dedicated memory region for tag storage.
This patch adds a new memory type, BM_MEM_TAG, to allow for the proper
accounting and reservation of this memory region. This ensures that the
payload, e.g. depthcharge, can correctly identify and utilize the tag
storage area.
BUG=b:438666196
Change-Id: I2f6d2b3c2c1a8e1f0e9b2c3d4e5f6a7b8c9d0e1f
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch introduces a new function, bootmem_add_range_from, which
allows adding a memory range of a specific type only if it is carved
out from a range of another specific type. This is useful for cases
where memory needs to be allocated from a pre-defined region.
The function checks if the target range is fully contained within a
range of `from_tag` before marking it as `new_tag`. Error reporting
is included to log cases where the allocation is not possible.
BUG=b:438666196
Change-Id: Icfdb5ef9114572c075be6ef4e57d00151300a17a
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90469
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GCC generates correct code for __builtin_bswapXX() on all architectures,
including ArmV4. It seems that whatever bug caused this to not work back
in commit 879ea7fce8 ("endian: Replace explicit byte swapping with
compiler builtin") has been fixed now. We can eliminate the swabXX()
functions and simplify the code.
All instances that had been calling these functions directly should have
been using real endianness conversions anyway.
Change-Id: I19713fd009aa5c0e01c4a42e0cf012364d6bed60
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90438
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
We've accumulated a number of endianness-handling and related macros
that are duplicated between coreboot and libpayload. This patch reduces
duplication by merging them into a commonlib header. This has the added
side-benefit of bringing the coreboot implementation of beXXenc/dec()
functions to libpayload, which lead to better code generation by
avoiding https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92716.
Keep the htobell()-style functions in libpayload only since they're not
needed in coreboot and not preferred. Keep the cpu_to_beXX()-style
functions in coreboot only -- maybe we should deprecate those
eventually.
This patch is explicitly copying and relicensing some of the code I
originally added as GPLv2 in commit e8e92d60c4 ("endian.h: Add
be32dec/be32enc family of functions") to BSD-3.
Change-Id: I5eb83d44a98b3aa59bba65b8e22df668874d2668
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90308
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The option was introduced by
commit ae738acdc5 ("cpu/x86: Support CPUs without rdmsr/wrmsr")
for the intel quark SOC. However the SOC doesn't exist anymore in
coreboot. Nor does any other SOC use this option.
Therefore remove it.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I4f3f5e91c00784c159042271387c2e862f351881
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90421
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Parse the supported voltages from the DDR3 SPD and populate the
corresponding fields in CBMEM_ID_MEMINFO to make sure the SMBIOS
type 17 tables report the actual supported voltages of the DIMM.
Change-Id: I35af7c23f285af10b607a80eab7f4d9df664b3fd
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
If the Top Swap mechanism is enabled, after running the bootblock from
the TOP_SWAP region, boot from an updatable COREBOOT_TS FMAP region.
Having flashed the TOP_SWAP bootblock and COREBOOT_TS, this allows the
user to boot a newer version of the firmware with the ability to
revert to the previous known-good version by performing a CMOS reset.
Requires having a read-write COREBOOT_TS region in the FMAP file.
This is part of an ongoing implementation of a redundancy feature
proposed on the mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
TEST=Boot Protectli VP6650, setting the attempt_slot_b flag to
different values, observing the "Booting from COREBOOT/COREBOOT_TS
region" prints correspondingly.
Change-Id: Ieadc9bfbe940cbec79eb84f16a5d622bfbb82ede
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
