drivers/spi: Allow SoC to provide the SPI flash CS index
On AMD platforms the PSP can boot from different SPI CS lines and do a recovery boot in case the default CS0 isn't usable. Allow the SoC to provide the current boot_device CS line by adding a new weak function. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ic9ed54b7979405d433f22458265f09701cda842e Reviewed-on: https://review.coreboot.org/c/coreboot/+/90777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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3 changed files with 15 additions and 2 deletions
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@ -8,6 +8,11 @@
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static struct spi_flash sfg;
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static bool sfg_init_done;
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__weak int boot_device_spi_cs(void)
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{
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return 0; /* Default to chip select 0 */
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}
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static ssize_t spi_readat(const struct region_device *rd, void *b,
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size_t offset, size_t size)
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{
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@ -47,7 +52,7 @@ static const struct region_device spi_rw =
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static void boot_device_rw_init(void)
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{
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const int bus = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS;
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const int cs = 0;
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const int cs = boot_device_spi_cs();
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if (sfg_init_done == true)
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return;
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@ -17,6 +17,11 @@
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static struct spi_flash spi_flash_info;
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static bool spi_flash_init_done;
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__weak int boot_device_spi_cs(void)
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{
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return 0; /* Default to chip select 0 */
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}
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/*
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* SPI speed logging for big transfers available with BIOS_DEBUG. The format is:
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*
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@ -82,7 +87,7 @@ static struct mmap_helper_region_device mdev =
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void boot_device_init(void)
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{
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int bus = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS;
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int cs = 0;
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int cs = boot_device_spi_cs();
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if (spi_flash_init_done == true)
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return;
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@ -27,6 +27,9 @@ enum bootdev_prot_type {
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* most likely not to work so don't rely on such semantics.
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*/
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/* Return the chip select index used for probing the SPI flash. */
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int boot_device_spi_cs(void);
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/* Return the region_device for the read-only boot device. This is the root
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device for all CBFS boot devices. */
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const struct region_device *boot_device_ro(void);
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