Update generate_font.py to produce 8-bit alpha maps instead of 1-bit
packed bitmaps. This enables text smoothing (anti-aliasing) during
framebuffer rendering by providing pixel intensity values (0-255).
Key changes:
- Switch PIL image mode from "1" (monochrome) to "L" (8-bit grayscale).
- Change C data type from uint32_t bit-packed rows to uint8_t byte arrays.
- Implement vertical centering logic using font metrics (ascent/descent).
- Add glyph clipping detection and warnings for both width and height.
- Format C output so each source line represents one glyph row.
Change-Id: Iec8a0123456789abcdef0123456789abcdef0123
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91178
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update generate_font.py to support user-defined canvas width and height
via command-line arguments. This replaces the hardcoded 16x24 limits.
Key changes:
- Use argparse for --width and --height parameters.
- Ensure glyphs are left-aligned to the MSB (bit 15 or 31) for
scalability.
TEST=Able to create font table upto 32 pixels wide.
```
python generate_font.py <path_to_ttf> --width 24 --height 32 > font_table.c
```
Change-Id: Ifd02a979abf41a2c2b088ae58bb931f9f6421491
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91165
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add extra_dump (-e) support for NCT6791D and NCT6796D to dump all HWM
banked registers: global, SYSFAN, CPUFAN, AUXFAN0, PECI calibration,
PECI setup, AUXFAN1–3 (+AUXFAN4 for -96D). Uses index port at base+5
and data port at base+6, per datasheets.
TEST=build/dump SIO registers for out-of-tree board Erying SRMJ4 with
NCT6796D.
Change-Id: I689374826bc1e38efaa3d68013610a8fa2052b1f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91098
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Per the NCT6791D datasheet, global configuration register 0x2d is
reserved, so exclude it from the dump like other reserved registers
(0x12, 0x15-0x19, 0x23, etc).
This was discovered when comparing datasheets for the -91D and -96D;
0x2d is a strapped register for the -96D, but reserved for the -91D.
Change-Id: I7d0372c4592f5532480acc5220ee11d9800d2277
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91097
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
cbfstool/flashmap/kv_pair.h uses the `__printf` macro. So we need to
include the header file defining `__printf` in the compilation.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I4ce98f59b94d64ef4e0694e0c83f7b83f6feec7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This adds generate_font.py, a Python utility designed to convert
standard TTF/OTF files into a compact bitmapped format suitable for
firmware framebuffers.
Key features:
- Generates a left-aligned (normalized) bitmapped table to eliminate
dead space in font glyphs.
- Outputs a character width table to support proportional spacing.
- Exports FONT_HEIGHT and FONT_WIDTH macros for C synchronization.
- Limits output to printable ASCII (32-126) to minimize binary bloat.
The tool uses the Pillow (PIL) library to rasterize glyphs and is
intended to be used during the build process to generate C source
files for splash screen text rendering.
Usage:
python util/font/generate_font.py <font.ttf> > font_table.c
Change-Id: Iec8907f1a5f24d61822230f6a22295c8382d2229
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Commit 4a09db75d9 ("util/autoport: Add
support for 9 Series PCHs (Lynx Point Refresh)") got submitted after
commit 01d82febb2 ("util/autoport:
Separate handling of Kconfig selects").
The latter commit was specifically made so that the former commit could
properly express a Kconfig select with a condition. However, the former
commit did not get updated, and got submitted as-is since there was no
unresolved review comment to keep track of this TODO. As a result, what
should have been a conditional Kconfig select but with the condition in
a comment to work around limitations of the original system accidentally
became a bool option override.
So, simply use the new system to express a conditional Kconfig select.
This fixes the wrongly-generated Kconfig as well as the original issue.
Even though this would still have worked, the `USE_BROADWELL_MRC` option
must be selected for boards with a Lynx Point Refresh PCH, since Haswell
MRC will not work on those PCHs. Still, this can be caught and corrected
during review, in case any board ports are made before this fix lands.
Change-Id: I98f032283e9e5bb5ec13dbff382304b7abfec07e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91027
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Handle ADL-P and ADL-M PCI IDs the same as ADL-N and RPL-P for
dumping LPC registers. Add southbridge names/labels for ADL-P
and ADL-M.
TEST=build and run 'inteltool -l' to dump LPC/eSPI registers on
google/taeko (RPL-P), verify output matches LPC decode set in devicetree
Change-Id: I84901a8e25eb679acb31be1caa8fffa667454c62
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91026
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested on a HP ProDesk 400 G7, with an i5-10500 and a Q470 chipset.
Dumping MCH, SPI/BIOS CONTROL, LPC/eSPI, GPIO, EPBAR and DMIBAR work.
Change-Id: I0eca3a72c42b0cb85bcda8502bccbb4a80704b3b
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The current clang version cannot be built using GCC-15 so switch to a
more recent release.
It also adds a new dependency called third party. Its used in various
LLVM components and is needed to build clang.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I0f2ebc214726fd4ae4f7bba50a662dd5cb89a718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89377
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The existing Lynx Point code is known to work with 9 series PCHs, as
evidenced by commit f5105313cf ("mb/asrock/z97_extreme6: Add new
mainboard") and commit 58c7a84097 ("mb/asrock: Add Z97E-ITX/ac
(Haswell/Broadwell)"). Add the missing IDs to autoport's existing Lynx
Point code.
These IDs were taken from the Intel 9 Series Chipset Family Platform
Controller Hub datasheet (document 330550), section 1.4 "Device and
Revision ID Table".
TEST=Autoport output for the ASRock Z87E-ITX remains unchanged
TEST=Autoport generates output for the ASRock Z97E-ITX/ac
Change-Id: I94c0b35245624d1a68ab69332fe9a5c5abfc5310
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90054
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Using this, the compiler is going to check if the printf formatting is
correct for our printk messages.
Since we already have the macro, might as well use it.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I247f24ed64c2be7fc411f5e2fdd38715698bc4e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90829
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Its actually the size FMAP flash region so the name is more appropriate.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I152b66abedb68f1ab809d918502efe096e9dde59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90811
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PSP soft fuse is a 64bit value which does not use address mode
bits. Those address mode bits are also part of the soft fuse value,
thus must not be hardcoded to 0.
Change-Id: I5a3e078800653d15baf1939fdce11a60031b9978
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90789
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add PCI IDs necessary to support Intel Core Ultra 9 285H (Arrow Lake-H
platform). Arrow Lake is a Meteor Lake variant, so handle the same as
Meteor Lake-P. Add a missing PCI ID for MTL-P as well.
TEST=dump GPIOs on Starlabs Starfighter with Core Ultra 125H (MTL) and
285H (ARL) CPUs.
Change-Id: I14b74227ce808a7b4269741b7e2c5f23326bced4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Replace hardcoded values of address mode with its corresponding
enum value to increase code readability.
Change-Id: Ib2d97f36aa19235a312558e397f97e2607476e61
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90391
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Test if shellball extraction fails, and if it does, show the output of
the command and then exit, as nothing more can be done.
Change-Id: I0cd7416c988d11e019bfd0b4cd52af8811e6d1e2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Many newer ChromeOS recovery shellballs require 7z to decompress, so
add it as a dependency.
Change-Id: Ibe0391567736a39c31914c573b154d8ed7de617b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Refactor exit_if_dependencies_are_missing() to check all dependencies
in a single pass using an associative array, collect any missing ones,
and report them all together before exiting. This provides better UX
by showing all missing dependencies at once rather than exiting after
the first one.
This replaces the previous approach that would exit immediately upon
finding the first missing dependency, often causing users to run the
script several times to identify and install all missing dependencies.
Change-Id: Ieb03756b24fd2aa1af2c0ffaed717d06c9e85cbb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Using generics (introduced in go 1.18) we can avoid repeating the same
code multiple times by encapsulating it into a generic function.
Change-Id: I5dc6696f8802d3fe57290121e22b2c27c545d3ef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Previously, `KconfigBool` was used to generate selects (if the option
value is true) or bool option overrides (if the option value is false).
This approach is not particularly flexible: one cannot have conditions
for selects, and bool option overrides can only disable options.
Introduce a new `KconfigStatement` map of Kconfig names to conditions.
An empty condition string means that no condition is to be added. Also
update uses of `KconfigBool` to `KconfigSelect` to preserve autoport's
current behaviour.
TEST=Generated files for HP ProBook 4740s (Sandy Bridge) do not change.
Change-Id: I88666ce0d761c1d393ac602196229ec0878fed42
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
I use this to dump SIO config on an HP Z210 CMT workstation.
It's a shotgun blast into the dark, although based on what was
done for Z220, already in tree.
Change-Id: I83184f29c11c92384f6a09b671ed9e24956e9e57
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82627
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It updates the target variable that is used for `clang -target`.
Simply because the format was wrong. According to the documentation the
format of the so called "target triple" is:
<arch><sub>-<vendor>-<sys>-<env>
with:
arch = x86_64, i386, arm, thumb, mips, etc.
sub = for ex. on ARM: v5, v6m, v7a, v7m, etc.
vendor = pc, apple, nvidia, ibm, etc. (can be omitted)
sys = none, linux, win32, darwin, cuda, etc.
env = eabi, gnu, android, macho, elf, etc.
In case of powerpc that causes an issue when trying to update clang to
version 21. The target parameter for clang ends up being
"powerpc64-none-unknown-linux-gnu". After testing, it turns out that in
clang version 18 that is actually a valid target parameter, although not
according to the documentation. In clang 21 however its not valid so fix
it accordingly.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I958416e6c56459766794830fbeac57ac827ffdd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
GCC's configure script requires gnat1, gnatbind, and gnatmake to be
available as unversioned executables in PATH when building with Ada
support. The previous detection logic only checked for gnat1 and used
a lenient searchtool check for gnatbind, which could incorrectly
enable Ada support when gnatmake was missing, causing configure to
fail with "GNAT is required to build ada".
In GNAT 15+, tools may only be available as versioned executables
(e.g., gnatbind-15, gnatmake-15), but GCC configure still requires
unversioned names. This change:
1. Adds explicit checks for gnatbind and gnatmake (unversioned)
2. Updates have_gnat() to require all three tools
3. Detects GNAT 15+ versioned tools and provides helpful error
messages with instructions to create symlinks
4. Falls back to generic installation instructions if no GNAT tools
are found
This prevents the configure error and provides clear guidance for
users with GNAT 15+ installations.
Change-Id: Idc16ec48612e88fc9bdd16b343ae267aa20490f3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
AMD_FW_GFXIMU_2 entry has the same type value as AMD_FW_SRAM_FW_EXT.
The tool may integrate one of these blobs incorrectly, because
it searches for the first entry of given type in the amd_psp_fw_table.
AMD_FW_GFXIMU_2 could have been added by mistake, because there is no
board that actually defines PSP_GFX_IMMU_FILE_2 in fw.cfg file.
Change-Id: I7e1f38c77156d06e9e6d801bdfa9b9eefcbb374e
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90388
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The AMD_TA_IKEK occurrs twice in the amd_psp_fw_table, but the tool
will only add it once anyways, so remove redundant entry.
Change-Id: I7fd13552edf98d7adc749726c8bba46124aed495
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
The RISC-V relocations are not correct. Resolved by referring to
binutils-gdb/blob/master/include/elf/riscv.h
Change-Id: I38306f511c96be75192e222e86526a87714126ea
Signed-off-by: Xiang W <wangxiang@iscas.ac.cn>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90600
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Checkpatch emits the following warning about autoport-generated code:
WARNING: space prohibited between function name and open parenthesis '('
So, simply get rid of that space.
Change-Id: If52e3d56c6b254efb61c70c8e482014dd4208172
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Separating the bootblock into two copies (in BOOTBLOCK and TOPSWAP fmap
regions) breaks the CBFS verification as TSPI CRTM knows nothing about
the new regions and looks for bootblock in a hard-coded COREBOOT fmap
region.
Introduce and use cbfs_unverified_area_type_alloc() which is an
extension of cbfs_unverified_area_alloc(), very similar to how
cbfs_ro_type_map() is an extension of cbfs_ro_map(). This allows to
specify a region of the bootblock file and skip verification because
bootblock serves as a container of hashes and is not verified itself.
The branching is done on the state of RTC BUC to always use the current
bootblock. Somewhat confusingly, the measurement always uses BOOTBLOCK
region because with active Top Swap that's the way to access a
memory-mapped TOPSWAP region.
Makefile.mk now verifies both COREBOOT and COREBOOT_TS regions.
cbfstool needed a few updates as well:
- recognize both "BOOTBLOCK" and "TOPSWAP" regions
- recognize both "COREBOOT" and "COREBOOT_TS" regions
- reset metadata cache before processing each region as cache may now
be invalid
SMM doesn't link with vboot functions, so cbfs_file_hash_mismatch() has
to skip verification in SMM due to the use of CMOS options backend.
This is a part of the bootblock redundancy feature proposed
on the mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
Tested by successfully booting into Protectli VP6670 with Top Swap and
CBFS Verification features enabled and Top Swap state being toggled.
Change-Id: Ia75e714ae84d8c0ae09b27495e3056313b109999
Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89691
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds zstd support to cbfstool. The code is taken from zstd-1.5.7
with modifications:
- renaming bits.h to zstd_bits.h to avoid conflicts with coreboot's
bits.h used on riscv
- renaming compiler.h to zstd_compiler.h to avoid conflicts with
coreboot's compiler.h
- Dropped all streaming API functions
- Dropped multithreaded support, since it's now unused
- Dropped local DDict support
zstd offers similar compression ratios to LZMA, but a vastly fast
decompress speed. Typically zstd results in slightly larger binaries
than LZMA. Whether zstd should then be preferred over LZMA depends on
a few things:
- Caching: When loading from memory mapped boot devices, zstd will read
the boot medium multiple times, while LZMA will not. If the memory
mapped boot medium is not cached zstd results in much slower
decompression.
- Boot medium speed: Often, but not always LZMA results in smaller
binaries. If the boot medium is the bottleneck, than loading smaller
binaries might actually be faster. On a fast boot medium (high spi
freq, using quad/dual io), the performance benefits from zstd might be
more substantial
- zstd decompression code has a much larger footprint than LZMA. If the
stage (postcar) is loaded in uncached memory the size increase might
slow things down.
On QEMU Q35 postcar .text section size doubled, while heap section
has growen by 50%.
- zstd uses a lot of .bss (CTX is about 32KiB large). This might not be
available in some environments.
Orignal commit from 2022 was using zstd-1.5.2. Updated to zstd-1.5.7.
Change-Id: I34508268f8767008ef25cb9e466d201345881232
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69753
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the xxhash lib to commonlib/bsd folder so that it can be
easily included by tools. Update use of standard headers to
allow compilation on POSIX compatible systems as well.
Use the new xxhash lib in cbfstool over the existing duplicated
xxhash lib residing in lz4/lib.
Change-Id: I21041409d5b734cecf43294dcaf3bf17531dbc15
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89682
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The script was failing when origin/main doesn't exist. Instead of
trying to detect or use a main branch, simply save the current HEAD
hash and restore it when done. This works regardless of branch names
or remote configuration.
Also improve the clean check to use git diff-files instead of
comparing to a specific branch.
Change-Id: I237de4b1e8a06fd4e1e3ef08286208c130e7a6bd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90502
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is the MCH Strap Length, and FMSBA is the corresponding
Flash MCH Strap Base Address. See ICH8 datasheet, FLMAP2.
Change-Id: I322c13d9228800a2736b0288377495287521712c
Signed-off-by: Daniel Maslowski <info@orangecms.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89614
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As of commit 31fc5b06a6 ("device: Introduce reworked azalia verb
table"), all boards using the old azalia verb table format must select
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE. The generated output of autoport
uses the old format, so select the config.
This is only meant to be a temporary measure as opposed to reworking
autoport to produce the new format, as I would rather incorporate
hda-decoder's functionality to generate hda-verb.c instead of
duplicating efforts. Support for the new format in hda-decoder is
currently WIP on CB:84357.
Change-Id: I54c6a92a69039eb747ee8cc6d5186dc3a3c6acc8
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90055
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add register tables and device IDs for Phoenix AM5 desktop CPUs.
TEST=Dump all data with amdtool on MSI PRO B650M-A.
Change-Id: Ia7af9194fb7516e98b7cddee2bfc65af12d56dc0
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90009
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add an utility similar to inteltool, which dumps useful information
for porting a board to coreboot.
TEST=Use amdtool on Gigabyte MZ33-AR1 with vendor BIOS and coreboot.
Change-Id: I34405897d0f5670038e7923f3680a28090d92821
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Allows ifittool to add FIT entries for files that are located in a
different FMAP region than the FIT table.
The region from where to source the file can be specified with -R.
If not given it defaults to using the value of the mandatory -r,
for full backwards compatibility.
Example: Tested with a custom binary with the bootblock and
corresponding FIT table in a separate region, and the microcode still
in the COREBOOT region:
λ ./ifittool -f test_ts.rom -a -n cpu_microcode_blob.bin -t 1 \
-r BOOTBLOCK \
-R COREBOOT \
-s 4
Change-Id: I7e49247f280ec118e09cf173795d7602a4c0d7f6
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89608
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
LZMA checks at util/cbfstool/lzma/lzma.c:Write() for the output
buffer/stream size and does not write beyond it.
LZ4 checks at src/commonlib/bsd/lz4.c.inc:LZ4_decompress_generic() for
the buffer/stream size and does not write beyond it.
Change-Id: I41298b509b3f5e775bb4000c82c539eefa80c885
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
It was accidently added and is just dead code.
It doesn't change any functionality.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I868b8c8725fc2240543fb1e9e379ecb5e1471ef4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89898
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Switch to using `objdump -f`, which consistently prints the line
"file format <format>" across modern binutils versions, and extract
the architecture format from that output. This restores correct
toolchain detection on Ubuntu 25.10 and other systems with binutils
≥ 2.43, without breakng older versions.
Before:
DEBUG: obj_type:
/tmp/temp.rrDQ8i.o: file format elf64-x86-64
DEBUG: obj_arch:
After:
DEBUG: obj_type:
/tmp/temp.8GsK08.o: file format elf64-x86-64
architecture: i386:x86-64, flags 0x00000000:
start address 0x0000000000000000
DEBUG: obj_arch: elf64-x86-64
Change-Id: Ic09304f9e81580bbe1c0bb4910c0cc534d3d2816
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89643
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
A .gitkeep file is an unofficial convention used in Git to keep and
track empty directories, as Git does not track empty folders by default.
This could be needed when one mainboard variant has an include directory
but another doesn't. If the directory is added to the include, it could
be easier to just create an empty include directory with a .gitkeep file
in it to keep things from failing.
Change-Id: I34b2ffa4d748d82e26867ecd5b9149301300e6a1
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
The amdfw.rom will be divided into 3 parts:
PSP Level 1, PSP Level 2A, PSP Level 2B.
The two ISHs are close to L1 and can be combined as a CBFS module.
To do that, move the new_psp_dir for L1 and L2 to separated branches.
The final sequence is EFS, PSP L1, ISH A, ISH B, PSP L2A, BIOS L2A,
PSP L2B, BIOS L2B.
TEST=Google/Skyrim
Change-Id: Id69268619893d78d9b5330052a4fd5b501263f75
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
coreboot does not use the nds32le-elf toolchain at all, but it causes
build issues in the CI. So drop it from the default builds. It can
still be built by using buildgcc.
Change-Id: I5e5e5b6914265d6aff14c011062db268db4acf6b
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89317
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
