util/amdtool: Add support for Phoenix AM5 CPUs
Add register tables and device IDs for Phoenix AM5 desktop CPUs. TEST=Dump all data with amdtool on MSI PRO B650M-A. Change-Id: Ia7af9194fb7516e98b7cddee2bfc65af12d56dc0 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90009 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michał Żygowski
Matt DeVillier
parent
8f3626c4b5
commit
7436c59875
9 changed files with 311 additions and 63 deletions
|
|
@ -34,7 +34,15 @@ static const struct {
|
|||
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_5, "Turin Data Fabric 5" },
|
||||
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_6, "Turin Data Fabric 6" },
|
||||
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_7, "Turin Data Fabric 7" },
|
||||
|
||||
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_PHX_ROOT_COMPLEX, "Phoenix Root Complex" },
|
||||
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_0, "Phoenix Data Fabric 0" },
|
||||
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_1, "Phoenix Data Fabric 1" },
|
||||
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_2, "Phoenix Data Fabric 2" },
|
||||
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_3, "Phoenix Data Fabric 3" },
|
||||
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_4, "Phoenix Data Fabric 4" },
|
||||
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_5, "Phoenix Data Fabric 5" },
|
||||
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_6, "Phoenix Data Fabric 6" },
|
||||
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_7, "Phoenix Data Fabric 7" },
|
||||
/* FCHs (Southbridges) */
|
||||
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_SMB_1, "FCH SMBus Controller" },
|
||||
{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FCH_LPC_1, "FCH LPC Bridge" },
|
||||
|
|
@ -351,7 +359,7 @@ int main(int argc, char *argv[])
|
|||
if (dump_lpc) {
|
||||
print_lpc(sb);
|
||||
printf("\n\n");
|
||||
print_espi(sb);
|
||||
print_espi(sb, nb);
|
||||
printf("\n\n");
|
||||
}
|
||||
|
||||
|
|
@ -371,20 +379,20 @@ int main(int argc, char *argv[])
|
|||
}
|
||||
|
||||
if (dump_gpios) {
|
||||
print_gpios(sb, 1, show_gpio_diffs);
|
||||
print_gpios(sb, nb, 1, show_gpio_diffs);
|
||||
printf("\n\n");
|
||||
} else if (show_gpio_diffs) {
|
||||
print_gpios(sb, 0, show_gpio_diffs);
|
||||
print_gpios(sb, nb, 0, show_gpio_diffs);
|
||||
printf("\n\n");
|
||||
}
|
||||
|
||||
if (dump_spi) {
|
||||
print_spi(sb);
|
||||
print_spi(sb, nb);
|
||||
printf("\n\n");
|
||||
}
|
||||
|
||||
if (dump_irq) {
|
||||
print_irq_routing(sb);
|
||||
print_irq_routing(sb, nb);
|
||||
printf("\n\n");
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -87,7 +87,21 @@ static inline void outl(uint32_t value, uint16_t port)
|
|||
#define PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_6 0x12c6
|
||||
#define PCI_DEVICE_ID_AMD_BRH_DATA_FABRIC_7 0x12c7
|
||||
|
||||
#define PCI_DEVICE_ID_AMD_PHX_ROOT_COMPLEX 0x14e8
|
||||
#define PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_0 0x14f0
|
||||
#define PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_1 0x14f1
|
||||
#define PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_2 0x14f2
|
||||
#define PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_3 0x14f3
|
||||
#define PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_4 0x14f4
|
||||
#define PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_5 0x14f5
|
||||
#define PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_6 0x14f6
|
||||
#define PCI_DEVICE_ID_AMD_PHX_DATA_FABRIC_7 0x14f7
|
||||
|
||||
#define CPUID_TURIN_C1 0x00b00f21
|
||||
#define CPUID_PHOENIX_A1 0x00a70f41
|
||||
#define CPUID_PHOENIX_A2 0x00a70f52
|
||||
#define CPUID_PHOENIX2_A0 0x00a70f80
|
||||
#define CPUID_HAWKPOINT2_A0 0x00a70fc0
|
||||
|
||||
#if !defined(__DARWIN__) && !defined(__FreeBSD__)
|
||||
typedef struct { uint32_t hi, lo; } msr_t;
|
||||
|
|
@ -117,11 +131,11 @@ uint32_t cpuid(uint32_t eax);
|
|||
int print_amd_msrs(void);
|
||||
int print_cpu_info(void);
|
||||
int print_lpc(struct pci_dev *sb);
|
||||
int print_espi(struct pci_dev *sb);
|
||||
int print_gpios(struct pci_dev *sb, int show_all, int show_diffs);
|
||||
int print_spi(struct pci_dev *sb);
|
||||
int print_espi(struct pci_dev *sb, struct pci_dev *nb);
|
||||
int print_gpios(struct pci_dev *sb, struct pci_dev *nb, int show_all, int show_diffs);
|
||||
int print_spi(struct pci_dev *sb, struct pci_dev *nb);
|
||||
int print_acpimmio(struct pci_dev *sb);
|
||||
void print_psb(struct pci_dev *nb);
|
||||
int print_irq_routing(struct pci_dev *sb);
|
||||
int print_irq_routing(struct pci_dev *sb, struct pci_dev *nb);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -518,6 +518,7 @@ int print_amd_msrs(void)
|
|||
|
||||
cpu_t cpulist[] = {
|
||||
{ CPUID_TURIN_C1, common_msrs, ARRAY_SIZE(common_msrs) },
|
||||
{ CPUID_PHOENIX_A2, common_msrs, ARRAY_SIZE(common_msrs) },
|
||||
};
|
||||
|
||||
cpu_t *cpu = NULL;
|
||||
|
|
|
|||
|
|
@ -17,10 +17,10 @@
|
|||
#define ESPI1_MMIO_BASE 0xfec30000
|
||||
#define ESPI_MMIO_SIZE 0x10000
|
||||
|
||||
#define BRH_ESPI0_SMN_BASE 0x02DC5000
|
||||
#define BRH_ESPI1_SMN_BASE 0x02DCA000
|
||||
#define ESPI0_SMN_BASE 0x02DC5000
|
||||
#define ESPI1_SMN_BASE 0x02DCA000
|
||||
|
||||
static const io_register_t kunlun_espi_cfg_registers[] = {
|
||||
static const io_register_t espi_cfg_registers[] = {
|
||||
{0x2C, 4, "MASTER_CAP"},
|
||||
{0x30, 4, "GLBL_CTL0"},
|
||||
{0x34, 4, "GLBL_CTL1"},
|
||||
|
|
@ -105,12 +105,13 @@ static uint32_t espi_read8(const io_register_t *reg, size_t espi_cntrlr)
|
|||
return read8(espibar + (espi_cntrlr * ESPI_MMIO_SIZE) + reg->addr);
|
||||
}
|
||||
|
||||
int print_espi(struct pci_dev *sb)
|
||||
int print_espi(struct pci_dev *sb, struct pci_dev *nb)
|
||||
{
|
||||
size_t i, espi, num_espi, cfg_registers_size = 0;
|
||||
size_t i, espi, cfg_registers_size = 0;
|
||||
uint32_t spibar_phys, spibar_mask;
|
||||
const io_register_t *cfg_registers;
|
||||
int smbus_rev = 0;
|
||||
size_t num_espi = 1;
|
||||
|
||||
printf("\n========== eSPI ==========\n\n");
|
||||
|
||||
|
|
@ -122,11 +123,13 @@ int print_espi(struct pci_dev *sb)
|
|||
|
||||
switch (smbus_rev) {
|
||||
case 0x71:
|
||||
num_espi = 2;
|
||||
cfg_registers = kunlun_espi_cfg_registers;
|
||||
cfg_registers_size = ARRAY_SIZE(kunlun_espi_cfg_registers);
|
||||
espi_smn_addr[0] = BRH_ESPI0_SMN_BASE;
|
||||
espi_smn_addr[1] = BRH_ESPI1_SMN_BASE;
|
||||
if (nb->device_id == PCI_DEVICE_ID_AMD_BRH_ROOT_COMPLEX)
|
||||
num_espi = 2;
|
||||
|
||||
cfg_registers = espi_cfg_registers;
|
||||
cfg_registers_size = ARRAY_SIZE(espi_cfg_registers);
|
||||
espi_smn_addr[0] = ESPI0_SMN_BASE;
|
||||
espi_smn_addr[1] = ESPI1_SMN_BASE;
|
||||
spibar_mask = 0xffffff00;
|
||||
break;
|
||||
default:
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
#define AMD_IOMUX_SIZE 0x100
|
||||
#define AMD_GPIO_BANK_SIZE (0x100 / 4)
|
||||
|
||||
#define AMD_BRH_IOMUX_SMN_BASE 0x02D01000
|
||||
#define AMD_FCH_ACPIMMIO_SMN_BASE 0x02D01000
|
||||
|
||||
static uint8_t *iomux_base;
|
||||
static uint32_t *gpio_base;
|
||||
|
|
@ -105,6 +105,90 @@ const char *const kunlun_iomux_gpio_names[] = {
|
|||
[0x98 * 4] = "I3C3_SDA", "I2C3_SDA", "GPIO152", "GPIO152",
|
||||
};
|
||||
|
||||
const char *const tacoma_iomux_gpio_names[] = {
|
||||
[0 ... AMD_IOMUX_MAX_FUNC_COUNT * AMD_IOMUX_SIZE - 1] = "",
|
||||
[ 0 * 4] = "PWR_BTN_L", "GPIO0", "GPIO0", "GPIO0",
|
||||
[ 1 * 4] = "SYS_RESET_L", "GPIO1", "GPIO1", "GPIO1",
|
||||
[ 2 * 4] = "WAKE_L", "GPIO2", "GPIO2", "GPIO2",
|
||||
[ 3 * 4] = "GPIO3", "GPIO3", "GPIO3", "GPIO3",
|
||||
[ 4 * 4] = "GPIO4", "GPIO4", "GPIO4", "GPIO4",
|
||||
[ 5 * 4] = "GPIO5", "GPIO5", "GPIO5", "GPIO5",
|
||||
[ 6 * 4] = "GPIO6", "GPIO6", "GPIO6", "GPIO6",
|
||||
[ 7 * 4] = "GPIO7", "GPIO7", "GPIO7", "GPIO7",
|
||||
[ 8 * 4] = "GPIO8", "TMU_CLK_OUT0", "TMU_CLK_OUT1", "GPIO8",
|
||||
[ 9 * 4] = "GPIO9", "GPIO9", "GPIO9", "GPIO9",
|
||||
[ 10 * 4] = "GPIO10", "S0A3_GPIO", "GPIO10", "DF_VRCONTEXT_0",
|
||||
[ 11 * 4] = "GPIO11", "BLINK", "GPIO11", "GPIO11",
|
||||
[ 12 * 4] = "LLB_L", "GPIO12", "GPIO12", "GPIO12",
|
||||
[ 16 * 4] = "USB_OC0_L", "GPIO16", "GPIO16", "GPIO16",
|
||||
[ 17 * 4] = "USB_OC1_L", "GPIO17", "GPIO17", "GPIO17",
|
||||
[ 18 * 4] = "USB_OC2_L", "GPIO18", "GPIO18", "GPIO18",
|
||||
[ 19 * 4] = "SMBUS1_SCL", "I2C3_SCL", "I3C3_SCL", "GPIO19",
|
||||
[ 20 * 4] = "SMBUS1_SDA", "I2C3_SDA", "I3C3_SDA", "GPIO20",
|
||||
[ 21 * 4] = "ESPI_RESET_L", "KBRST_L", "GPIO21", "GPIO21",
|
||||
[ 22 * 4] = "ESPI_ALERT_D1", "GPIO22", "GPIO22", "SD0_CMD",
|
||||
[ 23 * 4] = "AC_PRES", "GPIO23", "GPIO23", "GPIO23",
|
||||
[ 24 * 4] = "USB_OC3_L", "GPIO24", "GPIO24", "GPIO24",
|
||||
[ 26 * 4] = "PCIE_RST0_L", "GPIO26", "GPIO26", "GPIO26",
|
||||
[ 29 * 4] = "SPI_TPM_CS_L", "GPIO29", "GPIO29", "GPIO29",
|
||||
[ 30 * 4] = "SPI_CS2_L", "ESPI_CS_L", "GPIO30", "GPIO30",
|
||||
[ 31 * 4] = "SPI_CS3_L", "GPIO31", "GPIO31", "GPIO31",
|
||||
[ 32 * 4] = "GPIO32", "LPC_RST_L", "GPIO32", "GPIO32",
|
||||
[ 38 * 4] = "CLK_REQ5_L", "GPIO38", "GPIO38", "GPIO38",
|
||||
[ 39 * 4] = "CLK_REQ6_L", "GPIO39", "GPIO39", "GPIO39",
|
||||
[ 40 * 4] = "GPIO40", "GPIO40", "GPIO40", "GPIO40",
|
||||
[ 42 * 4] = "GPIO42", "DF_VRCONTEXT_1", "GPIO42", "GPIO42",
|
||||
[ 67 * 4] = "SPI_ROM_REQ", "GPIO67", "GPIO67", "GPIO67",
|
||||
[ 68 * 4] = "SPI1_DAT2", "GPIO68", "GPIO68", "SD0_DATA3",
|
||||
[ 69 * 4] = "SPI1_DAT3", "GPIO69", "SD0_CLK", "GPIO69",
|
||||
[ 70 * 4] = "SPI2_CLK", "GPIO70", "GPIO70", "GPIO70",
|
||||
[ 74 * 4] = "SPI1_CS1_L", "GPIO74", "GFX10_CAC_IPIO0", "GPIO74",
|
||||
[ 75 * 4] = "SPI2_CS1_L", "GPIO75", "GPIO75", "GPIO75",
|
||||
[ 76 * 4] = "SPI_ROM_GNT", "GPIO76", "GPIO76", "GPIO76",
|
||||
[ 77 * 4] = "SPI1_CLK", "GPIO77", "GPIO77", "SD0_DATA0",
|
||||
[ 78 * 4] = "SPI1_CS2_L", "GPIO78", "GFX10_CAC_IPIO1", "GPIO78",
|
||||
[ 79 * 4] = "SPI1_CS3_L", "GPIO79", "GPIO79", "GPIO79",
|
||||
[ 80 * 4] = "SPI1_DAT1", "GPIO80", "GPIO80", "SD0_DATA2",
|
||||
[ 81 * 4] = "SPI1_DAT0", "GPIO81", "GPIO81", "GPIO81",
|
||||
[ 84 * 4] = "FANIN0", "GPIO84", "GPIO84", "GPIO84",
|
||||
[ 85 * 4] = "FANOUT0", "GPIO85", "GPIO85", "GPIO85",
|
||||
[ 86 * 4] = "GPIO86", "GPIO86", "GPIO86", "GPIO86",
|
||||
[ 89 * 4] = "GENINT1_L", "PSP_INTR0", "GPIO89", "GPIO89",
|
||||
[ 90 * 4] = "GENINT2_L", "PSP_INTR1", "GPIO90", "GPIO90",
|
||||
[ 91 * 4] = "SPKR", "GPIO91", "GPIO91", "GPIO91",
|
||||
[ 92 * 4] = "CLK_REQ0_L", "GPIO92", "GPIO92", "GPIO92",
|
||||
[104 * 4] = "SPI2_DAT0", "GPIO104", "GPIO104", "GPIO104",
|
||||
[105 * 4] = "SPI2_DAT1", "GPIO105", "GPIO105", "GPIO105",
|
||||
[106 * 4] = "SPI2_DAT2", "GPIO106", "GPIO106", "GPIO106",
|
||||
[107 * 4] = "SPI2_DAT3", "GPIO107", "GPIO107", "GPIO107",
|
||||
[113 * 4] = "SMBUS0_SCL", "I2C2_SCL", "I3C2_SCL", "GPIO113",
|
||||
[114 * 4] = "SMBUS0_SDA", "I2C2_SDA", "I3C2_SDA", "GPIO114",
|
||||
[115 * 4] = "CLK_REQ1_L", "GPIO115", "GPIO115", "GPIO115",
|
||||
[116 * 4] = "CLK_REQ2_L", "GPIO116", "GPIO116", "GPIO116",
|
||||
[130 * 4] = "GPIO130", "GPIO130", "GPIO130", "GPIO130",
|
||||
[131 * 4] = "CLK_REQ3_L", "GPIO131", "GPIO131", "GPIO131",
|
||||
[132 * 4] = "CLK_REQ4_L", "OSCIN", "GPIO132", "GPIO132",
|
||||
[135 * 4] = "GPIO135", "UART2_CTS_L", "UART3_TXD", "GPIO135",
|
||||
[136 * 4] = "GPIO136", "UART2_RXD", "GPIO136", "GPIO136",
|
||||
[137 * 4] = "GPIO137", "UART2_RTS_L", "UART3_RXD", "GPIO137",
|
||||
[138 * 4] = "GPIO138", "UART2_TXD", "GPIO138", "GPIO138",
|
||||
[139 * 4] = "GPIO139", "UART2_INTR", "GPIO139", "GPIO139",
|
||||
[140 * 4] = "GPIO140", "UART0_CTS_L", "UART1_TXD", "GPIO140",
|
||||
[141 * 4] = "GPIO141", "UART0_RXD", "GPIO141", "GPIO141",
|
||||
[142 * 4] = "GPIO142", "UART0_RTS_L", "UART1_RXD", "GPIO142",
|
||||
[143 * 4] = "GPIO143", "UART0_TXD", "GPIO143", "GPIO143",
|
||||
[144 * 4] = "GPIO144", "SHUTDOWN_L", "UART0_INTR", "GPIO144",
|
||||
[145 * 4] = "I2C0_SCL", "I3C0_SCL", "GPIO145", "GPIO145",
|
||||
[146 * 4] = "I2C0_SDA", "I3C0_SDA", "GPIO146", "GPIO146",
|
||||
[147 * 4] = "I2C1_SCL", "I3C1_SCL", "GPIO147", "GPIO147",
|
||||
[148 * 4] = "I2C1_SDA", "I3C1_SDA", "GPIO148", "GPIO148",
|
||||
[153 * 4] = "GPIO153", "UART4_CTS_L", "GPIO153", "GPIO153",
|
||||
[154 * 4] = "GPIO154", "UART4_RTS_L", "GPIO154", "GPIO154",
|
||||
[155 * 4] = "GPIO155", "UART4_RXD", "GPIO155", "GPIO155",
|
||||
[156 * 4] = "GPIO156", "UART4_TXD", "GPIO156", "GPIO156",
|
||||
[157 * 4] = "GPIO157", "UART4_INTR", "GPIO157", "GPIO157",
|
||||
};
|
||||
|
||||
const uint8_t kunlun_iomux_group_defaults[] = {
|
||||
[0 ... AMD_IOMUX_SIZE - 1] = 0x00,
|
||||
[0x13] = 0x01,
|
||||
|
|
@ -115,6 +199,10 @@ const uint8_t kunlun_iomux_group_defaults[] = {
|
|||
[0x8E] = 0x01,
|
||||
};
|
||||
|
||||
const uint8_t tacoma_iomux_group_defaults[] = {
|
||||
[0 ... AMD_IOMUX_SIZE - 1] = 0x00
|
||||
};
|
||||
|
||||
const uint32_t kunlun_gpio_group_defaults[] = {
|
||||
[0 ... 4 * AMD_GPIO_BANK_SIZE - 1] = 0,
|
||||
[0x0000] = 0x00140000, 0x00140000, 0x00140000, 0x00140000,
|
||||
|
|
@ -146,6 +234,39 @@ const uint32_t kunlun_gpio_group_defaults[] = {
|
|||
[0x0260 / 4] = 0x00040000, 0x00000000, 0x00000000, 0x00000000,
|
||||
};
|
||||
|
||||
const uint32_t tacoma_gpio_group_defaults[] = {
|
||||
[0 ... 4 * AMD_GPIO_BANK_SIZE - 1] = 0,
|
||||
[0x0000] = 0x00140000, 0x00140000, 0x00140000, 0x00140000,
|
||||
[0x0010 / 4] = 0x00240000, 0x00240000, 0x00240000, 0x00140000,
|
||||
[0x0020 / 4] = 0x00240000, 0x00240000, 0x00140000, 0x00140000,
|
||||
[0x0030 / 4] = 0x00140000, 0x00000000, 0x00000000, 0x00000000,
|
||||
[0x0040 / 4] = 0x00140000, 0x00140000, 0x00140000, 0x00000000,
|
||||
[0x0050 / 4] = 0x00060000, 0x00140000, 0x00240000, 0x00140000,
|
||||
[0x0060 / 4] = 0x00140000, 0x00000000, 0x00240000, 0x00240000,
|
||||
[0x0070 / 4] = 0x00000000, 0x00140000, 0x00140000, 0x00140000,
|
||||
[0x0080 / 4] = 0x00240000, 0x00000000, 0x00000000, 0x00000000,
|
||||
[0x0090 / 4] = 0x00000000, 0x00000000, 0x00140000, 0x00140000,
|
||||
[0x00A0 / 4] = 0x00240000, 0x00000000, 0x00140000, 0x00000000,
|
||||
[0x0100 / 4] = 0x00000000, 0x00000000, 0x00000000, 0x00240000,
|
||||
[0x0110 / 4] = 0x00140000, 0x00140000, 0x00240000, 0x00000000,
|
||||
[0x0120 / 4] = 0x00000000, 0x00000000, 0x00140000, 0x00140000,
|
||||
[0x0130 / 4] = 0x00240000, 0x00240000, 0x00140000, 0x00140000,
|
||||
[0x0140 / 4] = 0x00240000, 0x00240000, 0x00000000, 0x00000000,
|
||||
[0x0150 / 4] = 0x00140000, 0x00140000, 0x00140000, 0x00000000,
|
||||
[0x0160 / 4] = 0x00000000, 0x00140000, 0x00140000, 0x00240000,
|
||||
[0x0170 / 4] = 0x00140000, 0x00000000, 0x00000000, 0x00000000,
|
||||
[0x01A0 / 4] = 0x00240000, 0x00240000, 0x00140000, 0x00140000,
|
||||
[0x01C0 / 4] = 0x00000000, 0x00100000, 0x00140000, 0x00160000,
|
||||
[0x01D0 / 4] = 0x00140000, 0x00000000, 0x00000000, 0x00000000,
|
||||
[0x0200 / 4] = 0x00000000, 0x00000000, 0x00140000, 0x00140000,
|
||||
[0x0210 / 4] = 0x00140000, 0x00000000, 0x00000000, 0x00240000,
|
||||
[0x0220 / 4] = 0x00240000, 0x00140000, 0x00140000, 0x00240000,
|
||||
[0x0230 / 4] = 0x00240000, 0x00240000, 0x00140000, 0x00140000,
|
||||
[0x0240 / 4] = 0x00240000, 0x00000000, 0x00060000, 0x00000000,
|
||||
[0x0250 / 4] = 0x00060000, 0x00000000, 0x00000000, 0x00000000,
|
||||
[0x0260 / 4] = 0x00000000, 0x00240000, 0x00140000, 0x00240000,
|
||||
[0x0260 / 4] = 0x00140000, 0x00240000, 0x00000000, 0x00000000,
|
||||
};
|
||||
|
||||
#pragma GCC diagnostic pop
|
||||
|
||||
|
|
@ -153,6 +274,10 @@ const uint16_t kunlun_special_gpio_regs[] = {
|
|||
0x0fc, 0x1fc, 0x2f0, 0x02f4, 0x2f8, 0x2fc
|
||||
};
|
||||
|
||||
const uint16_t tacoma_special_gpio_regs[] = {
|
||||
0x0fc, 0x2f0, 0x02f4, 0x2f8, 0x2fc
|
||||
};
|
||||
|
||||
const struct gpio_group kunlun_gpio_group = {
|
||||
.iomux_defaults = kunlun_iomux_group_defaults,
|
||||
.gpio_names = kunlun_iomux_gpio_names,
|
||||
|
|
@ -164,6 +289,17 @@ const struct gpio_group kunlun_gpio_group = {
|
|||
.acpimmio_iomux_offset = 0x0d00,
|
||||
};
|
||||
|
||||
const struct gpio_group tacoma_gpio_group = {
|
||||
.iomux_defaults = tacoma_iomux_group_defaults,
|
||||
.gpio_names = tacoma_iomux_gpio_names,
|
||||
.gpio_bank_count = 4,
|
||||
.gpio_defaults = tacoma_gpio_group_defaults,
|
||||
.special_gpio_regs = tacoma_special_gpio_regs,
|
||||
.special_gpio_regs_size = ARRAY_SIZE(tacoma_special_gpio_regs),
|
||||
.acpimmio_gpio_offset = 0x1500,
|
||||
.acpimmio_iomux_offset = 0x0d00,
|
||||
};
|
||||
|
||||
static const io_register_t fch_gpio_reg_fields[] = {
|
||||
{ 0, 4, "DebounceTmrOut" },
|
||||
{ 4, 1, "DebounceTmrOutUnit" },
|
||||
|
|
@ -278,7 +414,7 @@ static bool is_special_gpio_register(uint16_t reg, const struct gpio_group *sb_g
|
|||
return false;
|
||||
}
|
||||
|
||||
int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
|
||||
int print_gpios(struct pci_dev *sb, struct pci_dev *nb, int show_all, int show_diffs)
|
||||
{
|
||||
size_t i;
|
||||
const struct gpio_group *sb_gpio_group = NULL;
|
||||
|
|
@ -297,19 +433,28 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
|
|||
|
||||
switch (smbus_rev) {
|
||||
case 0x71:
|
||||
sb_gpio_group = &kunlun_gpio_group;
|
||||
acpi_mmio_smn_bar = AMD_BRH_IOMUX_SMN_BASE;
|
||||
use_smn = true;
|
||||
switch (nb->device_id) {
|
||||
case PCI_DEVICE_ID_AMD_BRH_ROOT_COMPLEX:
|
||||
sb_gpio_group = &kunlun_gpio_group;
|
||||
acpi_mmio_smn_bar = AMD_FCH_ACPIMMIO_SMN_BASE;
|
||||
use_smn = true;
|
||||
break;
|
||||
case PCI_DEVICE_ID_AMD_PHX_ROOT_COMPLEX:
|
||||
sb_gpio_group = &tacoma_gpio_group;
|
||||
acpi_mmio_smn_bar = AMD_FCH_ACPIMMIO_SMN_BASE;
|
||||
use_smn = true;
|
||||
break;
|
||||
default:
|
||||
goto err_out;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n");
|
||||
return 1;
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
break;
|
||||
default:
|
||||
printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n");
|
||||
return 1;
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
if (show_diffs && !show_all)
|
||||
|
|
@ -391,4 +536,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
|
|||
}
|
||||
|
||||
return 0;
|
||||
err_out:
|
||||
printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n");
|
||||
return 1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -118,13 +118,56 @@ static const struct irq_routing_table kunlun_irq_routing[] = {
|
|||
{ { 0x79, 1, "UART3" }, NULL },
|
||||
};
|
||||
|
||||
static const struct irq_routing_table tacoma_irq_routing[] = {
|
||||
{ { 0x00, 1, "INTA#" }, NULL },
|
||||
{ { 0x01, 1, "INTB#" }, NULL },
|
||||
{ { 0x02, 1, "INTC#" }, NULL },
|
||||
{ { 0x03, 1, "INTD#" }, NULL },
|
||||
{ { 0x04, 1, "INTE#" }, NULL },
|
||||
{ { 0x05, 1, "INTF#/GENINT2" }, NULL },
|
||||
{ { 0x06, 1, "INTG#" }, NULL },
|
||||
{ { 0x07, 1, "INTH#" }, NULL },
|
||||
{ { 0x08, 1, "Misc" }, print_misc_irq },
|
||||
{ { 0x09, 1, "Misc0" }, print_misc0_irq },
|
||||
{ { 0x0A, 1, "Misc1/HPET_L" }, NULL },
|
||||
{ { 0x0B, 1, "Misc2/HPET_H" }, NULL },
|
||||
{ { 0x0C, 1, "INTA from SERIRQ" }, NULL },
|
||||
{ { 0x0D, 1, "INTB from SERIRQ" }, NULL },
|
||||
{ { 0x0E, 1, "INTC from SERIRQ" }, NULL },
|
||||
{ { 0x0F, 1, "INTD from SERIRQ" }, NULL },
|
||||
{ { 0x10, 1, "SCI" }, NULL },
|
||||
{ { 0x11, 1, "SMBUS0" }, NULL },
|
||||
{ { 0x12, 1, "ASF" }, NULL },
|
||||
{ { 0x16, 1, "PerMon" }, NULL },
|
||||
{ { 0x17, 1, "SD" }, NULL },
|
||||
{ { 0x1A, 1, "SDIO" }, NULL },
|
||||
{ { 0x20, 1, "CIR (no IRQ connected)" }, NULL },
|
||||
{ { 0x21, 1, "GPIOa (from PAD_FANIN0)" }, NULL },
|
||||
{ { 0x22, 1, "GPIOb (from PAD_FANOUT0)" }, NULL },
|
||||
{ { 0x23, 1, "GPIOc (no IRQ connected)" }, NULL },
|
||||
{ { 0x43, 1, "EMMC" }, NULL },
|
||||
{ { 0x60, 1, "Gevent SCI interrupt" }, NULL },
|
||||
{ { 0x61, 1, "Gevent SMI interrupt" }, NULL },
|
||||
{ { 0x62, 1, "GPIO controller interrupt" }, NULL },
|
||||
{ { 0x70, 1, "I2C0" }, NULL },
|
||||
{ { 0x71, 1, "I2C1" }, NULL },
|
||||
{ { 0x72, 1, "I2C2" }, NULL },
|
||||
{ { 0x73, 1, "I2C3" }, NULL },
|
||||
{ { 0x74, 1, "UART0" }, NULL },
|
||||
{ { 0x75, 1, "UART1" }, NULL },
|
||||
{ { 0x76, 1, "I2C4" }, NULL },
|
||||
{ { 0x77, 1, "UART4" }, NULL },
|
||||
{ { 0x78, 1, "UART2" }, NULL },
|
||||
{ { 0x79, 1, "UART3" }, NULL },
|
||||
};
|
||||
|
||||
static uint8_t read_irq_reg(uint8_t addr)
|
||||
{
|
||||
outb(addr, AMD_PCI_INTR_IDX);
|
||||
return inb(AMD_PCI_INTR_DATA);
|
||||
}
|
||||
|
||||
int print_irq_routing(struct pci_dev *sb)
|
||||
int print_irq_routing(struct pci_dev *sb,struct pci_dev *nb)
|
||||
{
|
||||
int i, irq_table_size;
|
||||
const struct irq_routing_table *irq_table = NULL;
|
||||
|
|
@ -141,18 +184,25 @@ int print_irq_routing(struct pci_dev *sb)
|
|||
|
||||
switch (smbus_rev) {
|
||||
case 0x71:
|
||||
irq_table_size = ARRAY_SIZE(kunlun_irq_routing);
|
||||
irq_table = kunlun_irq_routing;
|
||||
switch (nb->device_id) {
|
||||
case PCI_DEVICE_ID_AMD_BRH_ROOT_COMPLEX:
|
||||
irq_table_size = ARRAY_SIZE(kunlun_irq_routing);
|
||||
irq_table = kunlun_irq_routing;
|
||||
break;
|
||||
case PCI_DEVICE_ID_AMD_PHX_ROOT_COMPLEX:
|
||||
irq_table_size = ARRAY_SIZE(tacoma_irq_routing);
|
||||
irq_table = tacoma_irq_routing;
|
||||
break;
|
||||
default:
|
||||
goto err_out;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
printf("Error: Dumping IRQ routing on this southbridge is not (yet) supported.\n");
|
||||
return 1;
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
break;
|
||||
default:
|
||||
printf("Error: Dumping IRQ routing on this southbridge is not (yet) supported.\n");
|
||||
return 1;
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
printf("PIC routing:\n\n");
|
||||
|
|
@ -177,4 +227,8 @@ int print_irq_routing(struct pci_dev *sb)
|
|||
printf("========================================\n");
|
||||
|
||||
return 0;
|
||||
|
||||
err_out:
|
||||
printf("Error: Dumping IRQ routing on this southbridge is not (yet) supported.\n");
|
||||
return 1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
#include <commonlib/helpers.h>
|
||||
#include "amdtool.h"
|
||||
|
||||
static const io_register_t kunlun_lpc_cfg_registers[] = {
|
||||
static const io_register_t lpc_cfg_registers[] = {
|
||||
{0x00, 4, "ID"},
|
||||
{0x04, 2, "CMD"},
|
||||
{0x06, 2, "STS"},
|
||||
|
|
@ -81,8 +81,8 @@ int print_lpc(struct pci_dev *sb)
|
|||
|
||||
switch (smbus_rev) {
|
||||
case 0x71:
|
||||
cfg_registers = kunlun_lpc_cfg_registers;
|
||||
cfg_registers_size = ARRAY_SIZE(kunlun_lpc_cfg_registers);
|
||||
cfg_registers = lpc_cfg_registers;
|
||||
cfg_registers_size = ARRAY_SIZE(lpc_cfg_registers);
|
||||
break;
|
||||
default:
|
||||
printf("Error: Dumping LPC on this southbridge is not (yet) supported.\n");
|
||||
|
|
|
|||
|
|
@ -134,6 +134,7 @@ void print_psb(struct pci_dev *nb)
|
|||
|
||||
switch (nb->device_id) {
|
||||
case PCI_DEVICE_ID_AMD_BRH_ROOT_COMPLEX:
|
||||
case PCI_DEVICE_ID_AMD_PHX_ROOT_COMPLEX:
|
||||
print_psb_status_v2(c2p_msg_38_error_codes,
|
||||
breithorn_c2p_msg_37_fields,
|
||||
ARRAY_SIZE(breithorn_c2p_msg_37_fields),
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
|
||||
#define AMD_FCH_SPIBAR_OFFSET 0xa0
|
||||
|
||||
#define BRH_SPI_SMN_BASE 0x2DC4000
|
||||
#define SPI_SMN_BASE 0x2DC4000
|
||||
|
||||
static const io_register_t spi100_speed_cfg_fields[] = {
|
||||
{ 0x0, 4, "TPM Speed" },
|
||||
|
|
@ -27,7 +27,7 @@ static const io_register_t spi100_host_prefetch_cfg_fields[] = {
|
|||
{ 0xf, 1, "Host Burst to 4DW Enable" },
|
||||
};
|
||||
|
||||
static const io_register_t kunlun_spi_cntl0_fields[] = {
|
||||
static const io_register_t spi_cntl0_fields[] = {
|
||||
{ 0x0, 8, "Spi OpCode (Reserved)" },
|
||||
{ 0x8, 1, "Disable Index Retry" },
|
||||
{ 0x9, 1, "Index Cacheline Stop" },
|
||||
|
|
@ -49,7 +49,13 @@ static const io_register_t kunlun_alt_spi_cs_fields[] = {
|
|||
{ 0x6, 1, "Lock SPI CS" },
|
||||
};
|
||||
|
||||
static const char * const kunlun_spi100_speed_values[] = {
|
||||
static const io_register_t tacoma_alt_spi_cs_fields[] = {
|
||||
{ 0x0, 2, "Alt SPI CS Enable" },
|
||||
{ 0x3, 1, "SPI Protect Enable 0" },
|
||||
{ 0x5, 1, "SPI Protect Lock" },
|
||||
};
|
||||
|
||||
static const char * const spi100_speed_values[] = {
|
||||
"66.66 MHz",
|
||||
"33.33 MHz",
|
||||
"22.22 MHz",
|
||||
|
|
@ -60,7 +66,7 @@ static const char * const kunlun_spi100_speed_values[] = {
|
|||
"Defined in SPIx6C[13:8]"
|
||||
};
|
||||
|
||||
static const io_register_t kunlun_spi_bar_registers[] = {
|
||||
static const io_register_t spi_bar_registers[] = {
|
||||
{ 0x00, 4, "SPI Control 0" },
|
||||
{ 0x04, 4, "SPI Restricted Command" },
|
||||
{ 0x08, 4, "SPI Restricted Command 2" },
|
||||
|
|
@ -144,8 +150,8 @@ static int print_spi_cntrl0(struct pci_dev *sb)
|
|||
switch (smbus_rev) {
|
||||
case 0x71:
|
||||
spi_cntrl0 = spi_read32(0);
|
||||
spi_cntrl_register = kunlun_spi_cntl0_fields;
|
||||
size = ARRAY_SIZE(kunlun_spi_cntl0_fields);
|
||||
spi_cntrl_register = spi_cntl0_fields;
|
||||
size = ARRAY_SIZE(spi_cntl0_fields);
|
||||
break;
|
||||
default:
|
||||
printf("Error: Dumping SPI CNTRL on this southbridge is not (yet) supported.\n");
|
||||
|
|
@ -171,7 +177,7 @@ static int print_spi_cntrl0(struct pci_dev *sb)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int print_spi_alt_cs(struct pci_dev *sb)
|
||||
static int print_spi_alt_cs(struct pci_dev *sb, struct pci_dev *nb)
|
||||
{
|
||||
int i, size = 0;
|
||||
int smbus_rev = 0;
|
||||
|
|
@ -188,19 +194,28 @@ static int print_spi_alt_cs(struct pci_dev *sb)
|
|||
|
||||
switch (smbus_rev) {
|
||||
case 0x71:
|
||||
spi_alt_cs = spi_read8(0x1d);
|
||||
spi_alt_cs_register = kunlun_alt_spi_cs_fields;
|
||||
size = ARRAY_SIZE(kunlun_alt_spi_cs_fields);
|
||||
switch (nb->device_id) {
|
||||
case PCI_DEVICE_ID_AMD_BRH_ROOT_COMPLEX:
|
||||
spi_alt_cs = spi_read8(0x1d);
|
||||
spi_alt_cs_register = kunlun_alt_spi_cs_fields;
|
||||
size = ARRAY_SIZE(kunlun_alt_spi_cs_fields);
|
||||
break;
|
||||
case PCI_DEVICE_ID_AMD_PHX_ROOT_COMPLEX:
|
||||
spi_alt_cs = spi_read8(0x1d);
|
||||
spi_alt_cs_register = tacoma_alt_spi_cs_fields;
|
||||
size = ARRAY_SIZE(tacoma_alt_spi_cs_fields);
|
||||
break;
|
||||
default:
|
||||
goto alt_cs_err;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
printf("Error: Dumping SPI_ALT_CS on this southbridge is not (yet) supported.\n");
|
||||
return 1;
|
||||
goto alt_cs_err;
|
||||
}
|
||||
|
||||
break;
|
||||
default:
|
||||
printf("Error: Dumping SPI_ALT_CS on this southbridge is not (yet) supported.\n");
|
||||
return 1;
|
||||
goto alt_cs_err;
|
||||
}
|
||||
|
||||
printf("SPI_ALT_CS = 0x%02x\n\n", spi_alt_cs);
|
||||
|
|
@ -214,6 +229,10 @@ static int print_spi_alt_cs(struct pci_dev *sb)
|
|||
}
|
||||
|
||||
return 0;
|
||||
|
||||
alt_cs_err:
|
||||
printf("Error: Dumping SPI_ALT_CS on this southbridge is not (yet) supported.\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int print_spi_speed_config(struct pci_dev *sb)
|
||||
|
|
@ -237,8 +256,8 @@ static int print_spi_speed_config(struct pci_dev *sb)
|
|||
spi_speed_cfg = spi_read16(0x22);
|
||||
spi_speed_cfg_register = spi100_speed_cfg_fields;
|
||||
size = ARRAY_SIZE(spi100_speed_cfg_fields);
|
||||
speed_values = kunlun_spi100_speed_values;
|
||||
values_size = ARRAY_SIZE(kunlun_spi100_speed_values);
|
||||
speed_values = spi100_speed_values;
|
||||
values_size = ARRAY_SIZE(spi100_speed_values);
|
||||
break;
|
||||
default:
|
||||
printf("Error: Dumping SPI100_SPEED_CFG on this southbridge is not (yet) supported.\n");
|
||||
|
|
@ -313,7 +332,7 @@ static int print_spi_host_prefetch(struct pci_dev *sb)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int print_spibar(struct pci_dev *sb)
|
||||
static int print_spibar(struct pci_dev *sb, struct pci_dev *nb)
|
||||
{
|
||||
int i, size = 0, spi_size = 0x1000;
|
||||
uint32_t spibar_phys, spibar_mask;
|
||||
|
|
@ -330,10 +349,10 @@ static int print_spibar(struct pci_dev *sb)
|
|||
|
||||
switch (smbus_rev) {
|
||||
case 0x71:
|
||||
size = ARRAY_SIZE(kunlun_spi_bar_registers);
|
||||
spi_register = kunlun_spi_bar_registers;
|
||||
size = ARRAY_SIZE(spi_bar_registers);
|
||||
spi_register = spi_bar_registers;
|
||||
spibar_mask = 0xffffff00;
|
||||
spi_smn_base = BRH_SPI_SMN_BASE;
|
||||
spi_smn_base = SPI_SMN_BASE;
|
||||
break;
|
||||
default:
|
||||
printf("Error: Dumping SPI on this southbridge is not (yet) supported.\n");
|
||||
|
|
@ -387,7 +406,7 @@ static int print_spibar(struct pci_dev *sb)
|
|||
}
|
||||
|
||||
print_spi_cntrl0(sb);
|
||||
print_spi_alt_cs(sb);
|
||||
print_spi_alt_cs(sb, nb);
|
||||
print_spi_speed_config(sb);
|
||||
print_spi_host_prefetch(sb);
|
||||
|
||||
|
|
@ -399,7 +418,7 @@ static int print_spibar(struct pci_dev *sb)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int print_spi(struct pci_dev *sb)
|
||||
int print_spi(struct pci_dev *sb, struct pci_dev *nb)
|
||||
{
|
||||
return print_spibar(sb);
|
||||
return print_spibar(sb, nb);
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue