brox_rtk_ec share the same power design with brox,
so follow brox set as 9W.
BUG=b:414474440
TEST=system can boot when AC only.
Change-Id: Ia05b331f229127b898f4549d5ba1ac2771ac8b7b
Signed-off-by: Elmo Lan <elmo_lan@realtek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
compiler-rt is not a variable used by the LLVM_ENABLE_PROJECTS config,
but has a separate configuration option.
Change-Id: Iacd9b5f1fc1444b3dd1a785b91510f346e7a2f51
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80737
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The old test code used outdated function declarations that break with
C23 in GCC 15. Instead of forcing C17 standard:
1. Add full prototype for g() function
2. Use 'void' for empty parameters
3. Clean up messy formatting
This keeps C23 compatibility while fixing the build.
Tested with GCC 15.1.0
The -std=gnu17 workaround is no longer needed.
Change-Id: I718a5ed5c11742b1c3448abf7198c96ac78bc98a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
"--parallel" is not a valid option for CMake.
Change-Id: Idba76ce6a29e5d582ce49aa91ce4013aebc6d835
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
The mb/adlink directory no longer exists, so remove it from the list of
checked directories.
Add a check to make sure that the directory exists before trying to lint
it in the future.
Change-Id: I59874cb7356c2e8eeb8fc216f2930b3d8ef513c7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88237
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Change .inc to .mk. This was missed when renaming the makefiles.
- Verify that dirs/files exist before checking.
- Use $FINDOPTS to control search when not in a git repo.
Change-Id: If0d80403a3e799b8103164cc075601a50c33a8d9
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The Kconfig linter was browsing into the openSIL tree and reporting
issues for the release because it can't use git grep there. This change
explicitly tells the Kconfig linter to ignore the openSIL submodule.
Change-Id: Ia0399225cced9f199a6d2a90bc6c2af905ff4e99
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The binary files were not being correctly filtered. This tells grep to
just ignore binary files. This isn't particularly important inside the
git tree, but for releases where we can't use git grep, it becomes an
issue.
Change-Id: I2852ea1e8b0f337aa5c78daa5e9dbd0c3d6768a9
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Group the variables by toolchain (GCC vs Clang) and order them by
build sequence.
Change-Id: Ifd911b719882adf1d2e9211f6009b579f8177abe
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88227
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow baseboard nissa and project pujjocento project to setting
GPE configuration.
BUG=b:395763555
BRANCH=none
TEST=Build and boot to OS.
Change-Id: I75deadd0c1b7218c2d0820d637cc2ec02bf9154f
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88199
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add MT62F2G32D4DS-023 WT:C in the memory_parts.json and re-generate the
SPD.
BUG=b:427327667
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I8f244c2f91d66ffcbc1ec2642304f77b522da09f
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Replace `data.vbt` with version from Intel FSP repository to match
the updated FSP release used in this platform.
This change is required when using 3rdparty/fsp/AlderLakeFspBinPkg
commit: 15848ee4934acbd94069454f369e9869bb0f1295
which introduces the "IoT ADL-N IPU25.3 (6114_00)" release.
With the previous VBT, the system boots but fails to display
any graphics output (HDMI) during firmware POST and OS boot.
This updated VBT resolves the display initialization issue.
Source:
15848ee493/AlderLakeFspBinPkg/IoT/AlderLakeN/Vbt/Vbt_ADLN.bin
Change-Id: If948d3bbef02f516067db0bad07167bdf7c81ce2
Signed-off-by: Kun-Yi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88191
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The addresses and their modes should now all be correct and we can
therefore treat the case where `addr` and `mode` do not match as an
actual error.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Id12c29648c0437dd082b471689ec3649314dee1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
There is no need to treat the APOB_NV binary special anymore, as
the mode and address should now always match for the APOB_NV address.
Since phoenix SOC generation this code even errors out on VBOOT
platforms, because APOB_NV address is actually a BIOS relative address.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I64d43e654e3694d7590edcba9a87c98367a7256c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
In order to not change the actual binaries in too many ways,
commit a7eb390796 ("mb/*/*/*.fmd: Start flash at 0") kept the current
behaviour in which the address mode was set to ADDR_REL_BIOS, but the
address itself was actually a physical address. It has probably only
worked all these years, because PSP/ABL code did apparently ignore the
address mode for this specific binary for generations previous to
phoenix.
Assuming the address mode is actually ignored we might as well use the
right address mode corresponding to the address that is set. That way
tooling that is used to inspect this image is not completely confused.
This sets the ADDR_PHYSICAL address mode to all generations that have
the APOB NV quirk. It therefore only affects these generations (previous
to phoenix).
tested:
Check that the binary is identical on bilby, morphius, kahlee, onyx and
birman_plus. bilby, kahlee, onyx don't have an APOB_NV region. morphius
uses a physical address anyway and birman_plus doesn't have the
apob_nv_quirk.
Check that only the address mode is changed to ADDR_PHYSICAL (and the
checksum of the table) on guybrush, frostflow, crater, chausie.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ib2edfb27ba0fa316f1fbe31bc0ad8e2060a70f48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87296
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This moves the code to amdfwtool.c, because the subsequent patch needs
it to be there in order to properly update the address_mode.
This patch should not change the binary in ANY way on any platform.
tested: Check that the binary is identical on guybrush, birman_plus,
frostflow, bilby, crater, grunt, myst, onyx_poc, morphius
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9c64c67ff8b9656516344fdafbfd2254abfceeef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The Fn key on kinmen emits a scancode of 94 (0x5e).
BUG=b:409148565
TEST=Flash kinmen, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`
Change-Id: If919c6f421719e06399620b17e1f4f5a161a7de2
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88207
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure GPIOs and related settings to align with the specifications
provided in the schematic_1433518 and platform mapping document
version Rev0p85.
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: Id63c52ffa2d111bd1f7c51831aa7087bef6006d9
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
and NC_LOCK GPP_F09
To ensure that poweroff is normal and DUT can boot to S0
when press power button or lid open in S5 state, the WAKE pin
GPP_V12 needs to be pulled high on soc side and GPP_F09 needs
to be configured as NC_LOCK.
BUG=413283383
TEST=emege-fatcat coreboot and poweroff and
s5 boot functions are normal
Change-Id: Iea8e44aa263dda7e447be1c9e53ffabf93c95a80
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88211
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit extends libpayload's understanding of SPI flash devices by
adding a flags field to both struct cb_spi_flash and struct
sysinfo_t.spi_flash.
The new CB_SPI_FLASH_FLAG_IN_4BYTE_ADDR_MODE flag will be populated
from the coreboot table's lb_spi_flash entry. This allows payloads to
reliably determine if the SPI flash is currently configured for 4-byte
addressing, enabling more robust flash operations without needing to
re-probe or re-enforce the mode.
Note: `erase_cmd` type was changed from uint32_t to uint8_t. This is
because only the lowest byte of the original uint32_t was ever used.
The change ensures proper sizing, maintains compatibility with older
coreboot tables, and makes the remaining space available for new fields.
BUG=b:417900125
TEST=Able to build google/bluey.
Change-Id: I101a50f899e82e9412024a049a9df59c5813313a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88182
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adds a new flags field to the lb_spi_flash coreboot table to indicate
if the SPI flash is operating in 4-byte address mode.
This allows payloads to query the current address mode directly from the
coreboot table, preventing redundant checks or re-enforcement of the
mode. The flag is set based on the
CONFIG_SPI_FLASH_FORCE_4_BYTE_ADDR_MODE configuration.
Important: `erase_cmd` was reduced from uint32_t to uint8_t.
Only the least significant byte was ever relevant, so this change
ensures accurate type representation, maintains backward compatibility
with existing coreboot table structures, and frees up space.
BUG=b:417900125
TEST=Able to build google/bluey.
Change-Id: I406536432b2a0c7f4108e5b33d5a20c272d917b0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit refactors the logic for entering and exiting 4-byte
addressing mode in the SPI flash driver.
Changes include:
- Renaming SPI_FLASH_EXIT_4BYTE_STAGE to SPI_FIRST_STAGE to better
reflect its broader applicability to initial boot stages.
- Applying SPI_FIRST_STAGE to both the force 4-byte address mode
and exit 4-byte address mode configurations, ensuring these
operations are only attempted during the appropriate early boot
phases.
- Renaming CMD_FORCE_4BYTE_ADDR_MODE to CMD_ENTER_4BYTE_ADDR_MODE for
consistency and clearer semantics, as 0xb7 is typically used to enter
this mode.
BUG=b:417900125
TEST=Able to build google/bluey.
Change-Id: I79e2c7bbd222fd0d76072860bdf3feba7e7d587d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit aligns the I2S and DMIC pad configurations in `fw_config.c`
and `gpio.c` for the Fatcat mainboard.
The changes include:
- Reordering I2S1 pad configurations in `fw_config.c` to match their
intended functions (TXD, RXD, SCLK, SFRM).
- Adding I2S2 pad configurations (SCLK, SFRM, TXD, RXD) to
`fw_config.c`.
- Removing duplicate DMIC_CLK and DMIC_DATA pad configurations from
`fw_config.c`.
- Moving the CODEC_EN pad configuration from `fp_disable_pads` and
`fp_enable_pads` in `fw_config.c` to `gpio_table` in `gpio.c`, and
changing its power state to DEEP (as applicable)
- Updating GPP_F17 to CODEC_INT_N with GPI configuration in `gpio.c`.
These adjustments ensure correct and consistent pad assignments
for audio functionality.
TEST=Able to hear devbeep while booting google/fatcat.
Change-Id: I477ffeef113e2f3a4d0e759b9416f9e7e5427ec3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
These are the release notes planned to go out with the 25.06 release.
Note that we've removed the bugs section. We may look at adding
"Fixed Bugs" and "New Bugs" in the future, but it was depressing not
seeing changes between the releases.
Change-Id: I8cedbdb7b05605d1904446590fb25552a7e0c727
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88206
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add FW_CONFIG probe based on pujjolo boxster of below devices:
Mipi camera
Schematic version: 500E_S3A0_TWL_MB_FVT_20250527
BUG=b:395763555
BRANCH=none
TEST=Boot to OS and verify the mipi camera device are set based on
fw_config.
Change-Id: I8760585d5012073fb3ca1d2636474a07b8eea97a
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
1. This change is based on the fact that the code for the pujjolo
and pujjoquince projects is shared.
2. Add fingerprint function and use proto board to verify the
functionality.
Schematic version: 500E_S3A0_TWL_MB_FVT_20250527
BUG=b:395763555
BRANCH=none
TEST=Use ectool --name=cros_fp version will return fingerprint
version information and check the functionality works.
Change-Id: I557c7b6a10b137604ff4abae81c7a231c48b099d
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88186
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current QCOM fixup function qualcomm_find_hash() assumes only one
ELF will be loaded by the primary boot loader and the bootblock is one
of the segments of that ELF.
However, the primary boot loader for QCOM X1P42100 SoC loads multiple
ELFs for QC_SEC, TME Sequencer, TME FW and bootblock. This change
updates the fixup functionality to handle bootblock being a separate
ELF.
If the bootblock offset does not fit within the first ELF, then the
fixup function understands that it is a multi ELF.
Additionally, it ensures the bootblock ELF uses MBN v7 format.
BUG=b:420542130
TEST=1. Create a image.serial.bin and ensure it boots on X1P42100
2. Used the following script to verify the hash
#! /bin/bash
image=/build/bluey/firmware/image-bluey.serial.bin
bin=/tmp/bb.bin
seg=/tmp/bb.seg
hash=/tmp/bb.hash
#
# Bootblock is the final ELF of the multi ELF. Hopefully
# there is no other ELF in ${image}. Get the offset of the
# final ELF in ${image} and get it out
#
bb_offset=`od -Ad -w4 -tx4 ${image} | grep 464c457f | tail -1 | cut -f1 -d ' '`
dd if=${image} of=${bin} skip=1 bs=${bb_offset} &> /dev/null
#
# The last two segments of the bootblock ELF have the actual
# executable and the hash. 'LOAD' is the executable segment and
# the other is the hash segment. Get their offsets and convert
# to decimal.
#
offs=`readelf -lW ${bin} | tail -2 | awk '{print $1" "$2" "$5}'`
offs=(`printf "%s %u %u %s %u %u" ${offs}`)
#
# Get the executable and hash segments
#
if [ ${offs[0]} = "LOAD" ]; then
first=${seg}
second=${hash}
else
first=${hash}
second=${seg}
fi
dd if=${bin} skip=${offs[1]} bs=1 count=${offs[2]} of=${first} &> /dev/null
dd if=${bin} skip=${offs[4]} bs=1 count=${offs[5]} of=${second} &> /dev/null
#
# Find the SHA384 hash for the executable segment
#
sha=`sha384sum ${seg} | cut -f1 -d ' ' | sed 's/../& /g'`
echo ===================================================
echo Expected hash:
echo
echo ${sha} | fold -w48
echo ===================================================
echo
hexdump -C ${hash} | grep -A4 "`echo ${sha} | cut -f1-4 -d ' '`"
Change-Id: If57ba0cc9a4f08b69d7712f27c215339307e73d4
Signed-off-by: Varadarajan Narayanan <vnarayan@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88148
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PBL of QCOM X1P42100 SoC loads image in multi ELF format, which is
a concatenation of TME SEQ, TME FW, QC-SEC and Bootblock binaries.
This script stitches the binaries together into multi ELF image.
Usage: create_multielf.py [-h] -f IN_FILES [-o [OUT_FILE]]
Example: python create_multielf.py -f image1,image2,image3 -o output.bin
Change-Id: I9cdbdf6b5c62663491ccd7d42ab270742760aa0b
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88145
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
1. This change is based on the fact that the code for the pujjolo
and pujjoquince projects is shared.
2. Add SD card function and use proto board to verify the
functionality.
Schematic version: 500E_S3A0_TWL_MB_FVT_20250527
BUG=b:395763555
BRANCH=none
TEST=Boot to OS and verify the mmcblk0 shown which use lsblk
command, and check if sd card could store file in desktop.
Change-Id: Ib7f854d9c902ba3f257d154ae6b95ea443fa78f5
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88184
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This new variant will support PTL pre-production silicon. The existing
`fatcatite` variant will support production silicon.
BUG=b:424355826
TEST=Able to build google/fatcatite4es.
Change-Id: I9c51c1720a354f80edcf8c8ef75bd564dd6a5b5d
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88128
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This new variant will support PTL pre-production silicon. The existing
`fatcatnuvo` variant will support production silicon.
BUG=b:424355826
TEST=Able to build google/fatcatnuvo4es.
Change-Id: I079f9bbf0be9c3149b3f583102bec32f328ab44d
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88129
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This new variant created will support PTL pre-production silicon. The
existing `fatcat` variant will support production silicon.
BUG=b:424355826
TEST=Able to build google/fatcat4es.
Change-Id: I0f925a73a42aaf6d3ae6980169d912374b12d8ae
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit introduces support for the H58G66BK7BX067 memory module
within the Intel PTLRVP mainboard variant. The changes include updates
to several configuration files to recognize and utilize this specific
memory module. The SPD source files and DRAM ID assignments have been
updated accordingly to integrate the new memory module into the build
system. This addition ensures compatibility and functionality with
the H58G66BK7BX067 memory module, allowing for expanded hardware
support and flexibility in memory configurations.
BUG=none
TEST=Build and verify memory module detection and initialization
on supported hardware configuration.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ic281125dd40bbcef50d138e912e7557d6552eb9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88177
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds the necessary configuration for the focaltech
touchscreen (FTSC1000) device, connected to I2C bus 38.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
Datasheet: FT8112_Data_Sheet_V0.2_HKC20240415.pdf
BUG=b:426038745
TEST=emerge-nissa coreboot and focaltech touchscreen can work well.
Change-Id: I478924fbebf2a5ecd60bad48b37bfa6581100601
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This reverts commit 2e495b09d5.
Reason for revert: mmio_tseg is reserved twice in
mc_add_dram_resources, where the duplication is introduced by
commit 43b0ed7089 ("soc/intel/xeon_sp: Improve final MTRR solution")
Change-Id: I0f1bf757d8d1fc449e4efc0ec171c6f982f79e9e
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add support for the new memory CXMT CXDB4CBAM-ML-A.
BUG=b:427090130
TEST=Use part_id_gen to generate related settings
Change-Id: I176fb49c17379fcf454f5a4d3ab4b057b50d34ce
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88167
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
New Touchscreen function for Quandiso project.
Touchscreen panel: HKO RB116AS01-4
Datasheet : Product%20Spec_RB116AS01-4_ver1.0.pdf
BUG=b:424332291
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. Confirm command evtest and touchscreen function is workable.
Change-Id: I6b1f9929fc63c056d7714c9ed67bcaffeebdab8b
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
It causes some name clashes (and therefore overshadowing) of function
names defined in xeon SOC code in later patches of the patch train.
We don't really have a standard naming scheme for callback functions, so
I just added a _func suffix/postfix to indicate the function is a
callback function and to prevent name clashes.
Change-Id: I21811f75ef6e7642a7e4f69997737cd7b8b1cef9
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
get_oled_description is a wrong function declaration. Remove
get_oled_description function declaration and include soc/display.h
for get_active_panel.
Change-Id: Id321882d5b4b00f4114ef7282d13af9003019f62
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88139
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SoCs with dptx_v2 (such as MT8196) use a different eDP MAC design from
old SoCs with dptx_v1. The formulas for register calculation are
different:
- The horizontal blanking (REG_3160_DP_ENCODER0_P0) is hsync + hbp + hfp
on MT8196, while on older SoCs it is hsync + hbp.
- The vertical blanking (REG_3174_DP_ENCODER0_P0) is vsync + vbp + vfp
on MT8196, but vsync + vbp on earlier SoCs.
The current formula for MT8196 only works correctly when ha/va are
multiples of 4 and hfp/vfp are 0. The new formula fixes display errors
at resolutions like 1366x768 (ha=1366, hfp=48).
To distinguish these differences, an edp_version parameter is added.
Also update the following settings for correct configuration:
- Set AUX_RX_UI_CNT_THR_AUX_FOR_26M to 14 to correct the previous
incorrect setting.
- Fix DVO_TGEN_H1 calculation for the case where ha is not a multiple
of 4 (such as 1366).
BUG=b:400886838
BRANCH=rauru
TEST=Check the display function on Navi
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Id0ae6845ce6a06cdcbc3dd9b1f8a63e2890c3b24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88188
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The Ocelot variants must support ES silicon as well as QS silicon. This
CL changes ocelot to ocelot4es, changes ocelotite to ocelotite4es, and
changes ocelotmchp to ocelotmchp4es.
BUG=b:425397790
TEST=`emerge-ocelot` and verify it builds without errors.
Change-Id: Iac0700688e7f616477bf462c5734a70110f9d6d7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88134
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add panel driver in mainboard for skywalker project.
BUG=b:400886838,b:425272330
BRANCH=none
TEST=check edp training pass and show log:
EQ training pass
Change-Id: I7352a6728237842a6819b7129c61a1d4c7646fcb
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88170
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
