The FADT for baytrail had incorrect offsets leading to
the kernel spewing a huge mess of ACPI errors. Fix these offsets
to be initialized in the chipset code.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted into kernel on rambi. Login screen comes up.
Change-Id: I89fc2a4fd800ff01cedf89b51cfb1369aceb9f03
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175663
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This provides the initial support for interrupt routing
in bay trail. It includes both acpi changes and board changes
to ensure the interdependencies are met with the current ASL
code. The PIRQ routing is handled by the mainboard exporting
an irqroute.h header that describes the per device and PIRQ
PCI settings.
There are still a lot of ACPI errors in the kernel with this
change, though.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted rambi into kernel.
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id8a865a24fc8d49743c0b54efdb64aaef52fcd8e
Reviewed-on: https://chromium-review.googlesource.com/175700
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This enables flow control and sets the REQ_SEL field according
to the SPI bus.
Since REQ_SEL is just a constant that is associated with each
channel, a member is added to the tegra_spi_regs struct to hold
the appropriate value.
BUG=none
BRANCH=none
TEST=built and booted on Nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I037aee7e2d422e24a4cbcbc75280ec3c93d3e7bd
Reviewed-on: https://chromium-review.googlesource.com/175630
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
This is needed to let the kernel know it can control everything
and not to disable features.
BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: I40ff15bb931a9be7c31509ec84489083b5af0a82
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175629
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Populate the PCI mmio region from NVS TOLM variable.
Other regions are fixed.
BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: Iec8352b0464ad850a76bd1706c028628c477731d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175628
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This adds the PCI configuration region table to baytrail.
BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: I0d975709a4a18d0f1c5e24581c9fd2190fe2996b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175627
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There is a lot of NVS allocated to things that are not really
used. Most of these are removed and some are moved around.
Thermals are expected to be handled with DPTF so I've removed
that bit of code but have not yet cleaned up the thermal zone.
I left in the SIO BARs since I think we will need those still
even though they may need work still.
BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: Id16ee67e6b3709a303c001afd72947147f938127
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175626
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The top of low memory is also the start of the region where
PCIe resources are allocated. This needs to be passed in
ACPI but is only readable from IOSF.
BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: Iad95335f72dc3e35b837bedb8d52d388c861a330
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175625
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a length define for all the reserved MMIO regions and
use them in the ACPI code to reserve the regions there.
Add a region for the "abort page" documented in the EDS.
BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: I2060dca0636a2fdc0533ddd0826f94add2c272c3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175624
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This shortens the grostesquely huge APBDMACHAN_* defines by
removing unecessary prefixes. Names of fields which appeared at
the end of these huge #defines are preserved as they are
presented in the manual, so searching for them is still easy.
The goal is to make it so that we can actually use the #defines
without the code becoming a hideous, line-broken mess. As they were,
the #defines made code so ugly that it actually became less readable.
Additionally, a couple trivial issues were found and fixed:
- Removes duplicate AHB bus width #defines
- Removes a non-sensical #define that seems to be a result of an
incompleted copy+paste job.
BUG=none
BRANCH=none
TEST=built and booted on Nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I72195ff08ef51bb645a1e1ae5a11346998a12635
Reviewed-on: https://chromium-review.googlesource.com/175631
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Add a graphics_clock function which is where we intend to do all clock
graphics init. This is modeled on how we are doing the UART clock; keep
it all in one place, not spread everywhere. Add sor_clock_{start,stop}
functions. We must start and stop the SOR clocks beore we mess with the
plldp.
BUG=None
TEST=This code builds and boots and shows graphics and depth charge screen.
BRANCH=None
Change-Id: Ida4a73f9020e5542f16d2ab0793fb2116156d562
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/175162
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
These need to be supported for graphics.
BUG=None
TEST=Build and boot and it all still works
BRANCH=None
Change-Id: Ie02cbd3012b320bb59be9e0fb899c09000f29a1b
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/175539
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
- a few clock gating bits were set improperly and was preventing
the system from transitioning out of S0 state.
- the XHCCI registers were not getting the top byte set properly
which includes things like DMA write request size and request
boundary crossing control. This was causing memory corruption.
BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot kernel from USB on rambi with XHCI driver
Change-Id: I8e8135a793dfbaa1f163766702e3a8f19bba9703
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175558
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Low system tables are in this region, and it is probably safer
to keep ASEG reserved.
Also keep the region used by ramoops from being used by the OS
and from being cleared by developer mode boots.
Lots more work needed to make the ACPI tables fully functional.
BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=boot on rambi and see that the kernel finds RSDP and uses ACPI
Change-Id: I4f7064d3cff14a3ecf15b194a1f20c1fa9d5e134
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175554
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This adds the EHCI driver back to libpayload and configures
the devicetree to route ports to EHCI.
This is hopefully just temporary until the issues with XHCI
can be worked out.
BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot from USB on rambi
Change-Id: I0549661f5e5fd83477f4839a05e7e21175b24b64
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175513
This adds required steps to initialize the EHCI controller
on the baytrail platform.
BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot from USB on rambi
Change-Id: I3a5487791e2305616036d4550e260a178c0e1c4d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175512
This adds required steps to initialize the XHCI controller
on the baytrail platform.
Actually using XHCI is causing lots of bad behavior including
apparent memory corruption.
BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: Ic43e04f4b47e107ec3bb0c387a9fc72c3cae0271
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175511
The reg_script stuff only makes sense for those platforms that
need it: ARM V8 and all x86. Have its usage controlled by a config variable.
BUG=None
TEST=the broken nyan build is fixed.
BRANCH=None
Change-Id: Iad54773f412e2d829e68b98fd845cd72ae408ee1
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/175530
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Apparently the LPE device needs a 25MHz clock. Provide
the work around to enable this clock.
BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and booted. Confirmed setting being applied.
Change-Id: Ibff5563436b3025eb8b61ffee3302bd2da872b39
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175493
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The clock control unit needs to be accessed to configure
some of the devices properly. Therefore. provide a way
to access the CCU.
BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built.
Change-Id: I30ed06e6aef81ee99c6d7ab3cbe8f83818b8dee5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175492
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Parts of the audio path are common between the HDA and LPE.
However, those parts are power-controlled by the D-state of
the HDA device. Therefore, one cannot put the HDA into D3Hot
because those audio paths will be shutdown.
BUG=chrome-os-partner:22871
BRANCH=None
TEST=Built and booted through depthcharge. Disabling HDA still
causes a shutdown when performing warm reset, however I
was able to verify the magic sequence was being performed.
Change-Id: I3b01356d85a4b7b902bd896b8eb9e7bc509fcc42
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175491
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Previously it was not known how to put the TXE pci device
into D3Hot. It's been disseminated that this is not a requirement
for disabling the TXE pci device in the function disable register.
Therefore, allow this by returning 0 from place_device_in_d3hot().
BUG=chrome-os-partner:22871
BRANCH=None
TEST=Temporarily set TXE to be disabled. Noted FUNC_DIS was being
set accordingly.
Change-Id: Ibf537bf8ba718859591dc89bdf41e57c1ea9d836
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175490
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This is an example consumer of the register script handler.
BUG=chrome-os-partner:23507
BRANCH=rambi
TEST=build and boot on rambi and see recovery screen
Change-Id: I4954a5defd0a345b179819b9f6bb15ea340a6715
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175214
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
This is based on the RCBA configuration setup from haswell.
It handles PCI, BARs, IO, MMIO, and baytrail-specific IOSF.
I did not extend it to handle MSR yet but that would be another
potential register type.
There are a number of approaches to this kind of thing, but in the
end they have a lot of switch statements and a mass of #defines.
I'm not particularly set on any of the details so comments welcome.
BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=emerge-rambi chromeos-coreboot-rambi
Change-Id: Ib873936ecf20fc996a8feeb72b9d04ddb523211f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175206
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
The same sequence is used regardless of the port
being read or written. Therefore, use the same
implementation for reading or writing to a port.
BUG=None
BRANCH=None
TEST=Built and booted through depthcharge. Dev and recovery
screens still work. Nothing bizarre in console output.
Change-Id: I1a64b54b50472fa7d601e199653eb4a76accf910
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175441
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The low power subsystem devices have a lot of their
configuration done in the IOSF sideband message space.
Add support for these access methods.
BUG=chrome-os-partner:23790
BRANCH=None
TEST=Built and booted through depthcharge.
Change-Id: I0dd52b952a16ef1280c29301164db041ee87f636
Signed-off-by: Aaron Durbin <adurbin@chromum.org>
Reviewed-on: https://chromium-review.googlesource.com/175440
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
BUG=chromium:285940
TEST=none
Change-Id: I90ee8999ed8b5234b622ea02bfe580068aaff01e
Reviewed-on: https://chromium-review.googlesource.com/175327
Reviewed-by: Mike Frysinger <vapier@chromium.org>
Commit-Queue: David James <davidjames@chromium.org>
Tested-by: David James <davidjames@chromium.org>
BUG=None
TEST=Builds and boots
BRANCH=None
Change-Id: I59209fe23cd74fbe74ef3f8de771e6a4cff7ab31
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/175270
Tested-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
BUG=None
TEST=builds
BRANCH=None
Change-Id: I163730e45cc18f125e32a1b4c5a685b3a1861486
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/175220
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The elog boot counter in cmos was not being initialized
nor incremented. Start doing that in romstage. Since S3
resume is not detected yet the increment is unconditional.
BUG=None
BRANCH=None
TEST=Built and booted through depthcharge multiple times. Noted
output such as 'Boot Count incremented to 4'.
Change-Id: Ic585d4ad4b3af086e0067e28fe0f35c02979bbd2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174717
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The ACPI code was previously complaining about not being able
to find the GNVS area: 'ACPI: Could not find CBMEM GNVS'. Fix
this by adding GNVS area early in start up. This is also the
appropriate place to set the acpi_slp_type variable to indicate
an S3 resume or not.
BUG=chrome-os-partner:22867
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted through depthcharge. Noted cbmem has 'ACPI GNVS'
entry.
Change-Id: Ifbca3dd390ebe573730ee204ca4c2f19626dd6b1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174647
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The callers of the following functions assume the storage
area provided by the pointers is initialized. That's not the
case as these were just place holders.
- void acpi_create_intel_hpet(acpi_hpet_t * hpet);
- void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
To fix this properly initialize the hpet entry, and just remove
the serialio_ssdt function entirely.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted through depthcharge on rambi. Noted no more
ACPI errors relating to invalid length.
Change-Id: If56ab033562ef2d755e9c9de42f507c95d291aba
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174716
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The EC LPC init function needs to run to enable the internal keyboard.
I needed this to confirm that it is just USB keyboards that are causing
all sorts of issues.
BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=boot to recovery screen and hit tab
Change-Id: Iea0fc66ba62ea7da71ef83c26e25ae32bef102bd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175207
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is essentially a direct port of CL:174505. It sets the EHCI
controllers Tx FIFO threshold setting to the recommended value for HOST
mode, which seems to help prevent FIFO underruns between the memory/AHB
and the host controller. This is necessary to get larger OUT transfers
to work, but there are still a few more general clock changes
concerning other AHB problems needed before they will really be usable.
BUG=None
TEST=None
Change-Id: I12783ba0a986678715d42e3d798756fa3d1ad690
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175200
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Enable first SATA port in Rambi device tree.
BUG=chrome-os-partner:23643
TEST=TEST=Manual, in dev mode. Verify on rambi that SATA disk is
detected, and kernel is found + booted.
Change-Id: Ic0cb5f9ff17ca0f6cc7941f203b9338df200811d
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174916
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add SATA driver for baytrail platform.
BUG=chrome-os-partner:23643
TEST=Manual, in dev mode. Verify on rambi that SATA disk is detected, and
kernel is found + booted.
Change-Id: I5c13e03203c8f26d233c7d10af8ff6812c460578
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174914
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Right now, firmware changes are rejected if the HWTest or VMTest
stages fail. This is unnecessary as firmware changes are very unlikely
to break these stages.
BUG=chromium:285940
TEST=Run it with my CL to ignore HWTest and VMTest
Change-Id: I4910b45df4c0a53f7d198f8f48454921d0198d7f
Reviewed-on: https://chromium-review.googlesource.com/175016
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aviv Keshet <akeshet@chromium.org>
Reviewed-by: Scott Zawalski <scottz@chromium.org>
Commit-Queue: David James <davidjames@chromium.org>
Tested-by: David James <davidjames@chromium.org>
Reviewed-by: Matt Tennant <mtennant@chromium.org>
This configuration change enables the running of reference code for
bayleybay.
BUG=chrome-os-partner:22580
BRANCH=None
TEST=manual
. built and noted output of reference code debug information. The
eMMC device driver (not yet in the code base) is working reliably
after several reboots and power cycles, indicating that the PLL
initialization code is kicking in.
Change-Id: I426baa46a72a567f54a00dc00321ee4227531eff
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175077
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the on-board devices in the SoC to the device tree.
Also, disable the unused devices aside from TXE and HDA.
Those particular devices cause the system to shut down
when they are disabled.
BUG=chrome-os-partner:22871
BRANCH=None
TEST=Built and booted through depthcharge. Noted the calls to the
southcluster disable function.
Change-Id: I482c1c9609833054aeb2948144af54b57d3df086
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174645
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
When the southcluster pci devices are listed in the devicetree add
the ability to perform the proper disabling seqence for turning
off devices. This only turns off the pci device interface as well
as put the device into D3Hot. It is not yet know how to put the TXE
device into D3Hot so it's currently not possible to disable that
device.
Also, expose the southcluster_enable_dev() function so that other
devices can call this if they require doing specific things before
disabling the device. The southcluster_enable_dev() is only called
on devices found in the devicetree and if they currently have no
ops associated with them.
BUG=chrome-os-partner:22871
BRANCH=None
TEST=Built and booted through depthcharge. Interrogated
output to ensure devices were being properly disabled.
Change-Id: I537ddcb9379907af2fe012948542b6150a8bf7c5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174644
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The dump_td() debug function in the EHCI stack incorrectly masks the
amount of transferred bytes on output... the actual field is 15 bits
wide (30:16). Let's just use the mask constant we already have for all
the other code.
BUG=None
TEST=None
Change-Id: I28c6f0ec75cc613e38d53b670645d19bf9ffe1b9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174986
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
There is nothing attached to these devices so we can disable
them as well as the function 0 DMA controller.
Also remove the EC SMI/SCI mappings since there is no EC.
(panther port of Iedfe711058676f7ee118b0b66ab0f8a1e792ea87)
BUG=chrome-os-partner:23563
TEST=none
BRANCH=panther
Change-Id: Ie66f9b66744db98f8638495c05f3a075b6fa6db9
Reviewed-on: https://chromium-review.googlesource.com/174944
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@chromium.org>
Tested-by: Mohammed Habibulla <moch@chromium.org>
Fan is attached to port 2 instead of 3.
(panther port of I9878063a24b0b908c74522580f776a4ce7d03d75)
BUG=chrome-os-partner:23563
TEST=none
BRANCH=panther
Change-Id: I028e0e5a748fa0a20d34e27e870e14ed8c75e4d1
Reviewed-on: https://chromium-review.googlesource.com/174984
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@chromium.org>
Tested-by: Mohammed Habibulla <moch@chromium.org>
Before I start moving things around I'm just cleaning house.
I'm so used to graphics exploding that I like to take it easy.
BUG=None
TEST=builds and boots to linux, with a dev screen on the way
BRANCH=None
Change-Id: I195520aa02ea82adf9e1d2befddc0528f5d15978
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/174995
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Add in register defines for PLLDP (I assume the display port PLL)
and SOR source 1 and 2 registers.
BUG=None
TEST=builds and boots to Linux
BRANCH=None
Change-Id: Ie629f81529f33a2d9be4b4e590ceca8cd3e9327b
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/174948
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
This patch adds the required bits and pieces to get USB set up correctly
for EHCI controllers with UTMI+ PHYs.
BUG=None
TEST=None
Change-Id: I89406ffa25fa96778965f8f1572fad8a74f10844
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174651
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
FixedIO seems like a nice short version of IO but in reality
it is limited to 10-bit ISA addresses and so should not really
be used in most situations.
Change all the references to use IO() directly instead.
BUG=chromium:311294
BRANCH=none
TEST=emerge-samus chromeos-coreboot-samus and check for iasl
warnings using updated iasl compiler revision 20130117.
Boot the imge and ensure that EC regions are still exported
in /proc/ioports.
Change-Id: I54de65892bed9e43dbba916990cf2b70c370843c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174810
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
