When cbfs debug is enabled, compilation fails because one of the debug
messages is using an non-existing variable.
BRANCH=nonr
BUG=None
TEST=compiling with CONFIG_DEBUG_CBFS enabled does not fail anymore.
Change-Id: Ic83f5e96cdcb5275ec0b7fadbc901e254a1002ca
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In able to do earlyprintk spew on LP0 resume, the kernel needs to
know the board UART. ODMDATA (in bct/odmdata.cfg) contains this info,
and the kernel looks for it in PMC_SCRATCH20. Fetch the ODMDATA word
from the BCT copy stored in IRAM by the BootROM.
BUG=chrome-os-partner:32015
BRANCH=none
TEST=Built for Rush and Ryu OK. Dumped PMC_SCRATCH20 in TegraShell
on Rush and confirmed value is what's in odmdata.cfg.
Change-Id: I63f33558ee8b00bd6c1e313efcd531e1d5fc67eb
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/222402
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch does some general cleanup in the Rockchip clock code, and
adds some more assertions regarding the PLL VCO and output frequency
ranges. It changes all PLL divisors to use the lowest values that can
still hit the target frequency, since higher NR values lead to higher
jitter and higher NO values increase power draw.
Also change DDR3 frequency code to hardcode the optimal divisors for
certail frequencies. As a little hack we will interpret 666000000 to
actually mean 666666666.6P (and analogous for 533MHz), since that's what
you usually want for memory.
BUG=chrome-os-partner:32139
TEST=Boot on veyron_pinky rev2, check that dpll_is shown as 666666666 in
/sys/kernel/debug/clk/clk_summary.
Change-Id: I4f3c39641955a95c6dfbe9334035eb670b138bf0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221801
This change re-writes the spi_xfer() function to support full-duplex
transfers.
Even though the code looks much different, the same basic algorithm
for setting up the transfer is used. The main difference is that
reads from rxdr and writes to txdr occur simultaneously and accounting
is more complicated, so I separated the higher-level accounting
portion from the low-level FIFO handling portion to simplify things.
BUG=chrome-os-partner:31850
BRANCH=none
TEST=Loaded content from SPI ROM fine, needs testing w/ EC
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I33d2f5179360baf94627c86b57d12f032897caf5
Reviewed-on: https://chromium-review.googlesource.com/218881
Reviewed-by: Julius Werner <jwerner@chromium.org>
Fix the typo of sate to state and add uKernel phase to just
output the current state byte.
BUG=chrome-os-partner:28234
BRANCH=samus,auron
TEST=build and boot on samus
Change-Id: I520a4cc75faffa5feeb6113ffd7b07a48c4e6f28
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222677
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The first 64 bytes of the framebuffer contain garbage after running
the option rom and after calling the VBE mode set with the flag to
clear the framebuffer.
Work around this issue by clearing the first 64 bytes in the framebuffer
in the broadwell graphics setup code after it executes the VBIOS.
BUG=chrome-os-partner:32771
BRANCH=samus,auron
TEST=build and boot on samus in dev mode, check for graphical corruption
Change-Id: I072bc913f7daea16e4861a7549e1b4ec85cde4cd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222676
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
BUG=chrome-os-partner:31424
TEST=Build a image and run on Samus proto boards to confirm if the
settings are applied correctly.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: I8138507506771148420a585fd12897a3bfe91916
Reviewed-on: https://chromium-review.googlesource.com/221387
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
CQ-DEPEND=CL:218766
BUG=none
BRANCH=none
TEST=built and booted on Pinky
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Icbee95350949bd9bfa4490a8a4b6bbf09beb4170
Reviewed-on: https://chromium-review.googlesource.com/221019
Reviewed-by: Julius Werner <jwerner@chromium.org>
Enable L1 Sub-State when both root port and endpoint support it.
BUG=chrome-os-partner:31424
TEST=Build a image and run on Samus proto boards to check if the
settings are applied correctly. I just only have proto boars and
need someone having EVT boards to confirm the settings.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: Id1b5a52ff0b896f4531c4a6e68e70a2cea8c736a
Reviewed-on: https://chromium-review.googlesource.com/221436
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
according to schematic, GPIO29 needs to output high to enable M.2
socket power
BUG=none
BRANCH=none
TEST=build ok and see wifi device on M.2 socket working in OS
Change-Id: I7f122541a7bf3a5d7872f37a866ea3f1e52e8b47
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/221927
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
this adds a flash vbnv driver for vboot to store non-volatile data in a flash
storage.
BUG=chrome-os-partner:32774
BRANCH=none
TEST=Built samus, veyron pinky, and cosmos
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: If5fc1b779722528134ad283fa030f150b3bab55f
Reviewed-on: https://chromium-review.googlesource.com/222258
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
There's no need to reserve the framebuffer within corebot. If the
payloads need a framebuffer they can allocate one themselves.
BUG=chrome-os-partner:31355
BRANCH=None
TEST=Built and booted on ryu.
Change-Id: I8d8b159e7fdd877e392193c5474a7518e9b3ad21
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221726
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
DDI-A should not need re-enabled in the resume path, just
the resume path when we did not execute VBIOS.
BUG=chrome-os-partner:28234
BRANCH=samus,auron
TEST=build and boot on samus, test suspend+resume
Change-Id: Iaf7d083c5c92c42b7a117e2d2c9546ada6bf5f76
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221988
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is the latest available microcode.
BUG=chrome-os-partner:28234
BRANCH=samus,auron
TEST=build and boot on samus
Change-Id: I3fdc93d834a43c97cf6f404f0f465902781ad9e4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221987
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds some simple constants to more easily write and do math
with frequencies, analogous to the existing KiB, MiB and GiB constants
for sizes. They are exemplary added to the Veyron_Pinky/Rk3288 code for
now and will hopefully be adopted by other parts of the codebase in the
future.
BUG=None
TEST=Compiled Veyron_Pinky.
Change-Id: I4a1927fd423eb96d3f76f7e44b451192038b02e0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221800
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This reverts commit 36960019dc.
Change-Id: Ie347622774bd9343face4890da2f65e8b29f4fb7
Reviewed-on: https://chromium-review.googlesource.com/221944
Reviewed-by: Michael Spang <spang@chromium.org>
Commit-Queue: Michael Spang <spang@chromium.org>
Tested-by: Michael Spang <spang@chromium.org>
Provide a weak implemenation of usb_setup_utmip function for those stages that
do not include usb.c.
BUG=chrome-os-partner:32684
BRANCH=None
TEST=Compiles successfully
Change-Id: Ib235cf039a17204ef7e06d545a3c86b75aff5b4c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/221575
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
This function needs to be available in different LOGLEVELs.
BUG=chrome-os-partner:28234
BRANCH=samus
TEST=USE=quiet-cb emerge-samus coreboot
Change-Id: Ia8f0d05af24c9070c8c9241a3a7e137f845d1cab
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221540
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is the specific codec setup platform data for samus.
BUG=chrome-os-partner:29649
BRANCH=samus
TEST=emerge-samus coreboot
Change-Id: I5e2a8fad58bb8a3d02ccece0b1f6fe52f56c94ea
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221539
Reviewed-by: Ben Zhang <benzh@chromium.org>
If secure monitor is used, rmodules support should be compiled in as well.
BUG=None
BRANCH=None
TEST=Compiles and boots to kernel prompt
Change-Id: Id1e33fd500d52cfa03a946bf7dd85e6a90f3360e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/221574
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
A higher drive setting is used for fast link training, once the
link training succeeds, a known-good drive setting will be used
for the main stream transactions.
For full link training sequence, the sink devices may ask for a
preferred drive setting, thus this drive setting should be used
for the main stream transactions too.
BUG=chrome-os-partner:32129
TEST=all panels on blaze/big devices work fine.
Change-Id: Icc540650dc1329af07fd9ee4661eb7fad435fde4
Signed-off-by: Neil Chen <neilc@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/219544
Reviewed-by: Julius Werner <jwerner@chromium.org>
The original dp driver supports only fast link training and a
special drive setting is used for the link training sequence.
This might not be accepted by all panels. The better way is to
go through full link training sequence to negotiate for a best
drive setting.
With the change, dp driver will try fast link training first,
this is same as before. If it fails in fast link training, will
try full link training.
BUG=chrome-os-partner:32129
TEST=all panels on blaze/big devices work fine.
Change-Id: I6f3402c4c5993a156c965c7f52b011d336a2946f
Signed-off-by: Neil Chen <neilc@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/219543
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
rockchip_spi_slave has a fifo_size member which doesn't change.
This just replaces the struct member with a #define.
BUG=none
BRANCH=none
TEST=built and booted on Pinky
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I9ea5cdad49ee10c5f32304d0909c4a7e74a261f9
Reviewed-on: https://chromium-review.googlesource.com/220471
Reviewed-by: Julius Werner <jwerner@chromium.org>
This re-factors rockchip_spi to remove speed_hz which will instead be
passed in via rockchip_spi_init(), thus making it easier to support
other boards which may have different slave devices attached.
BUG=none
BRANCH=none
TEST=built and booted on Pinky
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I7baf0fa0a2660e3c975847fdec3eb92bcd0d6c10
Reviewed-on: https://chromium-review.googlesource.com/220411
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch moves init for I2C, SPI, ChromeOS GPIOs to the
board-specific bootblock init function on Pinky, the idea being
to isolate SoC code so that it's more readily adaptable for
different boards.
BUG=none
BRANCH=none
TEST=built and booted on Pinky
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I75516bbd332915c1f61249844e18415b4e23c520
Reviewed-on: https://chromium-review.googlesource.com/220410
Reviewed-by: Julius Werner <jwerner@chromium.org>
Since the UART which is used for the serial console may change from
board-to-board, this moves CONSOLE_SERIAL_UART_ADDRESS from rk3288's
Kconfig into Pinky's Kconfig.
BUG=none
BRANCH=none
TEST=built and booted on pinky
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I29837a72d8cf205a144494a6c8ce350465118b34
Reviewed-on: https://chromium-review.googlesource.com/221438
Reviewed-by: Julius Werner <jwerner@chromium.org>
Turns out making the compilation of every single source file depend on
the auto-generated build.h in CL:219170 wasn't really such a great idea
for incremental builds. Who would've thought.
However, it's still undesirable that individual Makefiles for sources
that actually include build.h need to add that dependency manually.
Therefore, this patch fixes the issue by using $(generic-deps) as an
order-only prerequisites in rules. This kind of prerequisite is still
made before the target if it doesn't exist, but it is not automatically
updated based on the timestamp. Also removed some additional manual
build.h dependencies that I must somehow overlooked in the old patch.
The files that actually include build.h still get it as a normal
prerequisite through the automatic dependency rule in <filename>.d that
is created by GCC's -MMD option. $(generic-deps) only solves the
chicken-and-egg problem of where build.h comes from in fresh/cleaned
build directories that don't have any .d dependency files yet.
BUG=chrome-os-partner:32622
TEST=Manually did an incremental build with a single changed file.
Confirmed that actual build.h dependencies (id.bootblock.o, console.*.o)
were still remade, but not all other coreboot sources.
Change-Id: I5a830aae6b17dd7d4061a577fd2410b678d6f1f0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221470
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A branch instruction in a branch delay slot confuses the execution
pipeline and causes an exception.
bootblock.S was written 'by hand', has a branch instruction in branch
delay slot and includes '.set noreorder' directive, which causes it to
crash when trying to branch to main().
Adding a nop instruction fixes the problem. Also adding a nop after
the last branch in the file just in case main() returns and the object
linked next starts with a branch.
BUG=chrome-os-partner:31438
TEST=Running on the simulator can reach main() now
Change-Id: I0882b2eb5ce426f5a311018ffbb6f37a2ca64d98
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221421
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch creates a new mechanism to define the static memory layout
(primarily in SRAM) for a given board, superseding the brittle mass of
Kconfigs that we were using before. The core part is a memlayout.ld file
in the mainboard directory (although boards are expected to just include
the SoC default in most cases), which is the primary linker script for
all stages (though not rmodules for now). It uses preprocessor macros
from <memlayout.h> to form a different valid linker script for all
stages while looking like a declarative, boilerplate-free map of memory
addresses to the programmer. Linker asserts will automatically guarantee
that the defined regions cannot overlap. Stages are defined with a
maximum size that will be enforced by the linker. The file serves to
both define and document the memory layout, so that the documentation
cannot go missing or out of date.
The mechanism is implemented for all boards in the ARM, ARM64 and MIPS
architectures, and should be extended onto all systems using SRAM in the
future. The CAR/XIP environment on x86 has very different requirements
and the layout is generally not as static, so it will stay like it is
and be unaffected by this patch (save for aligning some symbol names for
consistency and sharing the new common ramstage linker script include).
BUG=None
TEST=Booted normally and in recovery mode, checked suspend/resume and
the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and
Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies
with ToT and looked for red flags.
Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213370
The ARM SMP feature was added a long time ago and has never really been
used by anyone since. We are still always compiling cpu_info() even
though we don't use it, and it makes some dangerous assumptions about
stack alignment that are not guaranteed anywhere.
I'm planning to change the way the stack boundaries are defined. Rather
than trying to work that into this unsafe, unused and hard to test
feature, I think we should just seal it off with police tape and make
sure that if anyone ever tries to use it again (which currently seems
unlikely), they get forced to do their due diligence on making sure it
works as intended.
BUG=None
TEST=Compiled Veyron_Pinky.
Change-Id: I8a60bd30e8b27a22bb3da68ca84daea99424dee9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219680
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The codec interrupt needs to be active high because multiple
interrupt sources share this line:
1) Headphone plug detect
2) Mic present
3) Hotword detect
These interrupt sources are OR-ed together.
BUG=chrome-os-partner:29649
BRANCH=samus
TEST=Jack detection works on samus
Change-Id: Ief0a291d9455f2d03789198153781ff8133aa1ce
Signed-off-by: Ben Zhang <benzh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220588
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
BUG=chrome-os-partner:31424,chromeos-os-partner:32380
TEST=Build a BIOS image and check the value is applied correctly.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: I0adda3643776b259a635a021babd983090f1df43
Reviewed-on: https://chromium-review.googlesource.com/220475
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Need END tag, "REG_SCRIPT_END", to indicate the end of smbus_init_script.
BUG=chromium:416651
TEST=test on Auron.
Change-Id: I1f5624f4c6ce7f0e8ceb8971aaa595d99e9ff82e
Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/220934
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Kenji Chen <kenji.chen@intel.com>
BUG=chrome-os-partner:31424
BRANCH=none
TEST=build only, due to I don't have broadwell system with wifi to test
need somebody help me to verify
Change-Id: I52360176e135ea7f01cc67a926be4870265f57d1
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/220743
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Set PCIE "Enable Clock Power Management", if endp supports
BUG=chrome-os-partner:31424
BRANCH=none
TEST=build and boot on rambi, check Enable Clock Power Management
in link control register is set properly
Change-Id: Ie54110d1ef42184cfcf47c9fe4d735960aebe47f
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/220742
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch adds the macros __ROMSTAGE__ and __RAMSTAGE__ which get
predefined in their respective stages by make, so that we have one
specific macro for every stage. It also renames __BOOT_BLOCK__ and
__VER_STAGE__ to __BOOTBLOCK__ and __VERSTAGE__ for consistency.
This change is intended to provided finer control and clearer
communication of intent after we added a new (optional) stage that falls
under __PRE_RAM__, and will hopefully provide some robustness for the
future (we don't want to end up always checking for romstage with #if
defined(__PRE_RAM__) && !defined(__BOOT_BLOCK__) &&
!defined(__VER_STAGE__) && !defined(__YET_ANOTHER_PRERAM_STAGE__)). The
__PRE_RAM__ macro stays as it is since many features do in fact need to
differentiate on whether RAM is available. (Some also depend on whether
RAM is available at the end of a stage, in which case #if
!defined(__PRE_RAM__) || defined(__ROMSTAGE__) should now be
authoritative.)
It's unfeasable to change all existing occurences of __PRE_RAM__ that
would be better described with __ROMSTAGE__, so this patch only
demonstratively changes a few obvious ones in core code.
BUG=None
TEST=None (tested together with dependent patch).
Change-Id: I6a1f25f7077328a8b5201a79b18fc4c2e22d0b06
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219172
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It's an unfortunate side effect of our different-archs-per-stage
mechanism that all src/arch/*/Kconfig files are always parsed with no
if blocks to exclude them if they're not relevant. This makes it very
easy to accidentally rely on a Kconfig default set by a totally
different and not applying architecture.
This patch moves a few Kconfigs from ARM and X86 that leaked out like
this into a common Kconfig file for clarity. It also removes the
never-used and never-working BOOTBLOCK_NORMAL mechanism from ARM, and
gave ARM64 its own BOOTBLOCK_CUSTOM mechanism so that it doesn't leech
off the ARM one (currently not used by any board).
In the future, we should maybe prefix all options in the arch/*/Kconfig
files with the architecture name (such as X86_BOOTBLOCK_NORMAL and
ARM_LPAE are already doing), to make it more apparent when they are used
in the wrong place.
BUG=None
TEST=None (tested together with dependent changes)
Change-Id: Ieb2d79bae6c6800be0f93ca3489b658008b1dfae
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219171
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch started out as an attempt to run linker scripts through the
preprocessor. However, since that required some more infrastructure
changes, the build system is so intertwined, and there are so many other
small issues that turned up and are easier to fix (and get running, and
test thoroughly) in a single go, it turned out a little bigger. In order
of appearance, it:
- wraps direct linker invocations in a macro to avoid the widespread
ifeq($(CONFIG_COMPILER_LLVM_CLANG),y) duplication.
- introduces an $(generic-deps) (equivalent to $(<class>-deps)) variable
for targets that all files depend on
- makes the $(src-to-obj) function usable in multiple places as the
authoritative way to get an output file name (even if the respective
source file is also under build/), and makes it preserve extensions on
everything except %.c and %.S (e.g. %.ld and %.asl)
- replaces the old $(<class>-postprocess) with a single
$(postprocessors) variable. The old ramstage-postprocess was weird
because it contained unescaped $(eval ...)s, meaning it gets executed
as soon as the variable is first substituted (and the other
$(eval ...) in the toplevel Makefile does essentially nothing). The
new mechanism is just $(eval ...)ed directly after the recursive parse
with no further magic. Files can freely append their own (escaped)
content to it and access variables valid in the calling context (like
$(<class>-objs)) directly.
- enhances the existing $(<class>-<type>-ccopts) mechanism with
$(<class>-generic-ccopts) and $(generic-<type>-ccopts) to reduce
duplication.
- makes .ld a type that can be added like a normal class file, causing
it to be preprocessed with the correct #defines for the current class
(needed for a follow-up feature). Migrates all linker scripts to this
mechanism, which allows us to get rid of the weird $(ldoptions)
mechanism (Kconfigs are replaced by preprocessor and no longer need to
be defined as symbols).
- removes duplicate $(INCLUDES) from $(CFLAGS)
- repairs the crazy state of MIPS Makefiles, which seem to have been
copied together from X86 despite having absolutely nothing in common
with that architecture. They were using the same code to paste
assembly pieces and linker scripts together without really needing it
for anything, and even accidentally relied on a Kconfig default set
in the arch/x86 subdirectory (I wish I was kidding). Changed them to
work equivalent to the arm/arm64 Makefiles which are far closer
related (also being SRAM-based platforms).
- moves the x86-specifc $(OPTION_TABLES_H) into the x86 Makefile.inc and
fixes an rule that would've had an empty target if it wasn't defined
- removes the custom ldscript-gathering variables for x86 bootblock and
romstage. The Makefile simply combines all .ld files that have been
added to the respective class now.
- uses the normal class build system to replace some of the custom rules
for autogenerated bootblock/crt0 files on x86, and removes some
hardcoded flags by using the normal $(...-ccopts) variables.
- moves the handling of .asl files from the global Makefile.inc to x86.
Changed to reuse the generic template for the preprocessing and C
compilation steps.
- removed the extra <name>.o linking step before linking an rmodule for
modules that don't require special linker flags (most of them).
- removes the incorrect assumption that there was a global $(LDFLAGS)
from the SMM Makefile.inc (it was named $(LDFLAGFS in one place so it
couldn't have been all that important ;) ).
- allow -j flag for parallel builds to be properly passed through to
vboot child invocation by using special $(MAKE) variable.
BUG=None
TEST=Built for Falco, Nyan_Blaze, Stout, Rush_Ryu and Urara. Binary
diffed old and new coreboot.rom (and some manually uncompressed stages),
confirmed that images/stages are byte-for-byte identical except for some
embedded timestamps and commit hashes. (Addresses in Falco/Stout
ramstages shifting slightly due to different link order for ASL object
files within their directory. Some addresses in Urara ramstage .rodata
and some relocation entries in rmodules moved around due to linking them
in fewer steps.)
Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
