erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

pearlvalley: enable M.2 socket power for wlan

Browse source 
according to schematic, GPIO29 needs to output high to enable M.2
socket power

BUG=none
BRANCH=none
TEST=build ok and see wifi device on M.2 socket working in OS

Change-Id: I7f122541a7bf3a5d7872f37a866ea3f1e52e8b47
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/221927
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Kane Chen 2014-10-08 17:23:09 +08:00 • committed by chrome-internal-fetch
commit f7dc2a0772
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/mainboard/intel/pearlvalley/gpio.h
View file

@ -52,7 +52,7 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_IRQ_EDGE, /* 26: NFC_IRQ_MGP5 */
PCH_GPIO_ACPI_SCI, /* 27: SMC_WAKE_SCI_N */
PCH_GPIO_OUT_LOW, /* 28: PCH_NFC_RESET */
PCH_GPIO_NATIVE, /* 29: PCH_SLP_WLAN_N */
PCH_GPIO_OUT_HIGH, /* 29: PCH_SLP_WLAN_N */
PCH_GPIO_NATIVE, /* 30: SUS_PWR_ACK_R */
PCH_GPIO_NATIVE, /* 31: AC_PRESENT_R */
PCH_GPIO_NATIVE, /* 32: PM_CKRUN_N */