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New mechanism to define SRAM/memory map with automatic bounds checking

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This patch creates a new mechanism to define the static memory layout
(primarily in SRAM) for a given board, superseding the brittle mass of
Kconfigs that we were using before. The core part is a memlayout.ld file
in the mainboard directory (although boards are expected to just include
the SoC default in most cases), which is the primary linker script for
all stages (though not rmodules for now). It uses preprocessor macros
from <memlayout.h> to form a different valid linker script for all
stages while looking like a declarative, boilerplate-free map of memory
addresses to the programmer. Linker asserts will automatically guarantee
that the defined regions cannot overlap. Stages are defined with a
maximum size that will be enforced by the linker. The file serves to
both define and document the memory layout, so that the documentation
cannot go missing or out of date.

The mechanism is implemented for all boards in the ARM, ARM64 and MIPS
architectures, and should be extended onto all systems using SRAM in the
future. The CAR/XIP environment on x86 has very different requirements
and the layout is generally not as static, so it will stay like it is
and be unaffected by this patch (save for aligning some symbol names for
consistency and sharing the new common ramstage linker script include).

BUG=None
TEST=Booted normally and in recovery mode, checked suspend/resume and
the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and
Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies
with ToT and looked for red flags.

Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213370
This commit is contained in:
Julius Werner 2014-08-20 15:29:56 -07:00 • committed by chrome-internal-fetch
commit f1e2028e7e
135 changed files with 1378 additions and 1781 deletions
Download patch file Download diff file Expand all files Collapse all files

5
Makefile.inc
View file

@ -352,6 +352,11 @@ tools: $(objutil)/kconfig/conf $(objutil)/cbfstool/cbfstool $(objutil)/cbfstool/
# Common recipes for all stages
###############################################################################
# loadaddr can determine the load address of a stage, which may be needed for
# platform-specific image headers (only works *after* the stage has been built)
loadaddr = $(shell $(OBJDUMP_$(1)) -p $(objcbfs)/$(1).debug | \
sed -ne '/LOAD/s/^.*vaddr 0x\([0-9a-fA-F]\{8\}\).*$$/0x\1/p')
# find-substr is required for stages like romstage_null and romstage_xip to
# eliminate the _* part of the string
find-substr = $(word 1,$(subst _, ,$(1)))

16
src/arch/arm/Makefile.inc
View file

@ -52,11 +52,9 @@ bootblock-y += memset.S
bootblock-y += memcpy.S
bootblock-y += memmove.S
bootblock-y += bootblock.ld
$(objcbfs)/bootblock.debug: $$(bootblock-objs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(call link,bootblock,$(filter %.a %.o,$(^)),-o $(@) -L$(obj) -T $(obj)/arch/arm/bootblock.bootblock.ld,--gc-sections)
$(call link,bootblock,$(filter %.a %.o,$(^)),-o $(@) -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld,--gc-sections)
endif # CONFIG_ARCH_BOOTBLOCK_ARM
@ -66,7 +64,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARM
$(objcbfs)/verstage.debug: $$(verstage-objs) $$(VB2_LIB)
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(call link,verstage,$(filter %.a %.o,$(^)),-o $(@) -L$(obj) -T $(obj)/arch/arm/verstage.verstage.ld,--gc-sections)
$(call link,verstage,$(filter %.a %.o,$(^)),-o $(@) -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld,--gc-sections)
verstage-$(CONFIG_EARLY_CONSOLE) += early_console.c
verstage-y += div0.c
@ -76,8 +74,6 @@ verstage-y += memcpy.S
verstage-y += memmove.S
verstage-y += stages.c
verstage-y += verstage.ld
###############################################################################
# romstage
###############################################################################
@ -99,13 +95,11 @@ rmodules_arm-y += memcpy.S
rmodules_arm-y += memmove.S
rmodules_arm-y += eabi_compat.c
romstage-y += romstage.ld
VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o
$(objcbfs)/romstage.debug: $$(romstage-objs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(call link,romstage,$(filter %.a %.o,$(^)),-o $(@) -L$(obj) -T $(obj)/arch/arm/romstage.romstage.ld,--gc-sections)
$(call link,romstage,$(filter %.a %.o,$(^)),-o $(@) -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld,--gc-sections)
endif # CONFIG_ARCH_ROMSTAGE_ARM
@ -126,8 +120,6 @@ ramstage-y += memcpy.S
ramstage-y += memmove.S
ramstage-y += clock.c
ramstage-y += ramstage.ld
rmodules_arm-y += memset.S
rmodules_arm-y += memcpy.S
rmodules_arm-y += memmove.S
@ -139,6 +131,6 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
$(objcbfs)/ramstage.debug: $$(ramstage-objs)
@printf " CC $(subst $(obj)/,,$(@))\n"
$(call link,ramstage,$(filter %.a %.o,$(^)),-o $(@) -L$(obj) -T $(obj)/arch/arm/ramstage.ramstage.ld,--gc-sections)
$(call link,ramstage,$(filter %.a %.o,$(^)),-o $(@) -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld,--gc-sections)
endif # CONFIG_ARCH_RAMSTAGE_ARM

20
src/arch/arm/armv4/bootblock.S
View file

@ -44,10 +44,8 @@ ENTRY(_start)
* Initialize the stack to a known value. This is used to check for
* stack overflow later in the boot process.
*/
ldr r0, .Stack
ldr r1, .Stack_size
sub r0, r0, r1
ldr r1, .Stack
ldr r0, =_stack
ldr r1, =_estack
ldr r2, =0xdeadbeef
init_stack_loop:
str r2, [r0]
@ -57,7 +55,7 @@ init_stack_loop:
/* Set stackpointer in internal RAM to call bootblock main() */
call_bootblock:
ldr sp, .Stack /* Set up stack pointer */
ldr sp, =_estack /* Set up stack pointer */
ldr r0,=0x00000000
/*
* The current design of cpu_info places the
@ -75,15 +73,3 @@ call_bootblock:
*/
bl main
ENDPROC(_start)
/* we do it this way because it's a 32-bit constant and
* in some cases too far away to be loaded as just an offset
* from IP
*/
.align 2
.Stack:
.word CONFIG_STACK_TOP
.align 2
/* create this size the same way we do in ramstage.ld: top-bottom */
.Stack_size:
.word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM

20
src/arch/arm/armv7/bootblock.S
View file

@ -62,10 +62,8 @@ ENTRY(_thumb_start)
* Initialize the stack to a known value. This is used to check for
* stack overflow later in the boot process.
*/
ldr r0, .Stack
ldr r1, .Stack_size
sub r0, r0, r1
ldr r1, .Stack
ldr r0, =_stack
ldr r1, =_estack
ldr r2, =0xdeadbeef
init_stack_loop:
str r2, [r0]
@ -75,7 +73,7 @@ init_stack_loop:
/* Set stackpointer in internal RAM to call bootblock main() */
call_bootblock:
ldr sp, .Stack /* Set up stack pointer */
ldr sp, =_estack /* Set up stack pointer */
ldr r0,=0x00000000
/*
* The current design of cpu_info places the struct at the top of the
@ -89,15 +87,3 @@ wait_for_interrupt:
wfi
mov pc, lr @ back to my caller
ENDPROC(_thumb_start)
/* we do it this way because it's a 32-bit constant and
* in some cases too far away to be loaded as just an offset
* from IP
*/
.align 2
.Stack:
.word CONFIG_STACK_TOP
.align 2
/* create this size the same way we do in ramstage.ld: top-bottom */
.Stack_size:
.word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM

5
src/arch/arm/armv7/mmu.c
View file

@ -31,6 +31,7 @@
#include <config.h>
#include <stdlib.h>
#include <stdint.h>
#include <symbols.h>
#include <cbmem.h>
#include <console/console.h>
@ -90,7 +91,7 @@ typedef uint32_t pmd_t;
static const unsigned int denom = 1;
#endif /* CONFIG_ARM_LPAE */
static pmd_t *const ttb_buff = (pmd_t *)CONFIG_TTB_BUFFER;
static pmd_t *const ttb_buff = (pmd_t *)_ttb;
/*
* mask/shift/size for pages and blocks
@ -186,7 +187,7 @@ void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
void mmu_init(void)
{
if (CONFIG_ARM_LPAE) {
pgd_t *const pgd_buff = (pgd_t*)(CONFIG_TTB_BUFFER + 16*KiB);
pgd_t *const pgd_buff = (pgd_t*)(_ttb + 16*KiB);
pmd_t *pmd = ttb_buff;
int i;

2
src/arch/arm/cpu.c
View file

@ -36,7 +36,7 @@ struct cpu_info *cpu_info(void)
{
#error "This is BROKEN! ARM stacks are currently not guaranteed to be " \
"STACK_SIZE-aligned in any way. If you ever plan to revive this " \
"feature, make sure you add the proper assertions " \
"feature, make sure you add the proper assertions to memlayout " \
"(and maybe consider revising the whole thing to work closer to what " \
"arm64 is doing now)."
uintptr_t addr = ALIGN((uintptr_t)__builtin_frame_address(0),

37
src/arch/arm/bootblock.ld → src/arch/arm/include/arch/header.ld
View file

@ -1,8 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2006 Advanced Micro Devices, Inc.
* Copyright (C) 2008-2010 coresystems GmbH
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -27,35 +26,9 @@ PHDRS
to_load PT_LOAD;
}
#ifdef __BOOTBLOCK__
ENTRY(_start)
TARGET(binary)
SECTIONS
{
. = CONFIG_BOOTBLOCK_BASE;
.bootblock . : {
*(.text._start);
KEEP(*(.id));
*(.text);
*(.text.*);
*(.rodata);
*(.rodata.*);
*(.data);
*(.data.*);
*(.bss);
*(.bss.*);
*(.sbss);
*(.sbss.*);
_end = .;
} : to_load = 0xff
preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE;
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
*(.ARM.*)
}
}
#else
ENTRY(stage_entry)
#endif

38
src/arch/arm/include/arch/memlayout.h Normal file
View file

@ -0,0 +1,38 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This file contains macro definitions for memlayout.ld linker scripts. */
#ifndef __ARCH_MEMLAYOUT_H
#define __ARCH_MEMLAYOUT_H
#define TTB(addr, size) \
REGION(ttb, addr, size, 16K) \
_ = ASSERT(size >= 16K + IS_ENABLED(CONFIG_ARM_LPAE) * 32, \
"TTB must be 16K (+ 32 for LPAE)!");
/* ARM stacks need 8-byte alignment and stay in one place through ramstage. */
#define STACK(addr, size) REGION(stack, addr, size, 8)
#define DMA_COHERENT(addr, size) \
REGION(dma_coherent, addr, size, (1 + IS_ENABLED(CONFIG_ARM_LPAE)) * 1M) \
_ = ASSERT(size % ((1 + IS_ENABLED(CONFIG_ARM_LPAE)) * 1M) == 0, \
"DMA coherency buffer must fit exactly in full superpages!");
#endif /* __ARCH_MEMLAYOUT_H */

2
src/arch/arm/include/arch/stages.h
View file

@ -22,7 +22,7 @@
extern void main(void);
void stage_entry(void) __attribute__((section(".text.stage_entry.arm")));
void stage_entry(void);
void stage_exit(void *);
void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size);

139
src/arch/arm/ramstage.ld
View file

@ -1,139 +0,0 @@
/*
* Memory map:
*
* CONFIG_RAMSTAGE_BASE : text segment
* : rodata segment
* : data segment
* : bss segment
* : stack
* : heap
*/
/*
* Bootstrap code for the STPC Consumer
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
*/
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
* 2005.12 yhlu add ramstage cross the vga font buffer handling
*/
/* We use ELF as output format. So that we can debug the code in some form. */
PHDRS
{
to_load PT_LOAD;
}
ENTRY(stage_entry)
SECTIONS
{
. = CONFIG_RAMSTAGE_BASE;
/* First we place the code and read only data (typically const declared).
* This could theoretically be placed in rom.
*/
.text : {
_text = .;
_start = .;
*(.text.stage_entry.arm);
*(.text);
*(.text.*);
. = ALIGN(16);
_etext = .;
} : to_load
.ctors : {
. = ALIGN(0x100);
__CTOR_LIST__ = .;
KEEP(*(.ctors));
LONG(0);
__CTOR_END__ = .;
}
.rodata : {
_rodata = .;
. = ALIGN(4);
console_drivers = .;
KEEP(*(.rodata.console_drivers));
econsole_drivers = . ;
. = ALIGN(4);
pci_drivers = . ;
KEEP(*(.rodata.pci_driver));
epci_drivers = . ;
cpu_drivers = . ;
KEEP(*(.rodata.cpu_driver));
ecpu_drivers = . ;
_bs_init_begin = .;
KEEP(*(.bs_init));
_bs_init_end = .;
*(.rodata)
*(.rodata.*)
/* kevinh/Ispiri - Added an align, because the objcopy tool
* incorrectly converts sections that are not long word aligned.
*/
. = ALIGN(4);
_erodata = .;
}
/* After the code we place initialized data (typically initialized
* global variables). This gets copied into ram by startup code.
* __data_start and __data_end shows where in ram this should be placed,
* whereas __data_loadstart and __data_loadend shows where in rom to
* copy from.
*/
.data : {
_data = .;
*(.data)
*(.data.*)
_edata = .;
}
/* bss does not contain data, it is just a space that should be zero
* initialized on startup. (typically uninitialized global variables)
* crt0.S fills between _bss and _ebss with zeroes.
*/
.bss . : {
_bss = .;
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
_ebss = .;
}
_end = .;
/* coreboot really "ends" here. Only heap and stack are placed after
* this line.
*/
.heap . : {
_heap = .;
/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
. = CONFIG_HEAP_SIZE ;
. = ALIGN(4);
_eheap = .;
}
/* The ram segment. This includes all memory used by the memory
* resident copy of coreboot, except the tables that are produced on
* the fly, but including stack and heap.
*/
_ram_seg = _text;
_eram_seg = _eheap;
/* The stack lives in SRAM in a different location, so keep
* it out of ram_seg
*/
_stack = CONFIG_STACK_BOTTOM;
_estack = CONFIG_STACK_TOP;
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.note.*)
}
}

79
src/arch/arm/romstage.ld
View file

@ -1,79 +0,0 @@
/*
* Memory map:
*
* CONFIG_ROMSTAGE_BASE : text segment
* : rodata segment
* : data segment
* : bss segment
* : stack
* : heap
*/
/*
* Bootstrap code for the STPC Consumer
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
*/
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
* 2005.12 yhlu add ramstage cross the vga font buffer handling
*/
/* We use ELF as output format. So that we can debug the code in some form. */
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
PHDRS
{
to_load PT_LOAD;
}
ENTRY(stage_entry)
SECTIONS
{
. = CONFIG_ROMSTAGE_BASE;
.romtext . : {
_start = .;
*(.text.stage_entry.arm);
*(.text.startup);
*(.text);
*(.text.*);
} : to_load
.romdata . : {
*(.rodata);
*(.rodata.*);
*(.data);
*(.data.*);
. = ALIGN(8);
}
/* bss does not contain data, it is just a space that should be zero
* initialized on startup. (typically uninitialized global variables)
* crt0.S fills between _bss and _ebss with zeroes.
*/
.bss . : {
. = ALIGN(8);
_bss = .;
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
_ebss = .;
}
_end = .;
preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE;
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
*(.eh_frame);
}
}

8
src/arch/arm/stages.c
View file

@ -22,10 +22,10 @@
* execution (bootblock entry and ramstage exit will depend on external
* loading).
*
* Entry points must be placed at the location the previous stage jumps
* to (the lowest address in the stage image). This is done by giving
* stage_entry() its own section in .text and placing it first in the
* linker script.
* Entry points should be set in the linker script and honored by CBFS,
* so text section layout shouldn't matter. Still, it doesn't hurt to put
* stage_entry first (which XXXstage.ld will do automatically through the
* .text.stage_entry section created by -ffunction-sections).
*/
#include <arch/stages.h>

67
src/arch/arm/verstage.ld
View file

@ -1,67 +0,0 @@
/*
* Memory map:
*
* CONFIG_VERSTAGE_BASE : text segment
* : rodata segment
* : data segment
* : bss segment
*/
/* We use ELF as output format. So that we can debug the code in some form. */
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
INCLUDE ldoptions
PHDRS
{
to_load PT_LOAD;
}
ENTRY(stage_entry)
SECTIONS
{
. = CONFIG_VERSTAGE_BASE;
.romtext . : {
_start = .;
*(.text.stage_entry.arm);
*(.text.startup);
*(.text);
*(.text.*);
} : to_load
.romdata . : {
*(.rodata);
*(.rodata.*);
*(.data);
*(.data.*);
. = ALIGN(8);
}
/* bss does not contain data, it is just a space that should be zero
* initialized on startup. (typically uninitialized global variables)
*/
.bss . : {
. = ALIGN(8);
_bss = .;
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
_ebss = .;
}
_end = .;
preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE;
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
*(.eh_frame);
}
}

12
src/arch/arm64/Makefile.inc
View file

@ -57,13 +57,11 @@ bootblock-y += ../../lib/memset.c
bootblock-y += ../../lib/memcpy.c
bootblock-y += ../../lib/memmove.c
bootblock-y += bootblock.ld
# Build the bootblock
$(objcbfs)/bootblock.debug: $$(bootblock-objs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(call link,bootblock,$(filter %.a %.o,$(^)),-o $(@) -L$(obj) -T $(obj)/arch/arm64/bootblock.bootblock.ld,--gc-sections)
$(call link,bootblock,$(filter %.a %.o,$(^)),-o $(@) -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld,--gc-sections)
endif # CONFIG_ARCH_BOOTBLOCK_ARM64
@ -85,8 +83,6 @@ romstage-y += ../../lib/memmove.c
romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
romstage-y += transition.c transition_asm.S
romstage-y += romstage.ld
rmodules_arm64-y += ../../lib/memset.c
rmodules_arm64-y += ../../lib/memcpy.c
rmodules_arm64-y += ../../lib/memmove.c
@ -98,7 +94,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm64/eabi_compat.rmodules_arm64.o
$(objcbfs)/romstage.debug: $$(romstage-objs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(call link,romstage,$(filter %.a %.o,$(^)),-o $(@) -L$(obj) -T $(obj)/arch/arm64/romstage.romstage.ld,--gc-sections)
$(call link,romstage,$(filter %.a %.o,$(^)),-o $(@) -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld,--gc-sections)
endif # CONFIG_ARCH_ROMSTAGE_ARM64
@ -123,8 +119,6 @@ ramstage-y += stage_entry.S
ramstage-$(CONFIG_ARCH_SPINTABLE) += spintable.c spintable_asm.S
ramstage-y += transition.c transition_asm.S
ramstage-y += ramstage.ld
rmodules_arm64-y += ../../lib/memset.c
rmodules_arm64-y += ../../lib/memcpy.c
rmodules_arm64-y += ../../lib/memmove.c
@ -143,6 +137,6 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
$(objcbfs)/ramstage.debug: $$(ramstage-objs)
@printf " CC $(subst $(obj)/,,$(@))\n"
$(call link,ramstage,$(filter %.a %.o,$(^)),-o $(@) -L$(obj) -T $(obj)/arch/arm64/ramstage.ramstage.ld,--gc-sections)
$(call link,ramstage,$(filter %.a %.o,$(^)),-o $(@) -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld,--gc-sections)
endif # CONFIG_ARCH_RAMSTAGE_ARM64

38
src/arch/arm64/bootblock.ld → src/arch/arm64/include/arch/header.ld
View file

@ -1,8 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2006 Advanced Micro Devices, Inc.
* Copyright (C) 2008-2010 coresystems GmbH
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -27,36 +26,7 @@ PHDRS
to_load PT_LOAD;
}
ENTRY(stage_entry)
#ifdef __BOOTBLOCK__
TARGET(binary)
SECTIONS
{
. = CONFIG_BOOTBLOCK_BASE;
.bootblock . : {
*(.text.stage_entry);
KEEP(*(.id));
*(.text);
*(.text.*);
*(.rodata);
*(.rodata.*);
*(.data);
*(.data.*);
*(.bss);
*(.bss.*);
*(.sbss);
*(.sbss.*);
} : to_load = 0xff
/* arm64 chipsets need to define CONFIG_BOOTBLOCK_STACK_(TOP|BOTTOM) */
_stack = CONFIG_BOOTBLOCK_STACK_BOTTOM;
_estack = CONFIG_BOOTBLOCK_STACK_TOP;
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
*(.ARM.*)
}
}
#endif
ENTRY(stage_entry)

35
src/arch/arm64/include/arch/memlayout.h Normal file
View file

@ -0,0 +1,35 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This file contains macro definitions for memlayout.ld linker scripts. */
#ifndef __ARCH_MEMLAYOUT_H
#define __ARCH_MEMLAYOUT_H
/* TODO: add SRAM TTB region and figure out the correct size/alignment for it */
/* ARM64 stacks need 16-byte alignment. The ramstage will set up its own stacks
* in BSS, so this is only used for the SRAM stages. */
#ifdef __PRE_RAM__
#define STACK(addr, size) REGION(stack, addr, size, 16)
#else
#define STACK(addr, size) REGION(preram_stack, addr, size, 16)
#endif
#endif /* __ARCH_MEMLAYOUT_H */

119
src/arch/arm64/ramstage.ld
View file

@ -1,119 +0,0 @@
/*
* Memory map:
*
* CONFIG_RAMBASE : text segment
* : rodata segment
* : data segment
* : bss segment
* : stack
* : heap
*/
/*
* Copyright 2013 Google Inc.
* Bootstrap code for the STPC Consumer
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
*/
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
* 2005.12 yhlu add ramstage cross the vga font buffer handling
*/
/* We use ELF as output format. So that we can debug the code in some form. */
ENTRY(stage_entry)
PHDRS
{
to_load PT_LOAD;
}
SECTIONS
{
. = CONFIG_RAMSTAGE_BASE;
.text : {
_text = .;
_start = .;
*(.text.stage_entry);
*(.text);
*(.text.*);
. = ALIGN(16);
_etext = .;
} : to_load
.ctors : {
. = ALIGN(0x100);
__CTOR_LIST__ = .;
KEEP(*(.ctors));
LONG(0);
LONG(0);
__CTOR_END__ = .;
}
.rodata : {
. = ALIGN(64);
_rodata = .;
console_drivers = .;
KEEP(*(.rodata.console_drivers));
econsole_drivers = . ;
. = ALIGN(64);
pci_drivers = . ;
KEEP(*(.rodata.pci_driver));
epci_drivers = . ;
cpu_drivers = . ;
KEEP(*(.rodata.cpu_driver));
ecpu_drivers = . ;
_bs_init_begin = .;
KEEP(*(.bs_init));
_bs_init_end = .;
. = ALIGN(64);
*(.rodata)
*(.rodata.*)
_erodata = .;
}
.data : {
. = ALIGN(64);
_data = .;
*(.data)
*(.data.*)
. = ALIGN(64);
_edata = .;
}
.bss : {
. = ALIGN(64);
_bss = .;
*(.bss)
*(.bss.*)
*(.sbss.*)
*(COMMON)
. = ALIGN(64);
_ebss = .;
}
.heap : {
_heap = .;
/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
. = . + CONFIG_HEAP_SIZE ;
. = ALIGN(64);
_eheap = .;
}
/* The ram segment. This includes all memory used by the memory
* resident copy of coreboot, except the tables that are produced on
* the fly, but including stack and heap.
*/
_ram_seg = _text;
_eram_seg = _eheap;
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.note.*)
}
}

87
src/arch/arm64/romstage.ld
View file

@ -1,87 +0,0 @@
/*
* Memory map:
*
* CONFIG_ROMSTAGE_BASE : text segment
* : rodata segment
* : data segment
* : bss segment
* : stack
* : heap
*/
/*
* Bootstrap code for the STPC Consumer
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
*/
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
* 2005.12 yhlu add ramstage cross the vga font buffer handling
*/
/* We use ELF as output format. So that we can debug the code in some form. */
OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
OUTPUT_ARCH(aarch64)
PHDRS
{
to_load PT_LOAD;
}
ENTRY(stage_entry)
SECTIONS
{
. = CONFIG_ROMSTAGE_BASE;
.romtext . : {
_start = .;
*(.text.stage_entry);
*(.text.startup);
*(.text);
*(.text.*);
} : to_load
.romdata . : {
*(.rodata);
*(.rodata.*);
*(.machine_param);
*(.data);
*(.data.*);
. = ALIGN(8);
_erom = .;
}
__image_copy_end = .;
/* bss does not contain data, it is just a space that should be zero
* initialized on startup. (typically uninitialized global variables)
* crt0.S fills between _bss and _ebss with zeroes.
*/
.bss . : {
. = ALIGN(8);
_bss = .;
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
_ebss = .;
}
_end = .;
/* arm64 chipsets need to define CONFIG_ROMSTAGE_STACK_(TOP|BOTTOM) */
_stack = CONFIG_ROMSTAGE_STACK_BOTTOM;
_estack = CONFIG_ROMSTAGE_STACK_TOP;
preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE;
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
*(.eh_frame);
}
}

12
src/arch/mips/Makefile.inc
View file

@ -43,8 +43,6 @@ bootblock-y += ../../lib/memcpy.c
bootblock-y += ../../lib/memmove.c
bootblock-y += ../../lib/memset.c
bootblock-y += bootblock.ld
# Much of the assembly code is generated by the compiler, and may contain
# terms which the preprocessor will happily go on to replace. For example
# "mips" would be replaced with "1". Clear all the built in definitions to
@ -53,7 +51,7 @@ bootblock-S-ccopts += -undef
$(objcbfs)/bootblock.debug: $$(bootblock-objs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(call link,bootblock,$(filter %.a %.o,$(^)),-o $(@) -L$(obj) -T $(obj)/arch/mips/bootblock.bootblock.ld,--gc-sections)
$(call link,bootblock,$(filter %.a %.o,$(^)),-o $(@) -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld,--gc-sections)
endif # CONFIG_ARCH_BOOTBLOCK_MIPS
@ -70,11 +68,9 @@ romstage-y += ../../lib/memcpy.c
romstage-y += ../../lib/memmove.c
romstage-y += ../../lib/memset.c
romstage-y += romstage.ld
$(objcbfs)/romstage.debug: $$(romstage-objs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(call link,romstage,$(filter %.a %.o,$(^)),-o $(@) -L$(obj) -T $(obj)/arch/mips/romstage.romstage.ld,--gc-sections)
$(call link,romstage,$(filter %.a %.o,$(^)),-o $(@) -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld,--gc-sections)
endif # CONFIG_ARCH_ROMSTAGE_MIPS
@ -92,12 +88,10 @@ ramstage-y += ../../lib/memcpy.c
ramstage-y += ../../lib/memmove.c
ramstage-y += ../../lib/memset.c
ramstage-y += ramstage.ld
ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
$(objcbfs)/ramstage.debug: $$(ramstage-objs)
@printf " CC $(subst $(obj)/,,$(@))\n"
$(call link,ramstage,$(filter %.a %.o,$(^)),-o $(@) -L$(obj) -T $(obj)/arch/mips/ramstage.ramstage.ld,--gc-sections)
$(call link,ramstage,$(filter %.a %.o,$(^)),-o $(@) -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld,--gc-sections)
endif # CONFIG_ARCH_RAMSTAGE_MIPS

6
src/arch/mips/bootblock.S
View file

@ -19,17 +19,17 @@
.set noreorder /* Prevent assembler from "optimizing" this code. */
.section ".start", "ax", %progbits
.section ".text._start", "ax", %progbits
.globl _start
_start:
/* Set the stack pointer */
li $sp, CONFIG_BOOTBLOCK_STACK_TOP
la $sp, _estack
/*
* Initialise the stack to a known value, used later to check for
* overflow.
*/
li $t0, CONFIG_BOOTBLOCK_STACK_BOTTOM
la $t0, _stack
addi $t1, $sp, -4
li $t2, 0xdeadbeef
1: sw $t2, 0($t0)

39
src/arch/mips/bootblock.ld → src/arch/mips/include/arch/header.ld
View file

@ -1,9 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2006 Advanced Micro Devices, Inc.
* Copyright (C) 2008-2010 coresystems GmbH
* Copyright (C) 2014 Imagination Technologies
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -19,39 +17,16 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* We use ELF as output format. So that we can debug the code in some form. */
OUTPUT_ARCH(mips)
ENTRY(_start)
PHDRS
{
to_load PT_LOAD;
}
preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE;
SECTIONS
{
. = CONFIG_BOOTBLOCK_BASE;
/* This section might be better named .setup */
.rom : {
_rom = .;
*(.start);
*(.id);
*(.text);
*(.text.*);
*(.rom.text);
*(.rom.data);
*(.rom.data.*);
*(.rodata.*);
_erom = .;
} : to_load = 0xff
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
}
}
#ifdef __BOOTBLOCK__
ENTRY(_start)
#else
ENTRY(stage_entry)
#endif

31
src/arch/mips/include/arch/memlayout.h Normal file
View file

@ -0,0 +1,31 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This file contains macro definitions for memlayout.ld linker scripts. */
#ifndef __ARCH_MEMLAYOUT_H
#define __ARCH_MEMLAYOUT_H
/* MIPS stacks need 8-byte alignment and stay in one place through ramstage. */
/* TODO: Double-check that that's the correct alignment for our ABI. */
#define STACK(addr, size) REGION(stack, addr, size, 8)
/* TODO: Need to add DMA_COHERENT region like on ARM? */
#endif /* __ARCH_MEMLAYOUT_H */

121
src/arch/mips/ramstage.ld
View file

@ -1,121 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* Based on src/arch/arm/ramstage.ld:
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
OUTPUT_ARCH(mips)
ENTRY(stage_entry)
PHDRS
{
to_load PT_LOAD;
}
SECTIONS
{
. = CONFIG_SYS_SDRAM_BASE;
.text : {
_text = .;
_start = .;
*(.text.stage_entry.mips);
*(.text);
*(.text.*);
. = ALIGN(16);
_etext = .;
} : to_load
.ctors : {
. = ALIGN(0x100);
__CTOR_LIST__ = .;
*(.ctors);
LONG(0);
__CTOR_END__ = .;
}
.rodata : {
_rodata = .;
. = ALIGN(4);
console_drivers = .;
KEEP(*(.rodata.console_drivers));
econsole_drivers = . ;
. = ALIGN(4);
pci_drivers = . ;
KEEP(*(.rodata.pci_driver));
epci_drivers = . ;
cpu_drivers = . ;
KEEP(*(.rodata.cpu_driver));
ecpu_drivers = . ;
_bs_init_begin = .;
KEEP(*(.bs_init));
_bs_init_end = .;
*(.rodata)
*(.rodata.*)
. = ALIGN(4);
_erodata = .;
}
.data : {
_data = .;
*(.data)
_edata = .;
}
/* bss will be cleared by cbfs_load_stage */
_bss = .;
.bss . : {
*(.bss)
*(.sbss)
*(COMMON)
}
_ebss = .;
_end = .;
/*
* coreboot from the perspective of the loader really "ends"
* here. Only symbols are placed after this.
*/
_heap = .;
_eheap = . + CONFIG_HEAP_SIZE;
_stack = CONFIG_STACK_BOTTOM;
_estack = CONFIG_STACK_TOP;
/*
* The ram segment. This includes all memory used by the memory
* resident copy of coreboot, except the tables that are produced on
* the fly, but including stack and heap.
*/
_ram_seg = _text;
_eram_seg = _eheap;
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.note.*)
}
}

72
src/arch/mips/romstage.ld
View file

@ -1,72 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Imagination Technologies
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
OUTPUT_ARCH(mips)
ENTRY(stage_entry)
PHDRS
{
to_load PT_LOAD;
}
preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE;
SECTIONS
{
. = CONFIG_ROMSTAGE_BASE;
.romtext . : {
_rom = .;
_start = .;
*(.text.stage_entry.mips);
*(.text.startup);
*(.text);
} : to_load
.romdata . : {
*(.rodata);
*(.data);
. = ALIGN(16);
_erom = .;
}
/* bss will be cleared by cbfs_load_stage */
.bss . : {
. = ALIGN(8);
_bss = .;
*(.bss)
*(.sbss)
*(COMMON)
}
_ebss = .;
_end = .;
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
*(.eh_frame);
}
}

2
src/arch/mips/stages.c
View file

@ -20,7 +20,7 @@
#include <arch/stages.h>
#include <arch/cache.h>
__attribute__((section(".text.stage_entry.mips"))) void stage_entry(void)
void stage_entry(void)
{
main();
}

6
src/arch/x86/boot/boot.c
View file

@ -2,6 +2,7 @@
#include <arch/stages.h>
#include <ip_checksum.h>
#include <string.h>
#include <symbols.h>
#include <cpu/x86/multiboot.h>
#if CONFIG_RELOCATABLE_RAMSTAGE
@ -29,11 +30,10 @@ void jmp_to_elf_entry(void *entry, unsigned long unused1, unsigned long unused2)
#else
void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size)
{
extern unsigned char _ram_seg, _eram_seg;
unsigned long lb_start, lb_size;
lb_start = (unsigned long)&_ram_seg;
lb_size = (unsigned long)(&_eram_seg - &_ram_seg);
lb_start = (unsigned long)&_program;
lb_size = _program_size;
printk(BIOS_SPEW, "entry = 0x%08lx\n", (unsigned long)entry);
printk(BIOS_SPEW, "lb_start = 0x%08lx\n", lb_start);

8
src/arch/x86/init/romstage.ld
View file

@ -56,13 +56,13 @@ SECTIONS
*(.car.global_data);
_car_data_end = .;
/* The preram cbmem console area comes last to take advantage
* of a zero-sized array to hold the memconsole contents that
* grows to a bound of CONFIG_CONSOLE_PRERAM_BUFFER_SIZE.
* of a zero-sized array to hold the memconsole contents.
* However, collisions within the cache-as-ram region cannot be
* statically checked because the cache-as-ram region usage is
* cpu/chipset dependent. */
preram_cbmem_console = .;
_preram_cbmem_console = .;
_epreram_cbmem_console = . + 0xc00;
}
_bogus = ASSERT((SIZEOF(.car.data) + CONFIG_CONSOLE_PRERAM_BUFFER_SIZE <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
_bogus = ASSERT((SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
}

2
src/arch/x86/lib/c_start.S
View file

@ -16,7 +16,7 @@ thread_stacks:
.space CONFIG_STACK_SIZE*CONFIG_NUM_THREADS
#endif
.section ".textfirst", "ax", @progbits
.section ".text._start", "ax", @progbits
.code32
.globl _start
.globl __rmodule_entry

118
src/arch/x86/ramstage.ld
View file

@ -8,123 +8,19 @@
* : stack
* : heap
*/
/*
* Bootstrap code for the STPC Consumer
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
*/
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
* 2005.12 yhlu add ramstage cross the vga font buffer handling
*/
/* We use ELF as output format. So that we can debug the code in some form. */
ENTRY(_start)
PHDRS
{
to_load PT_LOAD;
}
SECTIONS
{
. = CONFIG_RAMBASE;
/* First we place the code and read only data (typically const declared).
* This could theoretically be placed in rom.
*/
.text : {
_text = .;
*(.textfirst);
*(.text);
*(.text.*);
. = ALIGN(16);
_etext = .;
}
.ctors : {
. = ALIGN(0x100);
__CTOR_LIST__ = .;
*(.ctors);
LONG(0);
__CTOR_END__ = .;
}
INCLUDE "lib/ramstage.ramstage.ld"
.rodata : {
_rodata = .;
. = ALIGN(4);
/* If any changes are made to the driver start/symbols or the
* section names the equivalent changes need to made to
* rmodule.ld. */
console_drivers = .;
*(.rodata.console_drivers)
econsole_drivers = . ;
. = ALIGN(4);
pci_drivers = . ;
*(.rodata.pci_driver)
epci_drivers = . ;
cpu_drivers = . ;
*(.rodata.cpu_driver)
ecpu_drivers = . ;
_bs_init_begin = .;
*(.bs_init)
_bs_init_end = .;
*(.rodata)
*(.rodata.*)
/* kevinh/Ispiri - Added an align, because the objcopy tool
* incorrectly converts sections that are not long word aligned.
*/
. = ALIGN(4);
_erodata = .;
}
/* After the code we place initialized data (typically initialized
* global variables). This gets copied into ram by startup code.
* __data_start and __data_end shows where in ram this should be placed,
* whereas __data_loadstart and __data_loadend shows where in rom to
* copy from.
*/
.data : {
_data = .;
*(.data)
_edata = .;
}
/* bss does not contain data, it is just a space that should be zero
* initialized on startup. (typically uninitialized global variables)
* crt0.S fills between _bss and _ebss with zeroes.
*/
_bss = .;
.bss . : {
*(.bss)
*(.sbss)
*(COMMON)
}
_ebss = .;
_heap = .;
.heap . : {
/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
. = CONFIG_HEAP_SIZE ;
. = ALIGN(4);
}
_eheap = .;
/* The ram segment. This includes all memory used by the memory
* resident copy of coreboot, except the tables that are produced on
* the fly, but including stack and heap.
*/
_ram_seg = _text;
_eram_seg = _eheap;
/* CONFIG_RAMTOP is the upper address of cached memory (among other
* things). We must not exceed beyond that address, there be dragons.
*/
_bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.note.*)
}
_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
}

14
src/console/Kconfig
View file

@ -251,20 +251,6 @@ config CONSOLE_CBMEM_BUFFER_SIZE
value (64K or 0x10000 bytes) is large enough to accommodate
even the BIOS_SPEW level.
config CBMEM_CONSOLE_PRERAM_BASE
hex
depends on CONSOLE_CBMEM && CONSOLE_FIXED_PRERAM_CBMEM_BUFFER
config CONSOLE_PRERAM_BUFFER_SIZE
depends on CONSOLE_CBMEM
hex "Room allocated for console output before RAM is initialized"
default 0xc00
help
Console is used before RAM is initialized. This is the room reserved
in the DCACHE based RAM, SRAM, etc. to keep console output before it
can be saved in a CBMEM buffer. 3K bytes should be enough even for
the BIOS_SPEW level.
choice
prompt "Maximum console log level"

1
src/cpu/x86/lapic/lapic_cpu_init.c
View file

@ -25,6 +25,7 @@
#include <delay.h>
#include <lib.h>
#include <string.h>
#include <symbols.h>
#include <console/console.h>
#include <arch/hlt.h>
#include <device/device.h>

1
src/cpu/x86/mp_init.c
View file

@ -38,6 +38,7 @@
#include <lib.h>
#include <smp/atomic.h>
#include <smp/spinlock.h>
#include <symbols.h>
#include <thread.h>
#define MAX_APIC_IDS 256

4
src/cpu/x86/smm/smm.ld
View file

@ -10,6 +10,7 @@ SECTIONS
*/
. = 0xa0000;
.handler (.): {
_program = .;
/* Assembler stub */
*(.handler)
@ -31,9 +32,10 @@ SECTIONS
*(.bss)
*(.sbss)
/* What is this? */
/* What is this? (Something we don't need with -fno-common.) */
*(COMMON)
. = ALIGN(4);
_eprogram = .;
}
/* We are using the ASEG interleaved to stuff the SMM handlers

2
src/cpu/x86/smm/smm_tseg.ld
View file

@ -30,6 +30,7 @@ SECTIONS
/* 16KB for the heap at 64KB */
. = 0x10000;
.heap : {
_program = .;
_heap = .;
. = 0x4000;
_eheap = .;
@ -61,6 +62,7 @@ SECTIONS
. = ALIGN(4);
_smm_c_handler_end = .;
_eprogram = .;
}
/DISCARD/ : {

5
src/include/lib.h
View file

@ -45,11 +45,6 @@ int primitive_memtest(uintptr_t base, uintptr_t size);
/* Defined in src/lib/stack.c */
int checkstack(void *top_of_stack, int core);
#ifndef __PRE_RAM__ // fails in bootblock compiled with romcc
/* currently defined by a ldscript */
extern unsigned char _estack[];
#endif
/* Defined in romstage.c */
#if CONFIG_CPU_AMD_GEODE_LX
void cache_as_ram_main(void);

105
src/include/memlayout.h Normal file
View file

@ -0,0 +1,105 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This file contains macro definitions for memlayout.ld linker scripts. */
#ifndef __MEMLAYOUT_H
#define __MEMLAYOUT_H
#include <arch/memlayout.h>
#define STR(x) #x
#define SET_COUNTER(name, addr) \
_ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \
. = addr;
#define SYMBOL(name, addr) \
SET_COUNTER(name, addr) \
_##name = .;
#define REGION(name, addr, size, expected_align) \
SYMBOL(name, addr) \
_ = ASSERT(. == ALIGN(expected_align), \
STR(name must be aligned to expected_align!)); \
SYMBOL(e##name, addr + size)
/* Declare according to SRAM/DRAM ranges in SoC hardware-defined address map. */
#define SRAM_START(addr) SYMBOL(sram, addr)
#define SRAM_END(addr) SYMBOL(esram, addr)
#define DRAM_START(addr) SYMBOL(dram, addr)
#define PRERAM_CBMEM_CONSOLE(addr, size) \
REGION(preram_cbmem_console, addr, size, 4)
/* Use either CBFS_CACHE (unified) or both (PRERAM|POSTRAM)_CBFS_CACHE */
#define CBFS_CACHE(addr, size) REGION(cbfs_cache, addr, size, 4)
/* TODO: This only works if you never access CBFS in romstage before RAM is up!
* If you need to change that assumption, you have some work ahead of you... */
#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
#define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
#define POSTRAM_CBFS_CACHE(addr, size) \
REGION(unused_cbfs_cache, addr, size, 4)
#else
#define PRERAM_CBFS_CACHE(addr, size) \
REGION(unused_cbfs_cache, addr, size, 4)
#define POSTRAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size)
#endif
/* Careful: 'INCLUDE <filename>' must always be at the end of the output line */
#ifdef __BOOTBLOCK__
#define BOOTBLOCK(addr, sz) \
SET_COUNTER(bootblock, addr) \
_ = ASSERT(_ebootblock - _bootblock <= sz, \
STR(Bootblock exceeded its allotted size! (sz))); \
INCLUDE "lib/bootblock.bootblock.ld"
#else
#define BOOTBLOCK(addr, sz) \
SET_COUNTER(bootblock, addr) \
. += sz;
#endif
#ifdef __ROMSTAGE__
#define ROMSTAGE(addr, sz) \
SET_COUNTER(romstage, addr) \
_ = ASSERT(_eromstage - _romstage <= sz, \
STR(Romstage exceeded its allotted size! (sz))); \
INCLUDE "lib/romstage.romstage.ld"
#else
#define ROMSTAGE(addr, sz) \
SET_COUNTER(romstage, addr) \
. += sz;
#endif
#ifdef __RAMSTAGE__
#define RAMSTAGE(addr, sz) \
SET_COUNTER(ramstage, addr) \
_ = ASSERT(_eramstage - _ramstage <= sz, \
STR(Ramstage exceeded its allotted size! (sz))); \
INCLUDE "lib/ramstage.ramstage.ld"
#else
#define RAMSTAGE(addr, sz) \
SET_COUNTER(ramstage, addr) \
. += sz;
#endif
#endif /* __MEMLAYOUT_H */

76
src/include/symbols.h Normal file
View file

@ -0,0 +1,76 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
*/
#ifndef __SYMBOLS_H
#define __SYMBOLS_H
#include <types.h>
extern u8 _sram[];
extern u8 _esram[];
#define _sram_size (_esram - _sram)
extern u8 _dram[];
extern u8 _preram_cbmem_console[];
extern u8 _epreram_cbmem_console[];
#define _preram_cbmem_console_size \
(_epreram_cbmem_console - _preram_cbmem_console)
extern u8 _stack[];
extern u8 _estack[];
#define _stack_size (_estack - _stack)
extern u8 _cbfs_cache[];
extern u8 _ecbfs_cache[];
#define _cbfs_cache_size (_ecbfs_cache - _cbfs_cache)
extern u8 _payload[];
extern u8 _epayload[];
#define _payload_size (_epayload - _payload)
/* Careful: _e<stage> and _<stage>_size only defined for the current stage! */
extern u8 _bootblock[];
extern u8 _ebootblock[];
#define _bootblock_size (_ebootblock - _bootblock)
extern u8 _romstage[];
extern u8 _eromstage[];
#define _romstage_size (_eromstage - _romstage)
extern u8 _ramstage[];
extern u8 _eramstage[];
#define _ramstage_size (_eramstage - _ramstage)
/* "program" always refers to the current execution unit, except for x86 ROM. */
extern u8 _program[];
extern u8 _eprogram[];
#define _program_size (_eprogram - _program)
/* Arch-specific, move to <arch/symbols.h> if they become too many. */
extern u8 _ttb[];
extern u8 _ettb[];
#define _ttb_size (_ettb - _ttb)
extern u8 _dma_coherent[];
extern u8 _edma_coherent[];
#define _dma_coherent_size (_edma_coherent - _dma_coherent)
#endif /* __SYMBOLS_H */

8
src/lib/Makefile.inc
View file

@ -117,6 +117,14 @@ ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += ramstage_cache.c
ifneq ($(CONFIG_ARCH_X86),y)
# X86 bootblock and romstage use custom ldscripts that are all glued together,
# so we need to exclude it here or it would pick these up as well
bootblock-y += bootblock.ld
romstage-y += romstage.ld
endif
ramstage-y += ramstage.ld
smm-y += cbfs.c memcmp.c
smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c

48
src/lib/bootblock.ld Normal file
View file

@ -0,0 +1,48 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This file is included inside a SECTIONS block */
.bootblock . : {
_program = .;
_bootblock = .;
*(.text._start);
*(.text.stage_entry);
KEEP(*(.id));
*(.text);
*(.text.*);
*(.rodata);
*(.rodata.*);
*(.data);
*(.data.*);
*(.bss);
*(.bss.*);
*(.sbss);
*(.sbss.*);
_ebootblock = .;
_eprogram = .;
} : to_load = 0xff
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
*(.ARM.*)
}

5
src/lib/cbfs_spi.c
View file

@ -25,6 +25,7 @@
#include <cbfs.h>
#include <spi_flash.h>
#include <symbols.h>
/* SPI flash as CBFS media. */
struct cbfs_spi_context {
@ -80,8 +81,8 @@ static int init_cbfs_media_context(void)
if (!spi_context.spi_flash_info)
return -1;
spi_context.buffer.buffer = (void *)CONFIG_CBFS_CACHE_ADDRESS;
spi_context.buffer.size = CONFIG_CBFS_CACHE_SIZE;
spi_context.buffer.buffer = (void *)_cbfs_cache;
spi_context.buffer.size = _cbfs_cache_size;
}
return 0;

8
src/lib/cbmem_console.c
View file

@ -20,6 +20,7 @@
#include <console/console.h>
#include <cbmem.h>
#include <arch/early_variables.h>
#include <symbols.h>
#include <string.h>
/*
@ -40,11 +41,9 @@ static struct cbmem_console *cbmem_console_p CAR_GLOBAL;
/*
* While running from ROM, before DRAM is initialized, some area in cache as
* ram space is used for the console buffer storage. The size and location of
* the area are defined in the config.
* the area are defined by the linker script with _(e)preram_cbmem_console.
*/
extern struct cbmem_console preram_cbmem_console;
/*
* Once DRAM is initialized and the cache as ram mode is disabled, while still
* running from ROM, the console buffer in the cache as RAM area becomes
@ -121,8 +120,7 @@ static inline void init_console_ptr(void *storage, u32 total_space)
void cbmemc_init(void)
{
#ifdef __PRE_RAM__
init_console_ptr(&preram_cbmem_console,
CONFIG_CONSOLE_PRERAM_BUFFER_SIZE);
init_console_ptr(_preram_cbmem_console, _preram_cbmem_console_size);
#else
/*
* Initializing before CBMEM is available, use static buffer to store

114
src/lib/ramstage.ld Normal file
View file

@ -0,0 +1,114 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This file is included inside a SECTIONS block */
/* First we place the code and read only data (typically const declared).
* This could theoretically be placed in rom.
*/
.text : {
_program = .;
_ramstage = .;
_text = .;
*(.text._start);
*(.text.stage_entry);
*(.text);
*(.text.*);
. = ALIGN(16);
_etext = .;
} : to_load
#ifdef CONFIG_COVERAGE
.ctors : {
. = ALIGN(0x100);
__CTOR_LIST__ = .;
KEEP(*(.ctors));
LONG(0);
LONG(0);
__CTOR_END__ = .;
}
#endif
/* TODO: align data sections to cache lines? (is that really useful?) */
.rodata : {
_rodata = .;
. = ALIGN(8);
/* If any changes are made to the driver start/symbols or the
* section names the equivalent changes need to made to
* rmodule.ld. */
console_drivers = .;
KEEP(*(.rodata.console_drivers));
econsole_drivers = . ;
. = ALIGN(8);
pci_drivers = . ;
KEEP(*(.rodata.pci_driver));
epci_drivers = . ;
cpu_drivers = . ;
KEEP(*(.rodata.cpu_driver));
ecpu_drivers = . ;
_bs_init_begin = .;
KEEP(*(.bs_init));
_bs_init_end = .;
*(.rodata)
*(.rodata.*)
/* kevinh/Ispiri - Added an align, because the objcopy tool
* incorrectly converts sections that are not long word aligned.
*/
. = ALIGN(8);
_erodata = .;
}
.data : {
/* Move to different cache line to avoid false sharing with .rodata. */
. = ALIGN(64); /* May not be actual line size, not that important. */
_data = .;
*(.data)
*(.data.*)
_edata = .;
}
.bss . : {
_bss = .;
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
_ebss = .;
}
.heap . : {
_heap = .;
/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
. += CONFIG_HEAP_SIZE ;
. = ALIGN(4);
_eheap = .;
_eramstage = .;
_eprogram = .;
}
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.note.*)
}

10
src/lib/rmodule.ld
View file

@ -20,18 +20,21 @@ SECTIONS
.payload : {
/* C code of the module. */
_ram_seg = .;
*(.textfirst);
_program = .;
*(.text._start);
*(.text.stage_entry);
*(.text);
*(.text.*);
/* C read-only data. */
. = ALIGN(16);
#ifdef CONFIG_COVERAGE
__CTOR_LIST__ = .;
*(.ctors);
LONG(0);
LONG(0);
__CTOR_END__ = .;
#endif
/* The driver sections are to allow linking coreboot's
* ramstage with the rmodule linker. Any changes made in
@ -68,6 +71,7 @@ SECTIONS
. = ALIGN(8);
/* Data section. */
. = ALIGN(64); /* Mirror cache line alignment from ramstage. */
_sdata = .;
*(.data);
*(.data.*);
@ -95,7 +99,7 @@ SECTIONS
_heap = .;
. = . + __heap_size;
_eheap = .;
_eram_seg = .;
_eprogram = .;
}
/DISCARD/ : {

58
src/lib/romstage.ld Normal file
View file

@ -0,0 +1,58 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This file is included inside a SECTIONS block */
.text . : {
_program = .;
_romstage = .;
*(.text._start);
*(.text.stage_entry);
*(.text);
*(.text.*);
} : to_load
.data . : {
*(.rodata);
*(.rodata.*);
*(.data);
*(.data.*);
. = ALIGN(8);
}
.bss . : {
. = ALIGN(8);
_bss = .;
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
_ebss = .;
_eromstage = .;
_eprogram = .;
}
/* Discard the sections we don't need/want */
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
*(.eh_frame);
}

9
src/lib/selfboot.c
View file

@ -27,6 +27,7 @@
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <symbols.h>
#include <cbfs.h>
#include <lib.h>
#if CONFIG_COLLECT_TIMESTAMPS
@ -38,12 +39,8 @@
#define MAX_ADDR -1UL
#endif
/* from ramstage.ld: */
extern unsigned char _ram_seg;
extern unsigned char _eram_seg;
static const unsigned long lb_start = (unsigned long)&_ram_seg;
static const unsigned long lb_end = (unsigned long)&_eram_seg;
static const unsigned long lb_start = (unsigned long)&_program;
static const unsigned long lb_end = (unsigned long)&_eprogram;
struct segment {
struct segment *next;

60
src/mainboard/emulation/foundation-armv8/Kconfig
View file

@ -50,34 +50,6 @@ config DRAM_SIZE_MB
int
default 1024
# Memory map for Foundation v2 model
# Reference: ARM v8-A Foundation Model User Guide
#
# 0x00_0000_0000 - 0x00_03FF_FFFF Trusted Boot ROM
# 0x00_0400_0000 - 0x00_0403_FFFF Trusted SRAM
# 0x00_0600_0000 - 0x00_07FF_FFFF Trusted DRAM
# 0x00_1C01_0000 - 0x00_1C01_FFFF System Registers
# 0x00_1C09_0000 - 0x00_1C09_FFFF UART0 (PL011)
# 0x00_2E00_0000 - 0x00_2E00_FFFF Non-trusted SRAM
# 0x00_8000_0000 - 0x00_FFFF_FFFF DRAM (0GB - 2GB)
# 0x08_8000_0000 - 0x09_FFFF_FFFF DRAM (2GB - 8GB)
config BOOTBLOCK_BASE
hex
default 0x0
config ID_SECTION_BASE
hex
default 0x1f000
config ROMSTAGE_BASE
hex
default 0x4000000
config ROMSTAGE_SIZE
hex
default 0x20000
config BOOTBLOCK_ROM_OFFSET
hex
default 0x0
@ -90,36 +62,4 @@ config CBFS_ROM_OFFSET
hex
default 0x0110000
config IRAM_STACK
hex
default 0x0007ff00
config XIP_ROM_SIZE
hex
default ROMSTAGE_SIZE
config SYS_SDRAM_BASE
hex "SDRAM base address"
default 0x80000000
config SYS_TEXT_BASE
hex "Executable code section"
default 0x04e00000
config RAMBASE
hex
default SYS_SDRAM_BASE
config RAMTOP
hex
default 0x81000000
config STACK_TOP
hex
default 0x90000000
config STACK_SIZE
hex
default 0x00010000
endif # BOARD_EMULATION_FOUNDATION_ARMV8

4
src/mainboard/emulation/foundation-armv8/Makefile.inc
View file

@ -25,3 +25,7 @@ ramstage-y += timer.c
bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c
romstage-$(CONFIG_EARLY_CONSOLE) += uart.c
ramstage-y += uart.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

5
src/mainboard/emulation/foundation-armv8/mainboard.c
View file

@ -15,13 +15,14 @@
#include <console/console.h>
#include <device/device.h>
#include <symbols.h>
static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Enable foundation/armv8 device...\n");
ram_resource(dev, 0, CONFIG_RAMBASE / KiB,
(CONFIG_RAMTOP - CONFIG_RAMBASE) / KiB);
ram_resource(dev, 0, (uintptr_t)_dram / KiB,
(uintptr_t)_dram / KiB + CONFIG_DRAM_SIZE_MB * KiB);
}
struct chip_operations mainboard_ops = {

3
src/mainboard/emulation/foundation-armv8/media.c
View file

@ -14,6 +14,7 @@
*/
#include <cbfs.h>
#include <string.h>
#include <symbols.h>
#include <console/console.h>
/* Simple memory-mapped ROM emulation. */
@ -24,7 +25,7 @@ static int emu_rom_open(struct cbfs_media *media) {
static void *emu_rom_map(struct cbfs_media *media,
size_t offset, size_t count) {
return (void*)(offset + CONFIG_BOOTBLOCK_BASE);
return (void*)(offset + _bootblock);
}
static void *emu_rom_unmap(struct cbfs_media *media, const void *address) {

51
src/mainboard/emulation/foundation-armv8/memlayout.ld Normal file
View file

@ -0,0 +1,51 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <memlayout.h>
#include <arch/header.ld>
/*
* Memory map for Foundation v2 model
* Reference: ARM v8-A Foundation Model User Guide
*
* 0x00_0000_0000 - 0x00_03FF_FFFF Trusted Boot ROM
* 0x00_0400_0000 - 0x00_0403_FFFF Trusted SRAM
* 0x00_0600_0000 - 0x00_07FF_FFFF Trusted DRAM
* 0x00_1C01_0000 - 0x00_1C01_FFFF System Registers
* 0x00_1C09_0000 - 0x00_1C09_FFFF UART0 (PL011)
* 0x00_2E00_0000 - 0x00_2E00_FFFF Non-trusted SRAM
* 0x00_8000_0000 - 0x00_FFFF_FFFF DRAM (0GB - 2GB)
* 0x08_8000_0000 - 0x09_FFFF_FFFF DRAM (2GB - 8GB)
*/
SECTIONS
{
/* ROM_START(0x00000000) */
BOOTBLOCK(0x00000000, 32K)
/* ROM_END(0x04000000) */
SRAM_START(0x04000000)
ROMSTAGE(0x04000000, 128K)
SRAM_END(0x04030000)
DRAM_START(0x80000000)
RAMSTAGE(0x80000000, 128K)
STACK(0x90000000, 16K)
}

35
src/mainboard/emulation/qemu-armv7/Kconfig
View file

@ -50,45 +50,10 @@ config MAINBOARD_VENDOR
string
default "ARM Ltd."
config SYS_SDRAM_BASE
hex "SDRAM base address"
default 0x01000000
config DRAM_SIZE_MB
int
default 1024
# Memory map for qemu vexpress-a9:
#
# 0x0000_0000: jump instruction (by qemu)
# 0x0001_0000: bootblock (entry of kernel / firmware)
# 0x0002_0000: romstage, assume up to 128KB in size.
# 0x0007_ff00: stack pointer
# 0x0010_0000: CBFS header
# 0x0011_0000: CBFS data
# 0x0100_0000: reserved for ramstage
# 0x1000_0000: I/O map address
#
config STACK_TOP
hex
default 0x00100000
config STACK_BOTTOM
hex
default 0x0007FF00
config BOOTBLOCK_BASE
hex
default 0x00010000
config ROMSTAGE_BASE
hex
default 0x00020000
config RAMSTAGE_BASE
hex
default SYS_SDRAM_BASE
config BOOTBLOCK_ROM_OFFSET
hex
default 0x0

4
src/mainboard/emulation/qemu-armv7/Makefile.inc
View file

@ -25,3 +25,7 @@ ramstage-y += timer.c
bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c
romstage-$(CONFIG_EARLY_CONSOLE) += uart.c
ramstage-y += uart.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

3
src/mainboard/emulation/qemu-armv7/media.c
View file

@ -14,6 +14,7 @@
*/
#include <cbfs.h>
#include <string.h>
#include <symbols.h>
#include <console/console.h>
/* Simple memory-mapped ROM emulation. */
@ -25,7 +26,7 @@ static int emu_rom_open(struct cbfs_media *media)
static void *emu_rom_map(struct cbfs_media *media, size_t offset, size_t count)
{
return (void*)(offset + CONFIG_BOOTBLOCK_BASE);
return (void*)(offset + _bootblock);
}
static void *emu_rom_unmap(struct cbfs_media *media, const void *address)

47
src/mainboard/emulation/qemu-armv7/memlayout.ld Normal file
View file

@ -0,0 +1,47 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <memlayout.h>
#include <arch/header.ld>
/*
* Memory map for qemu vexpress-a9:
*
* 0x0000_0000: jump instruction (by qemu)
* 0x0001_0000: bootblock (entry of kernel / firmware)
* 0x0002_0000: romstage, assume up to 128KB in size.
* 0x0007_ff00: stack pointer
* 0x0010_0000: CBFS header
* 0x0011_0000: CBFS data
* 0x0100_0000: reserved for ramstage
* 0x1000_0000: I/O map address
*/
SECTIONS
{
/* TODO: does this thing emulate SRAM? */
BOOTBLOCK(0x10000, 64K)
ROMSTAGE(0x20000, 128K)
STACK(0x000FC000, 16K)
DRAM_START(0x01000000)
RAMSTAGE(0x01000000)
}

4
src/mainboard/google/daisy/Makefile.inc
View file

@ -25,3 +25,7 @@ romstage-y += wakeup.c
ramstage-y += mainboard.c
ramstage-y += chromeos.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

14
src/mainboard/google/daisy/mainboard.c
View file

@ -36,20 +36,17 @@
#include <soc/samsung/exynos5250/dp.h>
#include <soc/samsung/exynos5250/periph.h>
#include <soc/samsung/exynos5250/usb.h>
#include <symbols.h>
#include "exynos5250.h"
#define MMC0_GPIO_PIN (58)
/* convenient shorthand (in MB) */
#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
#define DRAM_START ((uintptr_t)_dram/MiB)
#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */
/* Arbitrary range of DMA memory for depthcharge's drivers */
#define DMA_START (0x77300000)
#define DMA_SIZE (0x00100000)
static struct edid edid = {
.ha = 1366,
.va = 768,
@ -333,7 +330,8 @@ static void mainboard_enable(device_t dev)
mmu_init();
mmu_config_range(0, DRAM_START, DCACHE_OFF);
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
_dma_coherent_size/MiB, DCACHE_OFF);
mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
dcache_mmu_enable();
@ -359,6 +357,6 @@ void lb_board(struct lb_header *header)
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (intptr_t)DMA_START;
dma->range_size = DMA_SIZE;
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = _dma_coherent_size;
}

1
src/mainboard/google/daisy/memlayout.ld Normal file
View file

@ -0,0 +1 @@
#include <soc/samsung/exynos5250/memlayout.ld>

8
src/mainboard/google/nyan/Kconfig
View file

@ -42,14 +42,6 @@ config MAINBOARD_PART_NUMBER
string
default "Nyan"
config DRAM_DMA_START
hex
default 0x90000000
config DRAM_DMA_SIZE
hex
default 0x00200000
choice
prompt "BCT boot media"
default NYAN_BCT_CFG_SPI

4
src/mainboard/google/nyan/Makefile.inc
View file

@ -40,3 +40,7 @@ romstage-y += early_configs.c
ramstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += mainboard.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

5
src/mainboard/google/nyan/mainboard.c
View file

@ -30,6 +30,7 @@
#include <soc/nvidia/tegra124/pmc.h>
#include <soc/nvidia/tegra124/spi.h>
#include <soc/nvidia/tegra/usb.h>
#include <symbols.h>
#include <vendorcode/google/chromeos/chromeos.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
@ -268,6 +269,6 @@ void lb_board(struct lb_header *header)
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = CONFIG_DRAM_DMA_START;
dma->range_size = CONFIG_DRAM_DMA_SIZE;
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = _dma_coherent_size;
}

1
src/mainboard/google/nyan/memlayout.ld Normal file
View file

@ -0,0 +1 @@
#include <soc/nvidia/tegra124/memlayout.ld>

24
src/mainboard/google/nyan/romstage.c
View file

@ -40,6 +40,7 @@
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/display.h>
#include <symbols.h>
#include <timestamp.h>
static void __attribute__((noinline)) romstage(void)
@ -54,24 +55,25 @@ static void __attribute__((noinline)) romstage(void)
sdram_init(get_sdram_config());
/* used for MMU and CBMEM setup, in MB */
u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
u32 dram_end = sdram_max_addressable_mb(); /* plus one... */
u32 dram_size = dram_end - dram_start;
u32 dram_start_mb = (uintptr_t)_dram/MiB;
u32 dram_end_mb = sdram_max_addressable_mb();
u32 dram_size_mb = dram_end_mb - dram_start_mb;
configure_l2_cache();
mmu_init();
/* Device memory below DRAM is uncached. */
mmu_config_range(0, dram_start, DCACHE_OFF);
/* SRAM is cached. Round the size up to 2MB, the LPAE page size. */
mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK);
mmu_config_range(0, dram_start_mb, DCACHE_OFF);
/* SRAM is cached. MMU code will round size up to page size. */
mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB),
DCACHE_WRITEBACK);
/* DRAM is cached. */
mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK);
/* A window for DMA is uncached. */
mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
_dma_coherent_size/MiB, DCACHE_OFF);
/* The space above DRAM is uncached. */
if (dram_end < 4096)
mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
if (dram_end_mb < 4096)
mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF);
mmu_disable_range(0, 1);
dcache_mmu_enable();

8
src/mainboard/google/nyan_big/Kconfig
View file

@ -44,14 +44,6 @@ config MAINBOARD_PART_NUMBER
string
default "Nyan Big"
config DRAM_DMA_START
hex
default 0x90000000
config DRAM_DMA_SIZE
hex
default 0x00200000
choice
prompt "BCT boot media"
default NYAN_BIG_BCT_CFG_SPI

4
src/mainboard/google/nyan_big/Makefile.inc
View file

@ -39,3 +39,7 @@ romstage-y += early_configs.c
ramstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += mainboard.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

5
src/mainboard/google/nyan_big/mainboard.c
View file

@ -30,6 +30,7 @@
#include <soc/nvidia/tegra124/pmc.h>
#include <soc/nvidia/tegra124/spi.h>
#include <soc/nvidia/tegra/usb.h>
#include <symbols.h>
#include <vendorcode/google/chromeos/chromeos.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
@ -266,6 +267,6 @@ void lb_board(struct lb_header *header)
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = CONFIG_DRAM_DMA_START;
dma->range_size = CONFIG_DRAM_DMA_SIZE;
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = _dma_coherent_size;
}

1
src/mainboard/google/nyan_big/memlayout.ld Normal file
View file

@ -0,0 +1 @@
#include <soc/nvidia/tegra124/memlayout.ld>

24
src/mainboard/google/nyan_big/romstage.c
View file

@ -40,6 +40,7 @@
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/display.h>
#include <symbols.h>
#include <timestamp.h>
static void __attribute__((noinline)) romstage(void)
@ -54,24 +55,25 @@ static void __attribute__((noinline)) romstage(void)
sdram_init(get_sdram_config());
/* used for MMU and CBMEM setup, in MB */
u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
u32 dram_end = sdram_max_addressable_mb(); /* plus one... */
u32 dram_size = dram_end - dram_start;
u32 dram_start_mb = (uintptr_t)_dram/MiB;
u32 dram_end_mb = sdram_max_addressable_mb();
u32 dram_size_mb = dram_end_mb - dram_start_mb;
configure_l2_cache();
mmu_init();
/* Device memory below DRAM is uncached. */
mmu_config_range(0, dram_start, DCACHE_OFF);
/* SRAM is cached. Round the size up to 2MB, the LPAE page size. */
mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK);
mmu_config_range(0, dram_start_mb, DCACHE_OFF);
/* SRAM is cached. MMU code will round size up to page size. */
mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB),
DCACHE_WRITEBACK);
/* DRAM is cached. */
mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK);
/* A window for DMA is uncached. */
mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
_dma_coherent_size/MiB, DCACHE_OFF);
/* The space above DRAM is uncached. */
if (dram_end < 4096)
mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
if (dram_end_mb < 4096)
mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF);
mmu_disable_range(0, 1);
dcache_mmu_enable();

8
src/mainboard/google/nyan_blaze/Kconfig
View file

@ -44,14 +44,6 @@ config MAINBOARD_PART_NUMBER
string
default "Nyan Blaze"
config DRAM_DMA_START
hex
default 0x90000000
config DRAM_DMA_SIZE
hex
default 0x00200000
choice
prompt "BCT boot media"
default NYAN_BLAZE_BCT_CFG_SPI

5
src/mainboard/google/nyan_blaze/Makefile.inc
View file

@ -43,3 +43,8 @@ romstage-y += sdram_configs.c
ramstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += mainboard.c
bootblock-y += memlayout.ld
verstage-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

5
src/mainboard/google/nyan_blaze/mainboard.c
View file

@ -30,6 +30,7 @@
#include <soc/nvidia/tegra124/pmc.h>
#include <soc/nvidia/tegra124/spi.h>
#include <soc/nvidia/tegra/usb.h>
#include <symbols.h>
#include <vendorcode/google/chromeos/chromeos.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
@ -266,6 +267,6 @@ void lb_board(struct lb_header *header)
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = CONFIG_DRAM_DMA_START;
dma->range_size = CONFIG_DRAM_DMA_SIZE;
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = _dma_coherent_size;
}

1
src/mainboard/google/nyan_blaze/memlayout.ld Normal file
View file

@ -0,0 +1 @@
#include <soc/nvidia/tegra124/memlayout.ld>

24
src/mainboard/google/nyan_blaze/romstage.c
View file

@ -40,6 +40,7 @@
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/display.h>
#include <symbols.h>
#include <timestamp.h>
static void __attribute__((noinline)) romstage(void)
@ -55,29 +56,30 @@ static void __attribute__((noinline)) romstage(void)
sdram_init(get_sdram_config());
/* used for MMU and CBMEM setup, in MB */
u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
u32 dram_end = sdram_max_addressable_mb(); /* plus one... */
u32 dram_size = dram_end - dram_start;
u32 dram_start_mb = (uintptr_t)_dram/MiB;
u32 dram_end_mb = sdram_max_addressable_mb();
u32 dram_size_mb = dram_end_mb - dram_start_mb;
#if !CONFIG_VBOOT2_VERIFY_FIRMWARE
configure_l2_cache();
mmu_init();
/* Device memory below DRAM is uncached. */
mmu_config_range(0, dram_start, DCACHE_OFF);
/* SRAM is cached. Round the size up to 2MB, the LPAE page size. */
mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK);
mmu_config_range(0, dram_start_mb, DCACHE_OFF);
/* SRAM is cached. MMU code will round size up to page size. */
mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB),
DCACHE_WRITEBACK);
/* The space above DRAM is uncached. */
if (dram_end < 4096)
mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
if (dram_end_mb < 4096)
mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF);
mmu_disable_range(0, 1);
dcache_mmu_enable();
#endif
/* DRAM is cached. */
mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK);
/* A window for DMA is uncached. */
mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
_dma_coherent_size/MiB, DCACHE_OFF);
/*
* A watchdog reset only resets part of the system so it ends up in

4
src/mainboard/google/peach_pit/Makefile.inc
View file

@ -25,3 +25,7 @@ romstage-y += wakeup.c
ramstage-y += mainboard.c
ramstage-y += chromeos.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

14
src/mainboard/google/peach_pit/mainboard.c
View file

@ -40,15 +40,12 @@
#include <drivers/parade/ps8625/ps8625.h>
#include <ec/google/chromeec/ec.h>
#include <stdlib.h>
#include <symbols.h>
/* convenient shorthand (in MB) */
#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
#define DRAM_START ((uintptr_t)_dram/MiB)
#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
/* Arbitrary range of DMA memory for depthcharge's drivers */
#define DMA_START (0x77300000)
#define DMA_SIZE (0x00100000)
static struct edid edid = {
.ha = 1366,
.va = 768,
@ -469,7 +466,8 @@ static void mainboard_enable(device_t dev)
/* set up caching for the DRAM */
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
_dma_coherent_size/MiB, DCACHE_OFF);
const unsigned epll_hz = 192000000;
const unsigned sample_rate = 48000;
@ -493,6 +491,6 @@ void lb_board(struct lb_header *header)
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (intptr_t)DMA_START;
dma->range_size = DMA_SIZE;
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = _dma_coherent_size;
}

1
src/mainboard/google/peach_pit/memlayout.ld Normal file
View file

@ -0,0 +1 @@
#include <soc/samsung/exynos5420/memlayout.ld>

4
src/mainboard/google/rush/Makefile.inc
View file

@ -40,3 +40,7 @@ romstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-y += reset.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

1
src/mainboard/google/rush/memlayout.ld Normal file
View file

@ -0,0 +1 @@
#include <soc/nvidia/tegra132/memlayout.ld>

4
src/mainboard/google/rush_ryu/Makefile.inc
View file

@ -40,3 +40,7 @@ romstage-y += sdram_configs.c
ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-y += reset.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

1
src/mainboard/google/rush_ryu/memlayout.ld Normal file
View file

@ -0,0 +1 @@
#include <soc/nvidia/tegra132/memlayout.ld>

8
src/mainboard/google/storm/Kconfig
View file

@ -48,12 +48,4 @@ config DRAM_SIZE_MB
default 512 if BOARD_VARIANT_AP148
default 1024
config DRAM_DMA_START
hex
default 0x5a000000
config DRAM_DMA_SIZE
hex
default 0x00200000
endif # BOARD_GOOGLE_STORM

3
src/mainboard/google/storm/Makefile.inc
View file

@ -27,3 +27,6 @@ ramstage-y += boardid.c
ramstage-y += cdp.c
ramstage-y += mainboard.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

11
src/mainboard/google/storm/mainboard.c
View file

@ -25,19 +25,20 @@
#include <device/device.h>
#include <gpiolib.h>
#include <string.h>
#include <symbols.h>
#include <soc/qualcomm/ipq806x/include/clock.h>
#include <soc/qualcomm/ipq806x/include/gpio.h>
#include <soc/qualcomm/ipq806x/include/usb.h>
/* convenient shorthand (in MB) */
#define DRAM_START (CONFIG_SYS_SDRAM_BASE / MiB)
#define DRAM_START ((uintptr_t)_dram / MiB)
#define DRAM_SIZE (CONFIG_DRAM_SIZE_MB)
#define DRAM_END (DRAM_START + DRAM_SIZE)
/* DMA memory for drivers */
#define DMA_START (CONFIG_DRAM_DMA_START / MiB)
#define DMA_SIZE (CONFIG_DRAM_DMA_SIZE / MiB)
#define DMA_START ((uintptr_t)_dma_coherent / MiB)
#define DMA_SIZE (_dma_coherent_size / MiB)
#define USB_ENABLE_GPIO 51
@ -134,8 +135,8 @@ void lb_board(struct lb_header *header)
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = CONFIG_DRAM_DMA_START;
dma->range_size = CONFIG_DRAM_DMA_SIZE;
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = _dma_coherent_size;
}
#define FAKE_GPIO_NUM -1

1
src/mainboard/google/storm/memlayout.ld Normal file
View file

@ -0,0 +1 @@
#include <soc/qualcomm/ipq806x/memlayout.ld>

4
src/mainboard/google/urara/Kconfig
View file

@ -38,10 +38,6 @@ config MAINBOARD_PART_NUMBER
string
default "ImgTec Pistachio Virtual Platform"
config SYS_SDRAM_BASE
hex "SDRAM base address"
default 0x80000000
config DRAM_SIZE_MB
int
default 256

3
src/mainboard/google/urara/Makefile.inc
View file

@ -21,3 +21,6 @@
ramstage-y += mainboard.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

1
src/mainboard/google/urara/memlayout.ld Normal file
View file

@ -0,0 +1 @@
#include <soc/imgtec/pistachio/memlayout.ld>

8
src/mainboard/google/veyron_pinky/Kconfig
View file

@ -60,14 +60,6 @@ config BOOT_MEDIA_SPI_BUS
hex
default 2
config DRAM_DMA_START
hex
default 0x10000000
config DRAM_DMA_SIZE
hex
default 0x00200000
config DRAM_SIZE_MB
int
default 2048

5
src/mainboard/google/veyron_pinky/Makefile.inc
View file

@ -34,3 +34,8 @@ ramstage-y += boardid.c
ramstage-y += chromeos.c
ramstage-y += mainboard.c
ramstage-y += reset.c
bootblock-y += memlayout.ld
verstage-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

5
src/mainboard/google/veyron_pinky/mainboard.c
View file

@ -22,6 +22,7 @@
#include <arch/cache.h>
#include <delay.h>
#include <edid.h>
#include <symbols.h>
#include <vbe.h>
#include <boot/coreboot_tables.h>
#include <device/i2c.h>
@ -153,6 +154,6 @@ void lb_board(struct lb_header *header)
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = CONFIG_DRAM_DMA_START;
dma->range_size = CONFIG_DRAM_DMA_SIZE;
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = _dma_coherent_size;
}

1
src/mainboard/google/veyron_pinky/memlayout.ld Normal file
View file

@ -0,0 +1 @@
#include <soc/rockchip/rk3288/memlayout.ld>

19
src/mainboard/google/veyron_pinky/romstage.c
View file

@ -34,6 +34,7 @@
#include <soc/rockchip/rk3288/clock.h>
#include <soc/rockchip/rk3288/pwm.h>
#include <soc/rockchip/rk3288/grf.h>
#include <symbols.h>
#include "timer.h"
static void regulate_vdd_log(unsigned int mv)
@ -64,9 +65,9 @@ void main(void)
start_romstage_time = timestamp_get();
#endif
/* used for MMU and CBMEM setup, in MB */
u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
u32 dram_size = CONFIG_DRAM_SIZE_MB;
u32 dram_end = dram_start + dram_size;
u32 dram_start_mb = (uintptr_t)_dram/MiB;
u32 dram_size_mb = CONFIG_DRAM_SIZE_MB;
u32 dram_end_mb = dram_start_mb + dram_size_mb;
console_init();
@ -81,15 +82,15 @@ void main(void)
#endif
mmu_init();
/* Device memory below DRAM is uncached. */
mmu_config_range(0, dram_start, DCACHE_OFF);
mmu_config_range(0, dram_start_mb, DCACHE_OFF);
/* DRAM is cached. */
mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK);
/* A window for DMA is uncached. */
mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
_dma_coherent_size/MiB, DCACHE_OFF);
/* The space above DRAM is uncached. */
if (dram_end < 4096)
mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
if (dram_end_mb < 4096)
mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF);
dcache_mmu_enable();
cbmem_initialize_empty();

31
src/soc/imgtec/pistachio/Kconfig
View file

@ -35,40 +35,9 @@ config BOOTBLOCK_CPU_INIT
string
default "soc/imgtec/pistachio/bootblock.c"
config BOOTBLOCK_BASE
hex
default 0x9b000000
config CBFS_ROM_OFFSET
# Effectively the maximum size of the bootblock
hex
default 0x4000
config ROMSTAGE_BASE
hex
default 0x9b004000
help
The address where romstage is supposed to be loaded, right above the
bootblock.
config CBMEM_CONSOLE_PRERAM_BASE
hex "memory address of the CBMEM console buffer"
default 0x9b00f800
help
Allocate 4KB to the pre-ram console buffer, we should be able to use
GRAM eventually and have a much larger buffer.
config BOOTBLOCK_STACK_BOTTOM
hex
default 0x9b00e000
help
This allocates 6KB of stack space. One needs to verify that this is
sufficient.
config BOOTBLOCK_STACK_TOP
hex
default CBMEM_CONSOLE_PRERAM_BASE
help
Bootblock stack starts immediately under the CBMEM console buffer,
stack location might be changed by ro stage.
endif

2
src/soc/imgtec/pistachio/Makefile.inc
View file

@ -51,5 +51,5 @@ $(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
# Create a complete bootblock which will start up the system
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw $(BIMGTOOL)
@printf " BIMGTOOL $(subst $(obj)/,,$(@))\n"
$(BIMGTOOL) $< $@ $(CONFIG_BOOTBLOCK_BASE)
$(BIMGTOOL) $< $@ $(call loadaddr,bootblock)

38
src/soc/imgtec/pistachio/memlayout.ld Normal file
View file

@ -0,0 +1,38 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <memlayout.h>
#include <arch/header.ld>
/* TODO: This should be revised by someone who understands the SoC better. */
SECTIONS
{
CBFS_CACHE(0x0, 0) /* TODO: fix this, it was already broken before!!! */
DRAM_START(0x80000000)
RAMSTAGE(0x80000000, 128K)
/* TODO: Does this SoC use SRAM? Add SRAM_START() and SRAM_END(). */
BOOTBLOCK(0x9B000000, 16K)
ROMSTAGE(0x9B004000, 40K)
STACK(0x9B00E000, 6K)
PRERAM_CBMEM_CONSOLE(0x9B00F800, 3K)
}

92
src/soc/nvidia/tegra124/Kconfig
View file

@ -26,35 +26,6 @@ config BOOTBLOCK_CPU_INIT
bootblock must load microcode or copy data from ROM before
searching for the bootblock.
# ROM image layout.
#
# 0x00000 Combined bootblock and BCT blob
# 0x18000 Master CBFS header.
# 0x18080 Free for CBFS data.
#
# iRAM (256k) layout.
# (Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
# so the bootblock loading address must be placed after that. After the
# handoff that area may be reclaimed for other uses, e.g. CBFS cache.)
#
# 0x4000_0000 TTB (16K+32B). 32B is for L1 table of LPAE.
# 0x4000_4020 CBMEM console area (8K-32B)
# 0x4000_6000 CBFS mapping cache (88K)
# 0x4001_C000 Stack (16KB... don't reduce without comparing LZMA scratchpad!).
# 0x4002_0000 Bootblock (max 48KB).
# 0x4002_C000 ROM stage (max 80KB).
# 0x4003_FFFF End of iRAM.
#
# if VBOOT2_VERIFY_FIRMWARE,
# 0x4000_0000 TTB (16K+32B). 32B is for L1 table of LPAE.
# 0x4000_4020 CBMEM console area (8K-32B)
# 0x4000_6000 CBFS mapping cache (72K)
# 0x4001_8000 vboot work buffer (16K)
# 0x4001_C000 Stack (16KB... don't reduce without comparing LZMA scratchpad!).
# 0x4002_0000 bootblock and romstage (max 70KB).
# 0x4003_1000 verstage (max 60KB).
# 0x4003_FFFF End of iRAM.
config BOOTBLOCK_ROM_OFFSET
hex
default 0x0
@ -67,69 +38,6 @@ config CBFS_ROM_OFFSET
hex "offset of CBFS data in ROM"
default 0x18080
config SYS_SDRAM_BASE
hex
default 0x80000000
config BOOTBLOCK_BASE
hex
default 0x40020000
# this has to be big enough to leave room big enough for the larger of the
# bootblock and the romstage.
config VERSTAGE_BASE
hex
default 0x40031000
# with vboot2, romstage is loaded over to the bootblock space
config ROMSTAGE_BASE
hex
default 0x40020000 if VBOOT2_VERIFY_FIRMWARE
default 0x4002c000
config RAMSTAGE_BASE
hex
default 0x80200000
config STACK_TOP
hex
default 0x40020000
config STACK_BOTTOM
hex
default 0x4001c000
# This is the ramstage thread stack, *not* the same as above! Currently unused.
config STACK_SIZE
hex
default 0x800
# TTB needs to be aligned to 16KB. Stick it in iRAM.
config TTB_BUFFER
hex "memory address of the TTB buffer"
default 0x40000000
config CBFS_CACHE_ADDRESS
hex "memory address to put CBFS cache data"
default 0x40006000
config CBFS_CACHE_SIZE
hex "size of CBFS cache data"
default 0x00012000 if VBOOT2_VERIFY_FIRMWARE
default 0x00016000
config VBOOT_WORK_BUFFER_ADDRESS
hex "memory address of vboot work buffer"
default 0x40018000
config VBOOT_WORK_BUFFER_SIZE
hex "size of vboot work buffer"
default 0x00004000
config CBMEM_CONSOLE_PRERAM_BASE
hex "memory address of the CBMEM console buffer"
default 0x40004020
choice CONSOLE_SERIAL_TEGRA124_UART_CHOICES
prompt "Serial Console UART"
default CONSOLE_SERIAL_UARTA

2
src/soc/nvidia/tegra124/Makefile.inc
View file

@ -103,6 +103,6 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BCT_BIN)
echo "Version = 1;" > $(BCT_WRAPPER)
echo "Redundancy = 1;" >> $(BCT_WRAPPER)
echo "Bctfile = $(BCT_BIN);" >> $(BCT_WRAPPER)
echo "BootLoader = $<,$(CONFIG_BOOTBLOCK_BASE),$(CONFIG_BOOTBLOCK_BASE),Complete;" >> $(BCT_WRAPPER)
echo "BootLoader = $<,$(call loadaddr,bootblock),$(call loadaddr,bootblock),Complete;" >> $(BCT_WRAPPER)
@printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n"
$(CBOOTIMAGE) $(BCT_WRAPPER) $@

20
src/soc/nvidia/tegra124/bootblock_asm.S
View file

@ -44,10 +44,8 @@ ENTRY(_start)
* Initialize the stack to a known value. This is used to check for
* stack overflow later in the boot process.
*/
ldr r0, .Stack
ldr r1, .Stack_size
sub r0, r0, r1
ldr r1, .Stack
ldr r0, =_stack
ldr r1, =_estack
ldr r2, =0xdeadbeef
init_stack_loop:
str r2, [r0]
@ -57,7 +55,7 @@ init_stack_loop:
/* Set stackpointer in internal RAM to call bootblock main() */
call_bootblock:
ldr sp, .Stack /* Set up stack pointer */
ldr sp, =_estack /* Set up stack pointer */
ldr r0,=0x00000000
/*
* The current design of cpu_info places the
@ -75,15 +73,3 @@ call_bootblock:
*/
bl main
ENDPROC(_start)
/* we do it this way because it's a 32-bit constant and
* in some cases too far away to be loaded as just an offset
* from IP
*/
.align 2
.Stack:
.word CONFIG_STACK_TOP
.align 2
/* create this size the same way we do in ramstage.ld: top-bottom */
.Stack_size:
.word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM

4
src/soc/nvidia/tegra124/cbfs.c
View file

@ -19,12 +19,12 @@
#include <cbfs.h> /* This driver serves as a CBFS media source. */
#include <symbols.h>
#include "spi.h"
int init_default_cbfs_media(struct cbfs_media *media)
{
return initialize_tegra_spi_cbfs_media(media,
(void*)CONFIG_CBFS_CACHE_ADDRESS,
CONFIG_CBFS_CACHE_SIZE);
_cbfs_cache, _cbfs_cache_size);
}

3
src/soc/nvidia/tegra124/clock.c
View file

@ -20,6 +20,7 @@
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <stdlib.h>
#include <symbols.h>
#include <arch/clock.h>
#include "clk_rst.h"
#include "flow.h"
@ -485,7 +486,7 @@ void clock_cpu0_config(void *entry)
{
void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100;
write32(CONFIG_STACK_TOP, &maincpu_stack_pointer);
write32((uintptr_t)_estack, &maincpu_stack_pointer);
write32((uintptr_t)entry, &maincpu_entry_point);
write32((uintptr_t)&maincpu_setup, evp_cpu_reset);

48
src/soc/nvidia/tegra124/memlayout.ld Normal file
View file

@ -0,0 +1,48 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <memlayout.h>
#include <vendorcode/google/chromeos/memlayout.h>
#include <arch/header.ld>
/*
* Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
* so the bootblock loading address must be placed after that. After the
* handoff that area may be reclaimed for other uses, e.g. CBFS cache.
*/
SECTIONS
{
SRAM_START(0x40000000)
TTB(0x40000000, 16K + 32)
PRERAM_CBMEM_CONSOLE(0x40004020, 8K - 32)
PRERAM_CBFS_CACHE(0x40006000, 16K)
VBOOT2_WORK(0x4000A000, 16K)
STACK(0x4000E000, 8K)
BOOTBLOCK(0x40010000, 24K)
VERSTAGE(0x40016000, 72K)
ROMSTAGE(0x40028000, 96K)
SRAM_END(0x40040000)
DRAM_START(0x80000000)
POSTRAM_CBFS_CACHE(0x80100000, 1M)
RAMSTAGE(0x80200000, 128K)
DMA_COHERENT(0x90000000, 2M)
}

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