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tegra132: remove framebuffer reservation

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There's no need to reserve the framebuffer within corebot. If the
payloads need a framebuffer they can allocate one themselves.

BUG=chrome-os-partner:31355
BRANCH=None
TEST=Built and booted on ryu.

Change-Id: I8d8b159e7fdd877e392193c5474a7518e9b3ad21
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221726
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Aaron Durbin 2014-10-07 16:16:48 -05:00 • committed by chrome-internal-fetch
commit 1ff8da9fed
5 changed files with 13 additions and 36 deletions
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15
src/soc/nvidia/tegra132/addressmap.c
View file

@ -22,7 +22,6 @@
#include <stdlib.h>
#include <console/console.h>
#include <soc/addressmap.h>
#include <soc/display.h>
#include <soc/id.h>
#include <symbols.h>
#include "mc.h"
@ -167,20 +166,6 @@ void memory_in_range_above_4gb(uintptr_t *base_mib, uintptr_t *end_mib)
memory_in_range(base_mib, end_mib, 0);
}
uintptr_t framebuffer_attributes(size_t *size_mib)
{
uintptr_t begin;
uintptr_t end;
/* Place the framebuffer just below the 32-bit addressable limit. */
memory_in_range_below_4gb(&begin, &end);
*size_mib = FB_SIZE_MB;
end -= *size_mib;
return end;
}
void trustzone_region_init(void)
{
struct tegra_mc_regs * const mc = (void *)(uintptr_t)TEGRA_MC_BASE;

22
src/soc/nvidia/tegra132/cbmem.c
View file

@ -23,18 +23,18 @@
void *cbmem_top(void)
{
static uintptr_t addr;
size_t fb_size;
/*
* FIXME(adurbin): The TZ registers are not accessible to the AVP.
* Therefore, if there is a TZ carveout then it needs to be handled
* here while executing on the AVP in order to properly place the
* CBMEM region.
*/
if (addr == 0) {
uintptr_t begin_mib;
uintptr_t end_mib;
/* CBMEM starts downwards from the framebuffer. */
if (addr == 0)
addr = framebuffer_attributes(&fb_size);
memory_in_range_below_4gb(&begin_mib, &end_mib);
/* Make sure we consume everything up to 4GIB. */
if (end_mib == 4096)
addr = ~(uint32_t)0;
else
addr = end_mib << 20;
}
return (void *)(addr << 20UL);
return (void *)addr;
}

3
src/soc/nvidia/tegra132/include/soc/addressmap.h
View file

@ -130,7 +130,4 @@ void mainboard_add_memory_ranges(struct memranges *map);
*/
void trustzone_region_init(void);
/* Return pointer and size in 1MiB units. */
uintptr_t framebuffer_attributes(size_t *size_mib);
#endif /* __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ADDRESS_MAP_H__ */

2
src/soc/nvidia/tegra132/include/soc/display.h
View file

@ -197,6 +197,4 @@ void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr,
u32 lane_count, u32 enhanced_framing, u32 panel_edp,
u32 pclkfreq, u32 linkfreq);
#define FB_SIZE_MB (32)
#endif /* __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_DISPLAY_H__ */

7
src/soc/nvidia/tegra132/soc.c
View file

@ -37,8 +37,8 @@
static void soc_read_resources(device_t dev)
{
unsigned long index = 0;
int i; uintptr_t begin, end, framebuffer_begin;
size_t size, framebuffer_size;
int i; uintptr_t begin, end;
size_t size;
for (i = 0; i < CARVEOUT_NUM; i++) {
carveout_range(i, &begin, &size);
@ -47,9 +47,6 @@ static void soc_read_resources(device_t dev)
reserved_ram_resource(dev, index++, begin * KiB, size * KiB);
}
framebuffer_begin = framebuffer_attributes(&framebuffer_size);
//TODO: Frame buffer needs to handled as a carveout from the below_4G
memory_in_range_below_4gb(&begin, &end);
size = end - begin;
ram_resource(dev, index++, begin * KiB, size * KiB);