BUG=None
TEST=builds
BRANCH=None
Change-Id: I163730e45cc18f125e32a1b4c5a685b3a1861486
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/175220
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The elog boot counter in cmos was not being initialized
nor incremented. Start doing that in romstage. Since S3
resume is not detected yet the increment is unconditional.
BUG=None
BRANCH=None
TEST=Built and booted through depthcharge multiple times. Noted
output such as 'Boot Count incremented to 4'.
Change-Id: Ic585d4ad4b3af086e0067e28fe0f35c02979bbd2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174717
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The ACPI code was previously complaining about not being able
to find the GNVS area: 'ACPI: Could not find CBMEM GNVS'. Fix
this by adding GNVS area early in start up. This is also the
appropriate place to set the acpi_slp_type variable to indicate
an S3 resume or not.
BUG=chrome-os-partner:22867
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted through depthcharge. Noted cbmem has 'ACPI GNVS'
entry.
Change-Id: Ifbca3dd390ebe573730ee204ca4c2f19626dd6b1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174647
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The callers of the following functions assume the storage
area provided by the pointers is initialized. That's not the
case as these were just place holders.
- void acpi_create_intel_hpet(acpi_hpet_t * hpet);
- void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
To fix this properly initialize the hpet entry, and just remove
the serialio_ssdt function entirely.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted through depthcharge on rambi. Noted no more
ACPI errors relating to invalid length.
Change-Id: If56ab033562ef2d755e9c9de42f507c95d291aba
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174716
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The EC LPC init function needs to run to enable the internal keyboard.
I needed this to confirm that it is just USB keyboards that are causing
all sorts of issues.
BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=boot to recovery screen and hit tab
Change-Id: Iea0fc66ba62ea7da71ef83c26e25ae32bef102bd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175207
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is essentially a direct port of CL:174505. It sets the EHCI
controllers Tx FIFO threshold setting to the recommended value for HOST
mode, which seems to help prevent FIFO underruns between the memory/AHB
and the host controller. This is necessary to get larger OUT transfers
to work, but there are still a few more general clock changes
concerning other AHB problems needed before they will really be usable.
BUG=None
TEST=None
Change-Id: I12783ba0a986678715d42e3d798756fa3d1ad690
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175200
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Enable first SATA port in Rambi device tree.
BUG=chrome-os-partner:23643
TEST=TEST=Manual, in dev mode. Verify on rambi that SATA disk is
detected, and kernel is found + booted.
Change-Id: Ic0cb5f9ff17ca0f6cc7941f203b9338df200811d
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174916
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add SATA driver for baytrail platform.
BUG=chrome-os-partner:23643
TEST=Manual, in dev mode. Verify on rambi that SATA disk is detected, and
kernel is found + booted.
Change-Id: I5c13e03203c8f26d233c7d10af8ff6812c460578
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174914
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Right now, firmware changes are rejected if the HWTest or VMTest
stages fail. This is unnecessary as firmware changes are very unlikely
to break these stages.
BUG=chromium:285940
TEST=Run it with my CL to ignore HWTest and VMTest
Change-Id: I4910b45df4c0a53f7d198f8f48454921d0198d7f
Reviewed-on: https://chromium-review.googlesource.com/175016
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aviv Keshet <akeshet@chromium.org>
Reviewed-by: Scott Zawalski <scottz@chromium.org>
Commit-Queue: David James <davidjames@chromium.org>
Tested-by: David James <davidjames@chromium.org>
Reviewed-by: Matt Tennant <mtennant@chromium.org>
This configuration change enables the running of reference code for
bayleybay.
BUG=chrome-os-partner:22580
BRANCH=None
TEST=manual
. built and noted output of reference code debug information. The
eMMC device driver (not yet in the code base) is working reliably
after several reboots and power cycles, indicating that the PLL
initialization code is kicking in.
Change-Id: I426baa46a72a567f54a00dc00321ee4227531eff
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175077
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the on-board devices in the SoC to the device tree.
Also, disable the unused devices aside from TXE and HDA.
Those particular devices cause the system to shut down
when they are disabled.
BUG=chrome-os-partner:22871
BRANCH=None
TEST=Built and booted through depthcharge. Noted the calls to the
southcluster disable function.
Change-Id: I482c1c9609833054aeb2948144af54b57d3df086
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174645
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
When the southcluster pci devices are listed in the devicetree add
the ability to perform the proper disabling seqence for turning
off devices. This only turns off the pci device interface as well
as put the device into D3Hot. It is not yet know how to put the TXE
device into D3Hot so it's currently not possible to disable that
device.
Also, expose the southcluster_enable_dev() function so that other
devices can call this if they require doing specific things before
disabling the device. The southcluster_enable_dev() is only called
on devices found in the devicetree and if they currently have no
ops associated with them.
BUG=chrome-os-partner:22871
BRANCH=None
TEST=Built and booted through depthcharge. Interrogated
output to ensure devices were being properly disabled.
Change-Id: I537ddcb9379907af2fe012948542b6150a8bf7c5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174644
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The dump_td() debug function in the EHCI stack incorrectly masks the
amount of transferred bytes on output... the actual field is 15 bits
wide (30:16). Let's just use the mask constant we already have for all
the other code.
BUG=None
TEST=None
Change-Id: I28c6f0ec75cc613e38d53b670645d19bf9ffe1b9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174986
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
There is nothing attached to these devices so we can disable
them as well as the function 0 DMA controller.
Also remove the EC SMI/SCI mappings since there is no EC.
(panther port of Iedfe711058676f7ee118b0b66ab0f8a1e792ea87)
BUG=chrome-os-partner:23563
TEST=none
BRANCH=panther
Change-Id: Ie66f9b66744db98f8638495c05f3a075b6fa6db9
Reviewed-on: https://chromium-review.googlesource.com/174944
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@chromium.org>
Tested-by: Mohammed Habibulla <moch@chromium.org>
Fan is attached to port 2 instead of 3.
(panther port of I9878063a24b0b908c74522580f776a4ce7d03d75)
BUG=chrome-os-partner:23563
TEST=none
BRANCH=panther
Change-Id: I028e0e5a748fa0a20d34e27e870e14ed8c75e4d1
Reviewed-on: https://chromium-review.googlesource.com/174984
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@chromium.org>
Tested-by: Mohammed Habibulla <moch@chromium.org>
Before I start moving things around I'm just cleaning house.
I'm so used to graphics exploding that I like to take it easy.
BUG=None
TEST=builds and boots to linux, with a dev screen on the way
BRANCH=None
Change-Id: I195520aa02ea82adf9e1d2befddc0528f5d15978
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/174995
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Add in register defines for PLLDP (I assume the display port PLL)
and SOR source 1 and 2 registers.
BUG=None
TEST=builds and boots to Linux
BRANCH=None
Change-Id: Ie629f81529f33a2d9be4b4e590ceca8cd3e9327b
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/174948
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
This patch adds the required bits and pieces to get USB set up correctly
for EHCI controllers with UTMI+ PHYs.
BUG=None
TEST=None
Change-Id: I89406ffa25fa96778965f8f1572fad8a74f10844
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174651
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
FixedIO seems like a nice short version of IO but in reality
it is limited to 10-bit ISA addresses and so should not really
be used in most situations.
Change all the references to use IO() directly instead.
BUG=chromium:311294
BRANCH=none
TEST=emerge-samus chromeos-coreboot-samus and check for iasl
warnings using updated iasl compiler revision 20130117.
Boot the imge and ensure that EC regions are still exported
in /proc/ioports.
Change-Id: I54de65892bed9e43dbba916990cf2b70c370843c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174810
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
The CBFS core checks the result of a media->map() operation in multiple
places for CBFS_MEDIA_INVALID_MAP_ADDRESS, suggesting that this is a
valid response. However, it ironically fails to do so when actually
mapping the CBFS file itself, which can fail on buffer-constrained
systems since the size is much larger than when mapping metadata. This
patch adds a check with an error message and a NULL pointer return for
that case to make it easier to understand this condition.
BUG=None
TEST=None
Change-Id: Icae3dd20d3d111cdfc4f2dc6397b52174349b140
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174951
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
I ran into this limit when trying to boot a netboot image with some
debugging output (guess those are bigger, not so sure why). We aren't
that constrained on this system so there's no harm in increasing it a
little (and there shouldn't be anything in that memory region since the
stack is still a bit higher, right)?
BUG=None
TEST=None
Change-Id: I11f12170c2c586f29bb9ad8d6301a6a1501e0813
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174950
Reviewed-by: Gabe Black <gabeblack@chromium.org>
While most registers accesses don't need the use of the MCRX
register (upper 24 bits of address) the MCRX register should
be protected. The reference code could be doing accesses to
registers that initlaized the MCRX register. Thus, any access
after that should ensure the MCRX register is initialized
appropriately.
BUG=None
BRANCH=None
TEST=Verified assembly output. Also, built and booted through
depthcharge.
Change-Id: I4d6cfbe6bb1666790c69778b8f2c8baeaf015264
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174643
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
We are currently running out of MTRRs with this CPU when
marking the graphics memory as write-combining. The reason
is that the graphics stolen memory was bumped to 64MiB which
changes the address space enough that the MTRRs are exhausted.
BUG=None
BRANCH=None
TEST=Built and analyzed MTRR usage. Also noted clearing upper
2GiB of memory in depthcharge does not take forever.
Change-Id: I2eb0168990a5c585605f958e1cbc9ec1a2322d1d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174653
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This was unfortunately put exactly where depthcharge wants to run. I must have
consistently thought "this should be far enough away from everything" and put
them in exactly the same spot.
BUG=None
TEST=With this change and Julius's USB changes, saw that depthcharge was no
longer broken by setting up the USB controllers.
BRANCH=None
Change-Id: I3a44a24d609879b0db046e1e9bc949378f52be94
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/174953
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This uses VBIOS release 1004 and the binary lives in the
private overlay.
BUG=chrome-os-partner:23507
BRANCH=rambi
TEST=build and boot to dev screen via HDMI on rambi
Change-Id: I88273b54d77f001a028b87fa66591963d6d83dac
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174923
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Ungate display in PUNIT
- Set GSM to 64MB since 32MB is not supported in <C0 stepping
- Initialize power management registers in GTT
- Execute VBIOS if found
BUG=chrome-os-partner:23507
BRANCH=rambi
TEST=build and boot to dev screen via HDMI on rambi
Change-Id: Idb032c7ea7f16b651b4c921e3429a652fe663a5d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174922
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The data needs to be available in the register before the control
bits are set to make the write happen.
BUG=chrome-os-partner:23507
BRANCH=rambi
TEST=successfully ungate power on PUNIT on rambi
Change-Id: I8fae60d5385ce9a401c1dec9cbb39b70d157a6c2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174898
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Changes to standard includes and files to define constants
and prototypes. Code from nvidia that turns on the display,
with lots of changes for coreboot.
With this code, which is going to be cleaned up, we get a display
in coreboot and depthcharge.
BUG=None
TEST=Builds, boots, and displays a color bar pattern from coreboot. Depthcharge
starts up, and we see the dev mode scary screen, just in time for Halloween.
BRANCH=None
Change-Id: I0eada9a7386e6f623cf8708144b0f6e850e97d50
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/174613
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
This speeds up execution but does require cache management in drivers.
BUG=None
TEST=Built and booted into depthcharge on nyan. Measured a speed up in
execution.
BRANCH=None
Change-Id: I7efe6af2c38e41402fa874ed59798f136e7e8ad4
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/173777
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The names are a bit wordy, and can be changed later if we wish.
BUG=None
TEST=Builds
BRANCH=None
Change-Id: I1c716afcc2871a3cb0697d1af855af380a9d3bca
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/174612
Tested-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
This adds support for finding a frame header in the input stream.
If a frame header is enabled, then the input buffer is scanned after
each iteration of the outer loop. If the header is found, the bytes
are shifted to the beginning of the buffer and the counter is
decremented so that if necessary another iteration can take place
with the remaining byte count.
This allows us to always transfer the maximum number of bytes.
BUG=none
BRANCH=none
TEST=tested on nyan, querying EC actually works now
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I5827b386fc372ee6768403f5a8bb86f7c680e523
Reviewed-on: https://chromium-review.googlesource.com/174711
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
This sets frame header information for CrOS EC so that the
SPI driver knows what to look for.
BUG=none
BRANCH=none
TEST=tested on nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I2af67292c2d448d06418b4f4f8bee7b103ab6e38
Reviewed-on: https://chromium-review.googlesource.com/174710
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
This re-factors tegra_spi_init() to return a pointer to a channel
struct. This allows the caller to modify configurable parameters
(namely frame header).
It's not exactly the most elegant interface, but it allows us to
set device-specific parameters from mainboard-specific code and
avoid making assumptions about board configuration in the SoC code.
It also avoids adding function args that are meaningless most of
the time.
BUG=none
BRANCH=none
TEST=tested on nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ibf7d315b54b1c23f19d7421713acb8d58b8e22c0
Reviewed-on: https://chromium-review.googlesource.com/174639
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
This adds a frame header byte and an enable switch to the
SPI channel struct. The current use case is so that mainboard
code can set the frame header for the CrOS EC.
BUG=none
BRANCH=none
TEST=tested on nyan (with follow-up CLs)
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I844ebfcb6fbf16b2fc7f775086f2803e026f9d08
Reviewed-on: https://chromium-review.googlesource.com/174638
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
This moves Tegra SPI-related structs from the source file to the
header. This will allow higher-level code to tinker with some
low-level SPI settings.
BUG=none
BRANCH=none
TEST=tested on nyan with follow-up CLs
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ic22c0e89203e88d92a4800ca429fd48ff163bcf5
Reviewed-on: https://chromium-review.googlesource.com/174637
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
This basically re-writes the SPI driver. It started out as several
large patches, but it seemed simpler to just squash those which
touched many of the same lines of code.
The first major change is that full duplexing is enabled. The first
version of the driver could only send or receive at once, but not
both.
The second major change is that alignment for DMA transfers is checked
so that the front and tail of each transaction buffer is checked for
alignment. PIO mode is used for bytes that are unaligned.
Third, this adds cache maintanence for DMA operations. Before starting
a DMA transaction, the aligned portion of the buffer will be cleaned
(Tx) or cleaned and invalidated (Rx).
Since this patch ended up re-writing huge swaths of code, a few
cosmetic changes were made along the way such as replacing "fifo"
with "pio" in functions names and such.
BUG=none
BRANCH=none
TEST=built and booted into depthcharge on nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I384b321a390898013c089e40c0e573dbb6aacea2
Reviewed-on: https://chromium-review.googlesource.com/174446
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
As rambi has the ChromeOS EC on it the EC needs to
be configured properly. Do this along with updating the
ChromeOS support for passing on write protect state, recovery
mode and developer mode.
BUG=chrome-os-partner:23387
BRANCH=None
TEST=Built and booted to depthcharge. EC software sync appears to
work correctly. Additionaly, 'mainboard_ec_init' appears in
the console output.
Change-Id: I40c5c9410b4acaba662c2b18b261dd4514a7410a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174714
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The EC needs to be initialized early in romstage. Therefore
perform the call after console has been initialized in order to
view any messages that the code may spit out.
BUG=chrome-os-partner:23387
BRANCH=None
TEST=Built and booted with recovery mode and EC in RW. Noted that
system reboots the EC.
Change-Id: I35aa3ea4aa3dbd9bd806b6498e227f45ceebd7a1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174713
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
First, use the _set and _clr versions of the clk_enb and rst_dev registers to
avoid having to both read and write to clear or set bits. Also, check to see
if we're actually trying to set or clear bits before writing into those
registers.
BUG=None
TEST=Built and booted on Nyan.
BRANCH=None
Change-Id: If3e5a0401bef7888e6af6395dd480901d25fdf09
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/174845
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
If we don't need the clocks or function units to get out of bootblock and onto
the main CPUs running rom stage, we can move that code to later where it might
be updated if/when we get early firmware selection going.
BUG=None
TEST=Built and booted on nyan.
BRANCH=None
Change-Id: Id4a77c24fe9f362a45d267c5f78808472c789e67
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/174844
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
BUG=None
TEST=Built and booted into depthcharge. Saw that the AP could communicate with
the EC over SPI.
BRANCH=None
Change-Id: Ib19a8e543a96a0614a97afc6e795496b1bdfc8b4
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/173954
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Version 2 of the efi wrapper wants the speed of the TSC
timer initialized in the parameter structure.
BUG=chrome-os-partner:22866
BRANCH=None
TEST=Built and booted through depthcharge. No errors spit out by
wrapper.
CQ-DEPEND=CL:*147256
Change-Id: I9cd265ea6bde93be85fc6fbc905d83af57fc2773
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174712
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Before the special PUNIT settings the GFX pci device
had the same device id as the transaction router. This
required a special case in the transaction router's
driver to do the proper thing for read_resources().
However, that requirement is no longer needed as the
PUNIT special message is now being done. Therefore,
remove the work around.
BUG=None
BRANCH=None
TEST=Built and looked at resource allocation logs to confirm
work around is no longer needed.
Change-Id: I90b155cb5560ca3291f146c2f586456e5529f6b2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174652
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
There's been a bit of confusion on this and the book is not helpful.
BUG=None
TEST=Just a comment, building is sufficient and it builds.
BUG=None
Change-Id: I497fe387238196602d57f178ba40eb4998ec2877
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://chromium-review.googlesource.com/173910
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
The decision about what clocks and units to enable and what sources and
divisors to use had been configured in the tegra124 source, but really those
decisions need to be made on a mainboard to mainboard basis. This code keeps
some generic mechanism in the tegra124 directory but moves most of the rest of
it to the nyan directory.
It would be good to abstract the source and divisor setting functions a bit
more since that code is still pretty big, and requires knowledge of the clock
and reset controller and its constants and bitfields.
Also we should move code related to function units which aren't actually used
in the bootblock into later stages so they can be updated.
BUG=None
TEST=Built and booted on nyan.
BRANCH=None
Change-Id: Ied7ecceced3016f1fcb32101d780b7c235b881db
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/174843
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This could be done much sooner in the generic timer initialization, but it's
not used by coreboot and, if it's done in the RAM stage, it would be
updateable when using early firmware selection.
BUG=None
TEST=Before setting up these timers, the Linux kernel behaved very poorly and
would hang, trip the watchdog timer, and/or otherwise crash. After setting
them up those problems were no longer noticeable.
BRANCH=None
Change-Id: I26e9dc6d5090a67c775e67f96cee13fad582803e
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/174836
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The kernel knows how to use the ARM architectural timer in a generic way, but
some setup is needed which is specific to the implementation. The tegra code
in the kernel doesn't configure those parts so we need to, or the kernel
behaves poorly.
BUG=None
TEST=Before this change, the kernel would hang, the watch dog timer would go
off and kill the machine, and/or there would be random seeming crashes and
instability. After this change those problems were essentially gone.
BRANCH=None
Change-Id: Ibe0dccc964771b0a4a2376be9940192a4dfa6c43
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/174835
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
