PWM_Frequency_03 changes from 200Hz to 2kHz.
The 14-inch 1080p panel supports 190Hz to 2kHz, so use the panel's
safe maximum instead of the old 200Hz default.
Change-Id: Ibf21bf291fecfd2b10a74bb3667549ef2f271356
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
PWM_Frequency_03 changes from 200Hz to 10kHz.
The 14-inch 4K panel supports 100Hz to 10kHz, so raise the board VBT
value to the panel's safe maximum.
Change-Id: I94694d06e09d58f92966a2c827aad52f15e1e4c6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91868
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PWM_Frequency_03 changes from 200Hz to 10kHz.
The 12.5-inch 2K panel supports 100Hz to 10kHz, while the 12.5-inch
3K panel supports 200Hz to 25kHz. Keep the shared board VBT at 10kHz
until panel-specific selection exists.
Change-Id: Ia8bf5a324eb65698a8ba89b89cee8a9d10fba07d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91867
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PWM_Frequency_03 changes from 200Hz to 10kHz.
The HZ panel is validated at 10kHz, so use that known-good value in
the board VBT instead of the old 200Hz default.
Change-Id: Ieaddba9a7fef42be8de2cc64f234a39dde62c25f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Restore the HZ panel VBT minimum brightness for panel entry 03 to the reference value.
Post_Min_Brightness_03 changes from 0 to 25.
Change-Id: I04ae425a1377b4a716127a0624872b74fb3eb962
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Fix the StarBook 14-inch 1080p panel VBT timing values against the
panel datasheet for panel entry 03.
eDP_DataOn_To_BkltEnable_Delay_03 changes from 10 to 800.
eDP_BkltDisable_To_DataOff_Delay_03 changes from 2000 to 500.
eDP_DataOff_To_PowerOff_Delay_03 changes from 500 to 5000.
Change-Id: Ie153c6272595268565e1966b7d7773d4d068680c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91864
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the i5 panel VBT timing values against the panel datasheet for panel entry 03.
eDP_DataOn_To_BkltEnable_Delay_03 changes from 10 to 2000.
eDP_BkltDisable_To_DataOff_Delay_03 changes from 2000 to 500.
eDP_DataOff_To_PowerOff_Delay_03 changes from 500 to 4500.
Change-Id: I717be5863d0352224eae1053db77e8d3234a396f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Fix the StarBook 14-inch 4K panel VBT timing values against the panel
datasheet for panel entry 03.
eDP_DataOn_To_BkltEnable_Delay_03 changes from 10 to 500.
eDP_BkltDisable_To_DataOff_Delay_03 changes from 2000 to 500.
eDP_DataOff_To_PowerOff_Delay_03 changes from 500 to 4500.
Change-Id: I941e268f6a05f74248b19eb75fc7f07f781e347c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91862
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the StarFighter panel VBT timing values against the panel datasheets for panel entry 03.
eDP_DataOn_To_BkltEnable_Delay_03 changes from 10 to 500.
eDP_BkltDisable_To_DataOff_Delay_03 changes from 2000 to 500.
eDP_DataOff_To_PowerOff_Delay_03 changes from 500 to 5000.
Change-Id: I382a1609aa7fee082b172ed07c761a7655a56dd3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Fix the HZ panel VBT timing values against the panel datasheet for
panel entry 03.
eDP_DataOn_To_BkltEnable_Delay_03 changes from 10 to 800.
eDP_BkltDisable_To_DataOff_Delay_03 changes from 2000 to 500.
eDP_DataOff_To_PowerOff_Delay_03 changes from 500 to 5000.
Change-Id: Icc711c3c6f105cfd6fc1dc5bbab24d9b172a924f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91860
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
gnvs.c uses the global NVS definitions directly, so include
acpi/acpi_gnvs.h explicitly instead of relying on indirect headers.
Change-Id: Ifd19111a01ced3cb9bdb85ac192358e823dd3f44
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91857
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add MKBP support for zork devices, so that vivaldi keyboard works for
devices running upstream coreboot and MrChromebox ECRW firmware.
TEST=build/boot google/morphius, verify vivaldi keyboard mapping
functional under both Linux and Win11.
Change-Id: I021454b92cdb90e2a385eee1b3d4cc0438c75132
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Add MKBP support for reef devices, so that vivaldi keyboard works for
devices running upstream coreboot and MrChromebox ECRW firmware.
TEST=build/boot google/reef, verify vivaldi keyboard mapping functional
under both Linux and Win11.
Change-Id: If7a8df8469c22404e22d80fd4d116b862b6b5cec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91786
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add MKBP support for octopus devices, so that vivaldi keyboard works for
devices running upstream coreboot and MrChromebox ECRW firmware.
TEST=build/boot google/ampton, verify vivaldi keyboard mapping
functional under both Linux and Win11.
Change-Id: I31ecd87d8e9335dd4131f022370b32bf2d056b03
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Add MKBP support for hatch devices, so that vivaldi keyboard works for
devices running upstream coreboot and MrChromebox ECRW firmware.
TEST=build/boot google/akemi, verify vivaldi keyboard mapping functional
under both Linux and Win11.
Change-Id: I7bd222160efdd4de0d63ab9542c0d2828aac583a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Add MKBP support for glados devices, so that vivaldi keyboard works for
devices running upstream coreboot and MrChromebox ECRW firmware.
TEST=build/boot google/chell, verify vivaldi keyboard mapping functional
under both Linux and Win11.
Change-Id: Ia1ea5cdece52d33f7467af0b6e1d891a04b63b94
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Allocate resources to devices on the bus.
This booted to the fedora disk image using nvme with the CrabEFI payload.
Change-Id: I898b38fd4fa94f7d1a73132d6f821ff7c9e201dd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
cbfstool/flashmap/kv_pair.h uses the `__printf` macro. So we need to
include the header file defining `__printf` in the compilation.
The tooling can now be compiled on its own outside the coreboot build
system.
Change-Id: I5a622b50684c42773e66e6d9145d5de9858c9e9a
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91887
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Using a signed, non-fixed-width type for bitfields can cause problems.
So, use uint8_t since the affected bitfields occupy exactly one byte.
Change-Id: I728072b10baf77819a387df76b588b6a826e2841
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91855
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The CPUCP (CPU Control Processor) binary is currently stored
uncompressed in the RO region. To save space in the RO section
while maintaining fast boot performance in normal mode, split the
CPUCP CBFS entry into two distinct files:
1. cpucp_rw: Stored in FW_MAIN_A and FW_MAIN_B with no compression
for performance.
2. cpucp_ro: Stored in the COREBOOT (RO) region with LZMA
compression to save flash space.
Update the loading logic in cpucp_load_reset.c to select the
appropriate binary based on the current vboot mode (Normal vs.
Recovery).
BUG=None
TEST=Verified that CPUCP loads from 'cpucp_rw' during normal boot
and 'cpucp_ro' when vboot recovery is triggered.
Normal Mode:
```
[INFO ] CBFS: Found 'fallback/cpucp_rw' @0xc8640 size 0x79244
in mcache @0x8669d628
```
Recovery Mode:
```
[INFO ] CBFS: Found 'fallback/cpucp_ro' @0xc8640 size 0x79244
in mcache @0x8669d628
```
Change-Id: Iec5294beec4377b13f8b7354d86055d5907c6556
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This pulls in the following change from the submodule:
- add binaries for V2000A
Change-Id: I606f7926bcdef2a02ed1f492f37a0d7aefa27714
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91856
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
aarch64-elf nm doesn't support '--no-weak'. Replace the 'nm --no-weak'
call with 'grep' with "[TDRCB]" pattern to collect the non-weak
symbols.
Change-Id: I19195034b31f39086946b7e5ee15317d6f5dd880
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
On Faegan the FSP supports RAS. Allow the user to configure
RAS features and pass them to the FSP using UPDs.
Change-Id: Ia7091d216a446d56632e64f9bba0e2a166410139
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91819
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Create the dirkson variant of the dirks project by
copying the files to a new directory named for the variant.
BUG=b:494049087
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_DIRKSON
Change-Id: I7e1257ebe8292e00a282eb75535466dcb2b459eb
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
The TBMC ACPI device is used by Windows ChromeEC drivers to determine
tablet mode and to enable motion sensors (accelerometer, gyroscope).
Since it's not needed/used by ChromeOS, restrict its inclusion to
non-ChromeOS builds.
TEST=build/boot Win11/Linux on eldrid, verify tablet mode and rotation
work properly, keyboard/touchpad disabled in tablet mode.
Change-Id: I65832388649daceb498c91e6405d2b8343ca2aeb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
The TBMC ACPI device is used by Windows ChromeEC drivers to determine
tablet mode and to enable motion sensors (accelerometer, gyroscope).
Since it's not needed/used by ChromeOS, restrict its inclusion to
non-ChromeOS builds.
TEST=build/boot Win11/Linux on magolor, verify tablet mode and rotation
work properly, keyboard/touchpad disabled in tablet mode.
Change-Id: I6853465ba77be1f95cbe5795b318df02ecc1da39
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91798
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The TBMC ACPI device is used by Windows ChromeEC drivers to determine
tablet mode and to enable motion sensors (accelerometer, gyroscope).
Since it's not needed/used by ChromeOS, restrict its inclusion to
non-ChromeOS builds.
TEST=build/boot Win11/Linux on taeko, verify tablet mode and rotation
work properly, keyboard/touchpad disabled in tablet mode.
Change-Id: Ie26cd77c8a58034dbce05a1ab308b9dcc122484c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91797
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TMBC support has been backported to the EC firmware for CYAN
and KEFKA, so add SCI support for the MODE_CHANGE host event.
TEST=build/boot Win11, Linux on CYAN, verify tablet mode switching
functional via Intel VBTN driver.
Change-Id: Id3474e07bad1b6371644821dfe39a8105e4dd0f8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Set SYSTEM_TYPE_CONVERTIBLE for Volteer-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI (VBTN).
Set the default SYSTEM_TYPE for non-convertibles to LAPTOP as
is done for most newer ChromeOS boards.
Change-Id: I02337464953fdb654e99019af4d2f142e1910e97
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Set SYSTEM_TYPE_CONVERTIBLE for Reef-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI (VBTN).
Change-Id: Iff5c8379ff318a5616fee0133fef6f0ad9b93003
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Set SYSTEM_TYPE_CONVERTIBLE for Octopus-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI (VBTN).
Change-Id: I298fb413480f6392990d00dc375db4d1e4176d9d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Set SYSTEM_TYPE_CONVERTIBLE for Hatch-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI (VBTN).
Change-Id: I8b72efb176087dda29b1c32b7ceef4c4544ef4d7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91748
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set SYSTEM_TYPE_CONVERTIBLE for the CAROLINE variant so SMBIOS
reports a convertible enclosure type. This allows non-ChromeOS
builds to enable EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS and use
the vendor tablet mode ACPI.
Change-Id: I67429b34a197cb4f1e3938040b0b1853462796c3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Set SYSTEM_TYPE_CONVERTIBLE for Dedede-based Spin/Flip devices
so SMBIOS reports a convertible enclosure type. This enables
EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS on non-ChromeOS builds
and allows use of the vendor tablet mode ACPI (VBTN).
Adjust the system type check in mainboard_init() to account for
both laptops and convertibles.
Change-Id: I8cce636eb7e8ae6dfe16d6cd5004f463b5a7dd2d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91745
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set SYSTEM_TYPE_CONVERTIBLE for Brya 360/flip variants so SMBIOS
reports a convertible enclosure type. This allows non-ChromeOS
builds to enable EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS and use
the vendor tablet mode ACPI (VBTN).
Change-Id: I84bfd1df72d24b717f2b89906fd8dd2bef38d2b5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Introduce EC_CHROMEEC_USE_VENDOR_TABLET_CONTROLS to control inclusion of
Intel VBTN and AMD VGBI ACPI devices used for tablet/convertible mode.
Default is y for non-ChromeOS builds when the board selects
SYSTEM_TYPE_CONVERTIBLE or SYSTEM_TYPE_DETACHABLE.
Add vbtn.asl (Intel INT33D6/INT33D3) and vgbi.asl (AMD AMD33D6/AMD33D3).
In ec.asl, gate VBTN/VGBI notify and these includes on the new config.
Boards that are convertibles or detachables will enable the vendor
tablet controls by selecting the appropriate SMBIOS enclosure type in
subsequent changes.
Change-Id: I208c1f1856a9223af5109464ecf316e76de3a976
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91742
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
In scenarios where the system is booting with a critical or low battery,
lowering the initial CPU frequency helps reduce the instantaneous power
draw, ensuring the battery can sustain the boot process while fast
charging is being enabled.
Changes:
- clock.h: Replace 806MHz (0x2A) with 710.4MHz (0x25) based on 19.2MHz
XO.
- mainboard.c: Update handle_low_power_charging_boot() to use the
new L-VAL and update the debug log accordingly.
BUG=b:436391478
Change-Id: Ida30824e344a4613c797083711c3f6ee31f9694d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
During certain boot sequences, such as low-battery or off-mode charging,
automatic USB Type-C port resets initiated by the ADSP can cause
unnecessary power fluctuations or connectivity drops.
Implement adsp_skip_port_reset(), which toggles the SKIP_PORT_RESET bit
in the PMIC_PD_NEGOTIATION_FLAG register. This bit informs the ADSP
firmware to bypass its default port reset logic. Use this during
low-power charging initialization to ensure a more stable boot process.
BUG=b:436391478
TEST=Verify no unexpected port resets occur during Google/Quartz boot.
Change-Id: I215a1806799a10355dd36b483f8d441f615f5258
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91666
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support to drop the CPU frequency to the minimum
806 MHz when the device enters OFF‑mode charging, improving power
efficiency. The register details are available in the
HRD-X1P42100-S1 hardware document:
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
Tested by creating an image.serial.bin and verifying that it boots
on X1P42100 and the CPU runs at 806 MHz during OFF‑mode charging.
Change-Id: I8f0d5b598a4dad419195957be8b334a27ec18982
Signed-off-by: Kirubakaran E <kirue@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91727
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Load ADSP firmware and then bring up LPASS/Q6 during the Bluey charging sequence.
This ensures ADSP‑dependent fast charging works reliably.
TEST:
- Built and booted image.serial.bin on X1P42100.
- Verified ADSP DTB and firmware load over UART.
- Verified Q6 and LPASS init during cold boot.
- Verified charging flow: device entered charging mode, battery current (~3550 mA)
reported, and CRD RED LED glowed.
Change-Id: I6a1326f4271c5121cd7284d64b2912505b2a93a2
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91564
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add clock_disable() (clear CBCR EN and poll CLK_OFF).
Add CBCR helper APIs and common bit definitions for HW_CTL,
FORCE_MEM_CORE_ON, IGNORE_RPMH_CLK_DIS and IGNORE_PMU_CLK_DIS.
BUG=None
TEST=Built and booted image.serial.bin on Bluey
Change-Id: I253414d01ec97aee45df1af0ed8cd06367351ef8
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91546
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
To support chargers connected through a Debug Accessory Mode (DAM)
cable, the PMIC must be configured to allow legacy charging paths even
when a debug accessory is detected.
Update the charging initialization to clear the suspend bit in the
SCHG_TYPE_C_SUSPEND_LEGACY_CHARGERS register. This ensures the SMB2360
can correctly negotiate and draw power when a DAM cable is in use.
BUG=none
TEST=Verify SMB2360 charging configuration on Google/Quartz.
Change-Id: I8d22abf92f4e8967efbe2ee3320c4a1461d6ef88
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91832
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Boost the initial CPU frequency from 1.36GHz to ~3.0GHz (2995.2 MHz)
during the boot phase to reduce the execution time of ramstage
and subsequent payload loading.
Changes:
- clock.h: Add L_VAL_2995P2MHz (0x9C) based on a 19.2MHz XO.
- clock.c: Update speed_up_boot_cpu() to use the 3.0GHz PLL
multiplier for the APSS NCC0 clock.
This change helps in further optimizing the boot timeline,
leveraging the higher clock speed for faster initialization.
BUG=b:449871690
TEST=Able to save ~50ms of the boot time (mostly during Qclib).
Change-Id: I459001717298b10201c3b3c8bf6b0c20097ae830
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91818
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Allow the SoC the specify the cache speed. Currently it's
always set to 0, which is unknown.
Change-Id: I317e248104c0026b7cca10b949fd47fba35b7338
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
On Qualcomm SoCs, the initial TTB is often placed in IMEM. During
ROMSTAGE, once DRAM is initialized and stable, the tables should be
moved to DRAM to ensure they remain accessible if IMEM is reclaimed
by other hardware blocks (like the ADSP).
Trigger mmu_relocate_ttb() at the end of the post-DRAM MMU
configuration flow.
BUG=b:436391478
TEST=Verify TTB moves to DRAM on Google/Quartz.
Debug logs:
```
[INFO ] Relocating TTB: 0x14842000 -> 0x80010000 (offset 0x6b7ce000)
[INFO ] TTB relocation is complete.
```
Change-Id: I123385e6cdd319c5ad4d3e7b266c506e7d2d5530
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91565
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Generate RAM ID for Samsung K4UBE3D4AA-MGCR
DRAM Part Name ID to assign
K4UBE3D4AA-MGCR 1 (0001)
BUG=b:420797833
BRANCH=firmware-brya-14505.B
TEST=emerge-constitution coreboot then check device boot
Change-Id: I9751baeec16d460b4d2b0de9158940e785ccf0ef
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91681
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Generate RAM ID for SCY SL5D32G32C2A-HC0
DRAM Part Name ID to assign
SL5D32G32C2A-HC0 3 (0011)
BUG=b:438402880
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot then check device boot
Change-Id: I354b950022cf05f69546d4c3d29f05981512ce51
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91519
Reviewed-by: Kyle Lin <kylelinck@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
