smbios: Add smbios_cache_speed() implementation
Allow the SoC the specify the cache speed. Currently it's always set to 0, which is unknown. Change-Id: I317e248104c0026b7cca10b949fd47fba35b7338 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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2 changed files with 7 additions and 1 deletions
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@ -104,6 +104,7 @@ unsigned int smbios_processor_family(struct cpuid_result res);
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unsigned int smbios_cache_error_correction_type(u8 level);
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unsigned int smbios_cache_sram_type(void);
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unsigned int smbios_cache_conf_operation_mode(u8 level);
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u8 smbios_cache_speed(u8 level);
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/* Used by mainboard to add port information of type 8 */
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struct port_information;
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@ -445,6 +445,11 @@ unsigned int __weak smbios_cache_conf_operation_mode(u8 level)
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return SMBIOS_CACHE_OP_MODE_UNKNOWN; /* Unknown */
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}
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u8 __weak smbios_cache_speed(u8 level)
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{
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return 0; /* Unknown */
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}
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/* Returns the processor voltage in 100mV units */
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unsigned int __weak smbios_cpu_get_voltage(void)
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{
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@ -583,7 +588,7 @@ int smbios_write_type7(unsigned long *current,
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t->associativity = associativity;
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t->supported_sram_type = sram_type;
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t->current_sram_type = sram_type;
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t->cache_speed = 0; /* Unknown */
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t->cache_speed = smbios_cache_speed(level);
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t->error_correction_type = smbios_cache_error_correction_type(level);
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t->system_cache_type = type;
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